Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
big_delay 500 1 T56 1 T103 1 T560 1
small_delay 676 1 T54 1 T55 1 T59 1
zero 624 1 T491 1 T405 1 T225 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
big_delay 200 1 T56 1 T103 1 T560 1
small_delay 976 1 T54 1 T55 1 T59 1
zero 624 1 T491 1 T405 1 T225 1