Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	479	1			T509	1		T503	1		T494	1
all_values[1]	460	1			T497	2		T509	5		T644	1
all_values[2]	432	1			T59	1		T509	1		T493	1
all_values[3]	515	1			T59	1		T497	2		T509	6
all_values[4]	474	1			T509	3		T494	1		T495	3
all_values[5]	509	1			T497	3		T509	1		T495	2
all_values[6]	490	1			T59	1		T226	1		T509	6
all_values[7]	485	1			T59	2		T497	1		T509	2
all_values[8]	473	1			T226	1		T509	1		T494	1
all_values[9]	480	1			T59	1		T509	2		T514	2
all_values[10]	524	1			T59	1		T509	2		T514	1
all_values[11]	488	1			T509	3		T493	1		T797	1
all_values[12]	456	1			T59	1		T497	1		T509	2
all_values[13]	478	1			T495	2		T512	1		T505	7
all_values[14]	512	1			T59	1		T414	1		T497	1
all_values[15]	495	1			T497	3		T509	2		T505	4
all_values[16]	493	1			T59	2		T509	3		T514	1
all_values[17]	489	1			T226	1		T497	2		T495	5
all_values[18]	482	1			T59	1		T226	1		T497	1
all_values[19]	495	1			T509	2		T503	1		T514	1
all_values[20]	554	1			T59	1		T226	2		T509	4
all_values[21]	483	1			T497	2		T509	2		T493	2
all_values[22]	540	1			T59	3		T497	1		T509	6
all_values[23]	515	1			T509	1		T494	1		T644	1
all_values[24]	474	1			T497	1		T509	2		T493	1
all_values[25]	480	1			T497	2		T509	4		T503	1
all_values[26]	512	1			T509	1		T495	2		T504	1
all_values[27]	501	1			T59	3		T509	4		T644	1
all_values[28]	506	1			T59	3		T226	1		T497	1
all_values[29]	482	1			T494	1		T495	6		T504	1
all_values[30]	480	1			T509	1		T495	3		T504	1
all_values[31]	479	1			T59	2		T509	4		T514	3
all_values[32]	501	1			T59	1		T497	1		T493	1
all_values[33]	522	1			T509	1		T503	1		T495	4
all_values[34]	493	1			T509	2		T494	1		T644	1
all_values[35]	550	1			T59	1		T497	1		T509	3
all_values[36]	499	1			T414	1		T509	5		T503	1
all_values[37]	478	1			T59	1		T509	1		T495	2
all_values[38]	471	1			T509	1		T503	1		T495	3
all_values[39]	472	1			T226	1		T509	3		T495	1
all_values[40]	491	1			T497	1		T509	3		T495	1
all_values[41]	484	1			T59	1		T497	1		T509	5
all_values[42]	451	1			T509	1		T493	2		T495	2
all_values[43]	495	1			T509	3		T495	4		T504	1
all_values[44]	472	1			T509	2		T495	2		T505	6
all_values[45]	492	1			T59	1		T497	2		T509	2
all_values[46]	482	1			T59	2		T644	1		T495	2
all_values[47]	496	1			T509	6		T495	7		T504	1
all_values[48]	491	1			T509	2		T493	2		T495	1
all_values[49]	543	1			T59	1		T497	1		T509	3