Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3704	1			T59	2		T226	2		T414	3
all_values[1]	3740	1			T59	6		T226	3		T414	6
all_values[2]	3685	1			T59	6		T226	1		T414	3
all_values[3]	3673	1			T59	2		T414	6		T509	19
all_values[4]	3820	1			T59	6		T226	3		T414	8
all_values[5]	3688	1			T59	6		T414	6		T509	19
all_values[6]	3623	1			T59	7		T226	3		T509	15
all_values[7]	3673	1			T59	3		T226	3		T414	4
all_values[8]	3709	1			T226	3		T414	5		T509	23
all_values[9]	3651	1			T59	3		T226	3		T414	3
all_values[10]	3691	1			T59	2		T414	8		T509	22
all_values[11]	3692	1			T59	5		T226	2		T414	1
all_values[12]	3639	1			T59	5		T226	2		T414	2
all_values[13]	3641	1			T59	5		T226	2		T414	2
all_values[14]	3721	1			T59	4		T226	1		T414	3
all_values[15]	3604	1			T59	4		T226	5		T414	3
all_values[16]	3681	1			T59	6		T226	2		T414	2
all_values[17]	3644	1			T59	7		T226	2		T414	5
all_values[18]	3757	1			T59	4		T226	3		T414	2
all_values[19]	3619	1			T59	3		T226	3		T414	5
all_values[20]	3728	1			T59	2		T226	2		T414	5
all_values[21]	3770	1			T59	6		T226	3		T414	4
all_values[22]	3711	1			T59	7		T226	2		T414	2
all_values[23]	3625	1			T59	3		T226	3		T414	4
all_values[24]	3710	1			T59	13		T226	3		T414	1
all_values[25]	3819	1			T59	3		T414	2		T509	24
all_values[26]	3677	1			T59	7		T226	2		T414	3
all_values[27]	3669	1			T59	10		T226	2		T414	2
all_values[28]	3605	1			T59	6		T226	1		T414	3
all_values[29]	3678	1			T59	2		T226	1		T414	2
all_values[30]	3700	1			T226	3		T414	3		T509	16
all_values[31]	3580	1			T59	1		T226	1		T414	2
all_values[32]	3658	1			T59	3		T414	6		T509	26
all_values[33]	3724	1			T59	4		T226	1		T414	2
all_values[34]	3733	1			T59	4		T226	5		T414	5
all_values[35]	3770	1			T59	7		T226	1		T414	3
all_values[36]	3553	1			T59	10		T226	1		T414	4
all_values[37]	3750	1			T59	8		T226	1		T414	4
all_values[38]	3611	1			T59	6		T226	2		T414	2
all_values[39]	3727	1			T59	3		T226	2		T414	1
all_values[40]	3675	1			T59	5		T226	2		T414	2
all_values[41]	3652	1			T59	11		T226	1		T414	9
all_values[42]	3637	1			T59	8		T226	4		T414	3
all_values[43]	3702	1			T59	6		T226	2		T414	3
all_values[44]	3685	1			T59	6		T414	4		T509	10
all_values[45]	3655	1			T59	6		T226	4		T414	1
all_values[46]	3704	1			T59	5		T226	2		T414	3
all_values[47]	3847	1			T59	3		T226	1		T414	7
all_values[48]	3639	1			T59	7		T226	2		T414	3
all_values[49]	3666	1			T59	2		T414	3		T509	20
all_values[50]	3605	1			T59	2		T226	4		T414	7
all_values[51]	3753	1			T59	4		T226	4		T414	4
all_values[52]	3742	1			T59	3		T226	2		T414	1
all_values[53]	3697	1			T59	5		T226	1		T414	4
all_values[54]	3792	1			T59	5		T226	2		T414	4
all_values[55]	3731	1			T59	4		T226	3		T414	3
all_values[56]	3765	1			T59	4		T226	2		T414	1
all_values[57]	3720	1			T59	1		T226	1		T509	28
all_values[58]	3696	1			T59	5		T226	1		T509	28
all_values[59]	3677	1			T59	6		T226	1		T414	7
all_values[60]	3712	1			T59	3		T226	1		T414	1
all_values[61]	3792	1			T59	4		T226	4		T414	5
all_values[62]	3587	1			T59	5		T414	6		T509	20
all_values[63]	3736	1			T59	8		T414	1		T509	18