Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.aon_timer_aon_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	144203	1			T23	9		T24	92		T25	16
values[2]	10642	1			T25	1		T137	1		T451	2
values[3]	4214	1			T550	1		T554	7		T683	11
values[4]	2470	1			T550	1		T554	3		T683	7
values[5]	1722	1			T550	1		T554	3		T683	6
values[6]	1109	1			T550	1		T554	1		T683	4
values[7]	797	1			T550	1		T554	5		T683	11
values[8]	781	1			T550	1		T554	2		T683	4
values[9]	651	1			T550	1		T554	2		T683	3
values[10]	524	1			T550	1		T554	3		T683	4
values[11]	425	1			T550	1		T554	3		T683	5
values[12]	424	1			T550	1		T554	4		T683	20
values[13]	385	1			T550	1		T554	4		T683	8
values[14]	312	1			T550	1		T554	5		T683	4
values[15]	286	1			T550	1		T554	2		T683	5
values[16]	332	1			T550	1		T554	3		T683	16
values[17]	380	1			T550	1		T554	2		T683	4
values[18]	323	1			T550	1		T554	2		T683	20
values[19]	386	1			T550	1		T554	1		T683	10
values[20]	324	1			T550	1		T554	4		T683	8
values[21]	379	1			T550	1		T554	3		T683	5
values[22]	336	1			T550	1		T554	4		T683	8
values[23]	323	1			T550	1		T554	4		T683	12
values[24]	338	1			T550	1		T554	1		T683	6
values[25]	286	1			T550	1		T554	2		T683	4
values[26]	296	1			T550	2		T554	1		T683	7
values[27]	273	1			T550	1		T554	4		T683	6
values[28]	275	1			T550	1		T554	2		T683	12
values[29]	303	1			T550	1		T554	6		T683	16
values[30]	275	1			T550	1		T554	8		T683	12
values[31]	334	1			T550	1		T554	3		T683	3
values[32]	280	1			T550	1		T554	2		T683	4
values[33]	325	1			T550	1		T554	1		T683	7
values[34]	274	1			T550	1		T554	2		T683	3
values[35]	286	1			T550	1		T554	1		T683	6
values[36]	293	1			T550	1		T554	1		T683	5
values[37]	311	1			T550	1		T554	1		T683	14
values[38]	285	1			T550	1		T554	5		T683	6
values[39]	332	1			T550	1		T554	4		T683	12
values[40]	289	1			T550	1		T554	3		T683	6
values[41]	304	1			T550	1		T554	2		T683	5
values[42]	286	1			T550	1		T554	2		T683	5
values[43]	328	1			T550	1		T554	1		T683	6
values[44]	278	1			T550	1		T554	3		T683	4
values[45]	333	1			T550	1		T554	5		T683	16
values[46]	240	1			T550	1		T554	3		T683	6
values[47]	276	1			T550	1		T554	1		T683	5
values[48]	274	1			T550	1		T554	3		T683	4
values[49]	259	1			T550	1		T554	2		T683	5
values[50]	257	1			T550	1		T554	1		T683	4
values[51]	264	1			T550	1		T554	3		T683	3
values[52]	305	1			T550	1		T554	4		T683	8
values[53]	305	1			T550	1		T554	2		T683	9
values[54]	266	1			T550	1		T554	3		T683	16
values[55]	264	1			T550	1		T554	2		T683	4
values[56]	307	1			T550	1		T554	3		T683	28
values[57]	255	1			T550	1		T554	3		T683	13
values[58]	269	1			T550	1		T554	1		T683	4
values[59]	260	1			T550	1		T554	4		T683	3
values[60]	239	1			T550	1		T554	4		T683	6
values[61]	232	1			T550	1		T554	1		T683	12
values[62]	234	1			T550	1		T554	4		T683	9
values[63]	190	1			T550	1		T554	2		T683	6
values[64]	181	1			T550	1		T554	1		T683	7
values[65]	210	1			T550	1		T554	15		T683	9
values[66]	219	1			T550	1		T554	41		T683	3
values[67]	198	1			T550	1		T554	49		T683	6
values[68]	160	1			T550	1		T554	30		T683	6
values[69]	110	1			T550	1		T554	14		T683	4
values[70]	109	1			T550	1		T554	6		T846	7
values[71]	119	1			T550	1		T554	10		T846	7
values[72]	114	1			T550	1		T554	15		T846	3
values[73]	123	1			T550	1		T554	5		T846	6
values[74]	94	1			T550	1		T554	4		T846	3
values[75]	76	1			T550	1		T554	5		T846	5
values[76]	96	1			T550	1		T554	12		T846	3
values[77]	95	1			T550	1		T554	5		T846	10
values[78]	96	1			T550	1		T554	6		T846	6
values[79]	86	1			T550	1		T554	11		T846	6
values[80]	99	1			T550	1		T554	8		T846	4
values[81]	94	1			T550	1		T554	1		T846	6
values[82]	97	1			T550	1		T554	3		T846	3
values[83]	86	1			T550	1		T554	3		T846	3
values[84]	104	1			T550	1		T554	3		T846	8
values[85]	93	1			T550	1		T554	3		T846	13
values[86]	78	1			T550	1		T554	6		T846	5
values[87]	97	1			T550	2		T554	4		T846	4
values[88]	80	1			T550	1		T554	6		T846	3
values[89]	73	1			T550	1		T554	1		T846	3
values[90]	74	1			T550	2		T846	3		T847	1
values[91]	92	1			T550	1		T846	8		T847	1
values[92]	80	1			T550	2		T846	9		T847	1
values[93]	66	1			T550	1		T846	2		T847	1
values[94]	70	1			T550	1		T846	5		T847	1
values[95]	75	1			T550	6		T846	2		T847	1
values[96]	63	1			T550	4		T846	3		T847	1
values[97]	77	1			T550	4		T846	14		T847	1
values[98]	79	1			T550	1		T846	12		T847	1
values[99]	91	1			T550	5		T846	13		T847	1
values[100]	87	1			T550	1		T846	2		T847	1
values[101]	83	1			T550	3		T846	3		T847	1
values[102]	77	1			T550	1		T846	6		T847	2
values[103]	75	1			T550	2		T846	3		T847	1
values[104]	81	1			T550	4		T846	2		T847	1
values[105]	62	1			T550	1		T846	5		T847	1
values[106]	79	1			T550	1		T846	6		T847	1
values[107]	80	1			T550	2		T846	15		T847	1
values[108]	76	1			T550	1		T846	10		T847	1
values[109]	68	1			T550	1		T846	3		T847	1
values[110]	76	1			T550	2		T847	1		T836	1
values[111]	74	1			T550	3		T847	1		T836	1
values[112]	69	1			T550	3		T847	1		T836	1
values[113]	64	1			T550	2		T847	1		T836	1
values[114]	71	1			T550	1		T847	1		T836	1
values[115]	75	1			T550	1		T847	1		T836	1
values[116]	73	1			T550	1		T847	1		T836	1
values[117]	81	1			T550	1		T847	1		T836	1
values[118]	71	1			T550	2		T847	1		T836	1
values[119]	86	1			T550	1		T847	3		T836	1
values[120]	76	1			T550	3		T847	3		T836	2
values[121]	70	1			T550	3		T847	1		T836	2
values[122]	87	1			T550	1		T847	1		T836	4
values[123]	82	1			T550	2		T847	3		T836	2
values[124]	107	1			T550	1		T847	2		T836	1
values[125]	96	1			T550	2		T847	1		T836	1
values[126]	149	1			T550	3		T847	1		T836	1
values[127]	1113	1			T550	25		T847	36		T836	27
values[128]	10114	1			T550	287		T847	286		T836	262