Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.45	95.51	94.13	92.03		94.96	96.47	99.59

Total tests in report: 2816

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
39.69	39.69	44.93	44.93	43.12	43.12	32.19	32.19			58.04	58.04	59.44	59.44	0.39	0.39	/workspace/coverage/default/62.chip_sw_all_escalation_resets.4172002272
48.71	9.02	52.45	7.51	51.95	8.82	35.68	3.49			65.87	7.82	85.66	26.22	0.65	0.26	/workspace/coverage/default/2.chip_jtag_csr_rw.4229608512
55.92	7.21	60.87	8.42	52.74	0.79	38.26	2.58			65.96	0.09	85.66	0.00	32.02	31.37	/workspace/coverage/cover_reg_top/66.xbar_access_same_device_slow_rsp.2793434262
60.61	4.69	71.16	10.29	59.36	6.62	40.44	2.18			75.01	9.05	85.66	0.00	32.02	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_20.634297233
63.97	3.36	71.26	0.10	61.46	2.10	40.45	0.01			75.40	0.39	85.66	0.00	49.58	17.57	/workspace/coverage/cover_reg_top/73.xbar_access_same_device_slow_rsp.1878149466
67.26	3.29	77.23	5.97	65.75	4.29	44.40	3.95			77.45	2.05	89.16	3.50	49.58	0.00	/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.1372027963
70.10	2.83	77.23	0.00	65.75	0.00	61.36	16.95			77.45	0.00	89.16	0.00	49.63	0.05	/workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.2170845994
72.53	2.44	79.91	2.68	71.63	5.88	61.74	0.38			82.43	4.98	89.16	0.00	50.32	0.69	/workspace/coverage/cover_reg_top/9.chip_csr_rw.2588282525
74.75	2.22	80.02	0.11	72.90	1.27	62.22	0.48			82.54	0.11	89.16	0.00	61.68	11.36	/workspace/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.3209371382
76.78	2.03	82.09	2.07	75.42	2.51	67.85	5.63			84.33	1.80	89.34	0.17	61.68	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.3313421950
78.67	1.89	82.09	0.00	75.92	0.50	67.85	0.00			84.43	0.10	89.34	0.00	72.41	10.73	/workspace/coverage/cover_reg_top/81.xbar_stress_all.2568495265
80.27	1.59	83.75	1.65	76.20	0.28	71.03	3.18			84.51	0.08	89.34	0.00	76.77	4.36	/workspace/coverage/cover_reg_top/2.xbar_stress_all_with_rand_reset.1903443326
81.50	1.23	85.87	2.13	78.19	1.99	71.99	0.96			86.82	2.31	89.34	0.00	76.77	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_0.728537318
82.69	1.20	87.81	1.94	80.38	2.19	72.34	0.35			88.82	1.99	90.03	0.70	76.77	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.1048194308
83.62	0.93	87.85	0.04	80.88	0.50	73.04	0.70			88.86	0.04	90.03	0.00	81.06	4.29	/workspace/coverage/cover_reg_top/87.xbar_stress_all_with_reset_error.1073833249
84.41	0.79	88.48	0.63	81.16	0.27	75.91	2.88			89.09	0.24	90.21	0.17	81.61	0.55	/workspace/coverage/default/0.chip_jtag_csr_rw.4010497237
85.17	0.76	88.48	0.00	81.29	0.13	75.91	0.00			89.11	0.02	90.21	0.00	86.03	4.42	/workspace/coverage/cover_reg_top/89.xbar_access_same_device_slow_rsp.2313490035
85.90	0.73	88.76	0.28	81.40	0.11	75.93	0.01			89.22	0.11	94.06	3.85	86.03	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.2383411021
86.56	0.67	89.43	0.67	82.02	0.61	77.61	1.68			89.76	0.54	94.23	0.17	86.35	0.32	/workspace/coverage/default/1.chip_jtag_csr_rw.1274484743
87.14	0.58	90.48	1.05	82.96	0.94	78.29	0.69			90.48	0.72	94.23	0.00	86.41	0.06	/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.3427444110
87.72	0.58	90.51	0.03	82.96	0.00	81.54	3.25			90.48	0.00	94.41	0.17	86.41	0.00	/workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.1075775350
88.26	0.55	90.51	0.00	83.59	0.63	81.54	0.00			90.56	0.08	94.41	0.00	88.97	2.56	/workspace/coverage/cover_reg_top/54.xbar_stress_all_with_rand_reset.3061886594
88.70	0.44	90.52	0.01	85.77	2.18	81.56	0.02			90.56	0.00	94.41	0.00	89.38	0.41	/workspace/coverage/cover_reg_top/18.chip_tl_errors.1257139768
89.13	0.43	91.11	0.60	86.61	0.84	81.99	0.44			91.26	0.70	94.41	0.00	89.38	0.00	/workspace/coverage/default/1.chip_sw_gpio.1572847085
89.51	0.38	91.70	0.59	88.10	1.49	82.03	0.04			91.42	0.16	94.41	0.00	89.40	0.02	/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.2907222017
89.89	0.38	91.88	0.18	88.25	0.15	83.48	1.45			91.57	0.16	94.76	0.35	89.40	0.00	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.988339763
90.24	0.35	92.60	0.72	88.76	0.52	83.55	0.07			92.39	0.82	94.76	0.00	89.40	0.00	/workspace/coverage/default/10.chip_sw_uart_rand_baudrate.1946573616
90.58	0.33	93.05	0.44	89.15	0.39	83.73	0.18			92.85	0.46	95.28	0.52	89.40	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1598897588
90.89	0.31	93.06	0.01	89.15	0.00	84.74	1.01			92.85	0.00	95.28	0.00	90.24	0.83	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.2150599064
91.19	0.31	93.06	0.00	89.15	0.00	84.74	0.00			92.85	0.00	95.28	0.00	92.07	1.83	/workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.832649783
91.47	0.28	93.06	0.00	89.31	0.16	84.74	0.00			92.86	0.02	95.28	0.00	93.58	1.52	/workspace/coverage/cover_reg_top/76.xbar_stress_all_with_rand_reset.116251268
91.75	0.28	93.57	0.51	89.78	0.47	84.98	0.23			93.33	0.47	95.28	0.00	93.58	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_10.2229664605
92.01	0.26	93.57	0.00	89.98	0.20	84.98	0.00			93.33	0.00	95.28	0.00	94.91	1.33	/workspace/coverage/cover_reg_top/65.xbar_random_zero_delays.4251296424
92.25	0.24	93.58	0.01	89.98	0.01	86.41	1.44			93.33	0.00	95.28	0.00	94.91	0.00	/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.1846308214
92.48	0.23	93.58	0.00	89.99	0.01	87.75	1.34			93.33	0.00	95.28	0.00	94.95	0.04	/workspace/coverage/default/92.chip_sw_all_escalation_resets.1358075400
92.71	0.23	93.58	0.00	89.99	0.00	87.75	0.00			93.33	0.00	95.28	0.00	96.32	1.37	/workspace/coverage/cover_reg_top/81.xbar_access_same_device_slow_rsp.3420736840
92.89	0.18	93.79	0.20	90.19	0.20	88.13	0.37			93.61	0.29	95.28	0.00	96.32	0.00	/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.3671534798
93.04	0.15	93.83	0.04	90.59	0.40	88.15	0.03			94.06	0.44	95.28	0.00	96.32	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.2980956018
93.19	0.15	93.83	0.00	90.64	0.05	88.15	0.00			94.06	0.00	95.28	0.00	97.18	0.86	/workspace/coverage/cover_reg_top/13.xbar_random_large_delays.1667821646
93.34	0.15	94.09	0.26	90.93	0.29	88.47	0.32			94.06	0.00	95.28	0.00	97.18	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.214344125
93.48	0.14	94.09	0.00	90.93	0.00	89.34	0.87			94.06	0.00	95.28	0.00	97.18	0.00	/workspace/coverage/default/2.chip_sw_flash_init.18183692
93.58	0.10	94.14	0.05	91.04	0.11	89.47	0.13			94.16	0.11	95.28	0.00	97.39	0.21	/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.3226257391
93.68	0.10	94.14	0.00	91.04	0.00	90.07	0.60			94.16	0.00	95.28	0.00	97.39	0.00	/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.1711825
93.76	0.08	94.14	0.00	91.54	0.50	90.07	0.00			94.16	0.00	95.28	0.00	97.39	0.00	/workspace/coverage/cover_reg_top/21.chip_tl_errors.3717531726
93.84	0.08	94.19	0.05	91.68	0.14	90.27	0.21			94.24	0.07	95.28	0.00	97.39	0.00	/workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.1122643311
93.91	0.07	94.20	0.01	91.71	0.03	90.48	0.21			94.24	0.01	95.45	0.17	97.39	0.00	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.3865570973
93.97	0.06	94.20	0.00	91.82	0.11	90.48	0.00			94.24	0.00	95.45	0.00	97.65	0.26	/workspace/coverage/cover_reg_top/42.xbar_stress_all_with_error.1305508574
94.03	0.06	94.21	0.01	91.82	0.00	90.49	0.01			94.24	0.00	95.80	0.35	97.65	0.00	/workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.1824418012
94.09	0.06	94.28	0.07	91.99	0.17	90.49	0.00			94.36	0.11	95.80	0.00	97.65	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_retention.3764565395
94.15	0.06	94.29	0.01	92.12	0.13	90.56	0.08			94.41	0.05	95.80	0.00	97.72	0.07	/workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.2045932200
94.20	0.05	94.31	0.02	92.26	0.14	90.57	0.01			94.55	0.15	95.80	0.00	97.72	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.268077977
94.25	0.04	94.31	0.00	92.28	0.02	90.78	0.21			94.57	0.02	95.80	0.00	97.73	0.01	/workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.3497474356
94.29	0.04	94.38	0.08	92.37	0.09	90.80	0.02			94.64	0.07	95.80	0.00	97.73	0.00	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.3426446449
94.33	0.04	94.38	0.00	92.37	0.00	90.80	0.00			94.64	0.00	95.80	0.00	97.98	0.25	/workspace/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.2746178847
94.37	0.04	94.51	0.12	92.37	0.01	90.89	0.09			94.66	0.02	95.80	0.00	97.98	0.00	/workspace/coverage/default/3.chip_tap_straps_testunlock0.2251967065
94.41	0.04	94.52	0.01	92.39	0.01	90.89	0.00			94.69	0.02	95.98	0.17	97.99	0.01	/workspace/coverage/default/19.chip_sw_all_escalation_resets.1823161629
94.45	0.04	94.52	0.00	92.62	0.23	90.89	0.00			94.69	0.00	95.98	0.00	97.99	0.00	/workspace/coverage/cover_reg_top/7.chip_tl_errors.4078196103
94.48	0.04	94.52	0.01	92.63	0.01	90.90	0.01			94.69	0.01	96.15	0.17	98.00	0.01	/workspace/coverage/default/43.chip_sw_all_escalation_resets.360506965
94.52	0.04	94.53	0.01	92.64	0.01	90.90	0.00			94.70	0.01	96.33	0.17	98.01	0.01	/workspace/coverage/default/11.chip_sw_all_escalation_resets.1326878672
94.55	0.03	94.53	0.00	92.64	0.00	90.93	0.03			94.70	0.00	96.50	0.17	98.01	0.00	/workspace/coverage/default/0.chip_sw_data_integrity_escalation.3020308725
94.59	0.03	94.53	0.00	92.64	0.00	90.93	0.00			94.70	0.00	96.50	0.00	98.21	0.20	/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.4004298722
94.62	0.03	94.53	0.00	92.64	0.00	91.10	0.16			94.70	0.00	96.50	0.00	98.25	0.04	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.2975630175
94.65	0.03	94.53	0.00	92.64	0.00	91.27	0.17			94.70	0.00	96.50	0.00	98.25	0.00	/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.1402927266
94.68	0.03	94.53	0.00	92.66	0.02	91.28	0.02			94.70	0.00	96.50	0.00	98.38	0.13	/workspace/coverage/default/1.chip_sw_alert_test.570452306
94.70	0.03	94.60	0.07	92.69	0.03	91.29	0.01			94.75	0.05	96.50	0.00	98.38	0.00	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.3186462737
94.73	0.03	94.60	0.00	92.80	0.10	91.29	0.00			94.77	0.02	96.50	0.00	98.41	0.04	/workspace/coverage/cover_reg_top/49.xbar_stress_all_with_rand_reset.189189988
94.75	0.03	94.62	0.02	92.81	0.02	91.37	0.08			94.79	0.02	96.50	0.00	98.43	0.01	/workspace/coverage/default/46.chip_sw_all_escalation_resets.2440058883
94.78	0.03	94.69	0.07	92.87	0.05	91.37	0.00			94.82	0.03	96.50	0.00	98.43	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_wake.2059673355
94.80	0.02	94.75	0.07	92.91	0.05	91.37	0.00			94.84	0.02	96.50	0.00	98.43	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.3486603438
94.82	0.02	94.79	0.03	92.97	0.06	91.37	0.01			94.87	0.02	96.50	0.00	98.43	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.2003252716
94.84	0.02	94.79	0.00	93.07	0.10	91.37	0.00			94.87	0.00	96.50	0.00	98.44	0.01	/workspace/coverage/cover_reg_top/79.xbar_stress_all_with_rand_reset.736223322
94.86	0.02	94.79	0.00	93.07	0.00	91.48	0.10			94.87	0.00	96.50	0.00	98.44	0.00	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1308762353
94.87	0.02	94.79	0.00	93.17	0.10	91.48	0.00			94.87	0.00	96.50	0.00	98.44	0.00	/workspace/coverage/cover_reg_top/2.chip_tl_errors.2632602595
94.89	0.02	94.79	0.00	93.27	0.10	91.48	0.00			94.87	0.00	96.50	0.00	98.44	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_20.1394937546
94.91	0.02	94.79	0.00	93.36	0.10	91.48	0.00			94.87	0.00	96.50	0.00	98.44	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_0.3454561405
94.92	0.02	94.80	0.02	93.39	0.03	91.51	0.03			94.88	0.02	96.50	0.00	98.44	0.00	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.734762242
94.94	0.02	94.81	0.01	93.44	0.05	91.52	0.01			94.90	0.02	96.50	0.00	98.44	0.00	/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.2730726930
94.95	0.01	94.81	0.00	93.53	0.09	91.52	0.00			94.90	0.00	96.50	0.00	98.44	0.00	/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.3723353310
94.96	0.01	94.82	0.01	93.53	0.00	91.60	0.08			94.90	0.00	96.50	0.00	98.44	0.00	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.1756029151
94.98	0.01	94.82	0.00	93.54	0.01	91.60	0.00			94.90	0.00	96.50	0.00	98.50	0.06	/workspace/coverage/cover_reg_top/27.xbar_stress_all_with_rand_reset.3027798251
94.99	0.01	94.82	0.00	93.58	0.04	91.60	0.00			94.91	0.02	96.50	0.00	98.51	0.01	/workspace/coverage/cover_reg_top/16.xbar_access_same_device.1644738038
95.00	0.01	94.82	0.00	93.58	0.00	91.66	0.07			94.91	0.00	96.50	0.00	98.51	0.00	/workspace/coverage/default/0.chip_sw_flash_init.3305989533
95.01	0.01	94.82	0.00	93.65	0.06	91.66	0.00			94.91	0.00	96.50	0.00	98.51	0.00	/workspace/coverage/cover_reg_top/3.chip_tl_errors.4031474085
95.02	0.01	94.82	0.00	93.65	0.01	91.66	0.00			94.91	0.00	96.50	0.00	98.57	0.06	/workspace/coverage/cover_reg_top/56.xbar_stress_all_with_rand_reset.976726370
95.03	0.01	94.82	0.00	93.65	0.00	91.72	0.06			94.91	0.00	96.50	0.00	98.57	0.00	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.932886166
95.04	0.01	94.82	0.00	93.71	0.06	91.72	0.00			94.91	0.00	96.50	0.00	98.57	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_0.2333480735
95.05	0.01	94.84	0.02	93.71	0.01	91.73	0.01			94.93	0.02	96.50	0.00	98.57	0.00	/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.2820965569
95.05	0.01	94.84	0.00	93.72	0.01	91.77	0.04			94.93	0.00	96.50	0.00	98.57	0.00	/workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.2903685659
95.06	0.01	94.84	0.00	93.72	0.00	91.77	0.00			94.93	0.00	96.50	0.00	98.61	0.05	/workspace/coverage/cover_reg_top/88.xbar_stress_all_with_rand_reset.1071594398
95.07	0.01	94.86	0.02	93.72	0.01	91.77	0.01			94.94	0.01	96.50	0.00	98.63	0.01	/workspace/coverage/default/27.chip_sw_all_escalation_resets.4255388823
95.08	0.01	94.86	0.00	93.73	0.01	91.77	0.00			94.94	0.00	96.50	0.00	98.66	0.04	/workspace/coverage/cover_reg_top/58.xbar_stress_all_with_rand_reset.409550241
95.08	0.01	94.87	0.01	93.75	0.02	91.79	0.02			94.94	0.00	96.50	0.00	98.66	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.1055524246
95.09	0.01	94.87	0.00	93.79	0.04	91.79	0.00			94.94	0.00	96.50	0.00	98.66	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_10.1426372040
95.10	0.01	94.87	0.00	93.80	0.01	91.79	0.00			94.94	0.00	96.50	0.00	98.68	0.02	/workspace/coverage/cover_reg_top/19.xbar_stress_all_with_rand_reset.743320107
95.10	0.01	94.87	0.00	93.80	0.00	91.82	0.03			94.94	0.00	96.50	0.00	98.68	0.00	/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.3437293708
95.11	0.01	94.87	0.00	93.83	0.03	91.82	0.00			94.94	0.00	96.50	0.00	98.68	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_10.1063083852
95.11	0.01	94.87	0.01	93.84	0.01	91.83	0.01			94.95	0.01	96.50	0.00	98.68	0.00	/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.1373143628
95.12	0.01	94.87	0.00	93.85	0.01	91.83	0.00			94.95	0.00	96.50	0.00	98.71	0.02	/workspace/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.1931127404
95.12	0.01	94.87	0.00	93.85	0.01	91.83	0.00			94.95	0.00	96.50	0.00	98.73	0.02	/workspace/coverage/cover_reg_top/28.chip_tl_errors.3547611967
95.13	0.01	94.89	0.01	93.86	0.01	91.84	0.01			94.95	0.00	96.50	0.00	98.73	0.00	/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.1524590530
95.13	0.01	94.89	0.00	93.87	0.01	91.87	0.03			94.95	0.00	96.50	0.00	98.73	0.00	/workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.1104112997
95.14	0.01	94.89	0.00	93.87	0.00	91.88	0.02			94.95	0.00	96.50	0.00	98.74	0.01	/workspace/coverage/default/15.chip_sw_all_escalation_resets.1295992022
95.14	0.01	94.90	0.01	93.87	0.01	91.89	0.01			94.95	0.00	96.50	0.00	98.74	0.00	/workspace/coverage/default/0.chip_sw_power_sleep_load.1010467882
95.15	0.01	94.90	0.00	93.87	0.00	91.89	0.00			94.95	0.00	96.50	0.00	98.77	0.02	/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.1105814376
95.15	0.01	94.90	0.00	93.89	0.02	91.89	0.00			94.95	0.00	96.50	0.00	98.77	0.00	/workspace/coverage/cover_reg_top/31.xbar_stress_all.3220113261
95.15	0.01	94.90	0.00	93.91	0.02	91.89	0.00			94.95	0.00	96.50	0.00	98.77	0.00	/workspace/coverage/cover_reg_top/6.chip_tl_errors.3933540581
95.16	0.01	94.90	0.00	93.93	0.02	91.89	0.00			94.95	0.00	96.50	0.00	98.77	0.00	/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.2070128122
95.16	0.01	94.90	0.00	93.93	0.00	91.91	0.02			94.95	0.00	96.50	0.00	98.77	0.00	/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.3948779201
95.16	0.01	94.90	0.00	93.95	0.02	91.91	0.00			94.95	0.00	96.50	0.00	98.77	0.00	/workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.1957492646
95.17	0.01	94.90	0.00	93.97	0.02	91.91	0.00			94.95	0.00	96.50	0.00	98.77	0.00	/workspace/coverage/default/0.chip_sw_entropy_src_csrng.846606491
95.17	0.01	94.90	0.00	93.99	0.02	91.91	0.00			94.95	0.00	96.50	0.00	98.77	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_20.2026342008
95.17	0.01	94.90	0.00	93.99	0.01	91.91	0.01			94.95	0.00	96.50	0.00	98.78	0.01	/workspace/coverage/default/16.chip_sw_all_escalation_resets.4077558308
95.17	0.01	94.90	0.00	93.99	0.00	91.92	0.01			94.95	0.00	96.50	0.00	98.79	0.01	/workspace/coverage/cover_reg_top/20.xbar_random.4229069131
95.18	0.01	94.90	0.00	93.99	0.01	91.92	0.00			94.95	0.00	96.50	0.00	98.80	0.01	/workspace/coverage/cover_reg_top/38.xbar_stress_all_with_rand_reset.209430725
95.18	0.01	94.90	0.00	94.00	0.01	91.92	0.00			94.95	0.00	96.50	0.00	98.81	0.01	/workspace/coverage/cover_reg_top/72.xbar_access_same_device.817852174
95.18	0.01	94.90	0.00	94.00	0.01	91.92	0.00			94.95	0.00	96.50	0.00	98.83	0.01	/workspace/coverage/default/24.chip_sw_all_escalation_resets.4097320058
95.18	0.01	94.90	0.00	94.01	0.01	91.92	0.00			94.95	0.00	96.50	0.00	98.83	0.00	/workspace/coverage/cover_reg_top/80.xbar_stress_all_with_rand_reset.3206595061
95.19	0.01	94.90	0.00	94.03	0.01	91.92	0.00			94.95	0.00	96.50	0.00	98.83	0.00	/workspace/coverage/default/2.chip_sw_gpio.1920592031
95.19	0.01	94.90	0.00	94.03	0.00	91.93	0.01			94.95	0.00	96.50	0.00	98.83	0.00	/workspace/coverage/default/0.chip_sw_usbdev_config_host.3815215493
95.19	0.01	94.91	0.01	94.03	0.00	91.93	0.00			94.95	0.00	96.50	0.00	98.83	0.00	/workspace/coverage/default/2.chip_sw_pattgen_ios.3604494308
95.19	0.01	94.92	0.01	94.03	0.00	91.94	0.01			94.95	0.00	96.50	0.00	98.83	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.2843178672
95.20	0.01	94.92	0.00	94.03	0.00	91.94	0.00			94.95	0.00	96.50	0.00	98.84	0.01	/workspace/coverage/cover_reg_top/19.chip_tl_errors.2759980617
95.20	0.01	94.92	0.00	94.03	0.00	91.94	0.00			94.95	0.00	96.50	0.00	98.85	0.01	/workspace/coverage/cover_reg_top/29.xbar_stress_all_with_rand_reset.818685374
95.20	0.01	94.92	0.00	94.03	0.00	91.94	0.00			94.95	0.00	96.50	0.00	98.86	0.01	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.2813873906
95.20	0.01	94.92	0.00	94.03	0.00	91.94	0.00			94.95	0.00	96.50	0.00	98.87	0.01	/workspace/coverage/default/0.chip_sw_all_escalation_resets.414844506
95.20	0.01	94.92	0.00	94.03	0.00	91.94	0.00			94.95	0.00	96.50	0.00	98.88	0.01	/workspace/coverage/default/1.chip_sw_all_escalation_resets.1471902396
95.21	0.01	94.92	0.00	94.03	0.00	91.94	0.00			94.95	0.00	96.50	0.00	98.90	0.01	/workspace/coverage/default/10.chip_sw_all_escalation_resets.1405079745
95.21	0.01	94.92	0.00	94.03	0.00	91.94	0.00			94.95	0.00	96.50	0.00	98.91	0.01	/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.359578110
95.21	0.01	94.92	0.00	94.03	0.00	91.94	0.00			94.95	0.00	96.50	0.00	98.92	0.01	/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.1190342054
95.21	0.01	94.92	0.00	94.03	0.00	91.94	0.00			94.95	0.00	96.50	0.00	98.93	0.01	/workspace/coverage/default/12.chip_sw_all_escalation_resets.4127732292
95.21	0.01	94.92	0.00	94.03	0.00	91.94	0.00			94.95	0.00	96.50	0.00	98.94	0.01	/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.4142831578
95.22	0.01	94.92	0.00	94.03	0.00	91.94	0.00			94.95	0.00	96.50	0.00	98.95	0.01	/workspace/coverage/default/13.chip_sw_all_escalation_resets.2305368127
95.22	0.01	94.92	0.00	94.03	0.00	91.94	0.00			94.95	0.00	96.50	0.00	98.97	0.01	/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.2305866556
95.22	0.01	94.92	0.00	94.03	0.00	91.94	0.00			94.95	0.00	96.50	0.00	98.98	0.01	/workspace/coverage/default/14.chip_sw_all_escalation_resets.3445947804
95.22	0.01	94.92	0.00	94.03	0.00	91.94	0.00			94.95	0.00	96.50	0.00	98.99	0.01	/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.110911921
95.22	0.01	94.92	0.00	94.03	0.00	91.94	0.00			94.95	0.00	96.50	0.00	99.00	0.01	/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.3112812211
95.22	0.01	94.92	0.00	94.03	0.00	91.94	0.00			94.95	0.00	96.50	0.00	99.01	0.01	/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.2973823821
95.23	0.01	94.92	0.00	94.03	0.00	91.94	0.00			94.95	0.00	96.50	0.00	99.02	0.01	/workspace/coverage/default/17.chip_sw_all_escalation_resets.1962564550
95.23	0.01	94.92	0.00	94.03	0.00	91.94	0.00			94.95	0.00	96.50	0.00	99.04	0.01	/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.2678029335
95.23	0.01	94.92	0.00	94.03	0.00	91.94	0.00			94.95	0.00	96.50	0.00	99.05	0.01	/workspace/coverage/default/18.chip_sw_all_escalation_resets.1598694402
95.23	0.01	94.92	0.00	94.03	0.00	91.94	0.00			94.95	0.00	96.50	0.00	99.06	0.01	/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.2120422446
95.23	0.01	94.92	0.00	94.03	0.00	91.94	0.00			94.95	0.00	96.50	0.00	99.07	0.01	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.3193115489
95.24	0.01	94.92	0.00	94.03	0.00	91.94	0.00			94.95	0.00	96.50	0.00	99.08	0.01	/workspace/coverage/default/2.chip_sw_all_escalation_resets.87651367
95.24	0.01	94.92	0.00	94.03	0.00	91.94	0.00			94.95	0.00	96.50	0.00	99.10	0.01	/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.316350312
95.24	0.01	94.92	0.00	94.03	0.00	91.94	0.00			94.95	0.00	96.50	0.00	99.11	0.01	/workspace/coverage/default/20.chip_sw_all_escalation_resets.4040916230
95.24	0.01	94.92	0.00	94.03	0.00	91.94	0.00			94.95	0.00	96.50	0.00	99.12	0.01	/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.2950435971
95.24	0.01	94.92	0.00	94.03	0.00	91.94	0.00			94.95	0.00	96.50	0.00	99.13	0.01	/workspace/coverage/default/21.chip_sw_all_escalation_resets.3004076589
95.25	0.01	94.92	0.00	94.03	0.00	91.94	0.00			94.95	0.00	96.50	0.00	99.14	0.01	/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.845320497
95.25	0.01	94.92	0.00	94.03	0.00	91.94	0.00			94.95	0.00	96.50	0.00	99.15	0.01	/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.4196919362
95.25	0.01	94.92	0.00	94.03	0.00	91.94	0.00			94.95	0.00	96.50	0.00	99.17	0.01	/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.1235306281
95.25	0.01	94.92	0.00	94.03	0.00	91.94	0.00			94.95	0.00	96.50	0.00	99.18	0.01	/workspace/coverage/default/25.chip_sw_all_escalation_resets.3378711410
95.25	0.01	94.92	0.00	94.03	0.00	91.94	0.00			94.95	0.00	96.50	0.00	99.19	0.01	/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.2270404470
95.26	0.01	94.92	0.00	94.03	0.00	91.94	0.00			94.95	0.00	96.50	0.00	99.20	0.01	/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.3923753056
95.26	0.01	94.92	0.00	94.03	0.00	91.94	0.00			94.95	0.00	96.50	0.00	99.21	0.01	/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.1491802239
95.26	0.01	94.92	0.00	94.03	0.00	91.94	0.00			94.95	0.00	96.50	0.00	99.22	0.01	/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.891659371
95.26	0.01	94.92	0.00	94.03	0.00	91.94	0.00			94.95	0.00	96.50	0.00	99.24	0.01	/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.2165958287
95.26	0.01	94.92	0.00	94.03	0.00	91.94	0.00			94.95	0.00	96.50	0.00	99.25	0.01	/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.1599745999
95.27	0.01	94.92	0.00	94.03	0.00	91.94	0.00			94.95	0.00	96.50	0.00	99.26	0.01	/workspace/coverage/default/32.chip_sw_all_escalation_resets.560273246
95.27	0.01	94.92	0.00	94.03	0.00	91.94	0.00			94.95	0.00	96.50	0.00	99.27	0.01	/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.8882751
95.27	0.01	94.92	0.00	94.03	0.00	91.94	0.00			94.95	0.00	96.50	0.00	99.28	0.01	/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.3418224490
95.27	0.01	94.92	0.00	94.03	0.00	91.94	0.00			94.95	0.00	96.50	0.00	99.30	0.01	/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.4103892120
95.27	0.01	94.92	0.00	94.03	0.00	91.94	0.00			94.95	0.00	96.50	0.00	99.31	0.01	/workspace/coverage/default/36.chip_sw_all_escalation_resets.499586212
95.28	0.01	94.92	0.00	94.03	0.00	91.94	0.00			94.95	0.00	96.50	0.00	99.32	0.01	/workspace/coverage/default/38.chip_sw_all_escalation_resets.1618894835
95.28	0.01	94.92	0.00	94.03	0.00	91.94	0.00			94.95	0.00	96.50	0.00	99.33	0.01	/workspace/coverage/default/39.chip_sw_all_escalation_resets.2171026848
95.28	0.01	94.92	0.00	94.03	0.00	91.94	0.00			94.95	0.00	96.50	0.00	99.34	0.01	/workspace/coverage/default/4.chip_sw_all_escalation_resets.702682576
95.28	0.01	94.92	0.00	94.03	0.00	91.94	0.00			94.95	0.00	96.50	0.00	99.35	0.01	/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.77108476
95.28	0.01	94.92	0.00	94.03	0.00	91.94	0.00			94.95	0.00	96.50	0.00	99.37	0.01	/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.1405148915
95.29	0.01	94.92	0.00	94.03	0.00	91.94	0.00			94.95	0.00	96.50	0.00	99.38	0.01	/workspace/coverage/default/41.chip_sw_all_escalation_resets.3916040214
95.29	0.01	94.92	0.00	94.03	0.00	91.94	0.00			94.95	0.00	96.50	0.00	99.39	0.01	/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.3556300621
95.29	0.01	94.92	0.00	94.03	0.00	91.94	0.00			94.95	0.00	96.50	0.00	99.40	0.01	/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.16766708
95.29	0.01	94.92	0.00	94.03	0.00	91.94	0.00			94.95	0.00	96.50	0.00	99.41	0.01	/workspace/coverage/default/44.chip_sw_all_escalation_resets.4100949523
95.29	0.01	94.92	0.00	94.03	0.00	91.94	0.00			94.95	0.00	96.50	0.00	99.42	0.01	/workspace/coverage/default/45.chip_sw_all_escalation_resets.2818150933
95.30	0.01	94.92	0.00	94.03	0.00	91.94	0.00			94.95	0.00	96.50	0.00	99.44	0.01	/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.3776556925
95.30	0.01	94.92	0.00	94.03	0.00	91.94	0.00			94.95	0.00	96.50	0.00	99.45	0.01	/workspace/coverage/default/50.chip_sw_all_escalation_resets.1675898852
95.30	0.01	94.92	0.00	94.03	0.00	91.94	0.00			94.95	0.00	96.50	0.00	99.46	0.01	/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.2345824567
95.30	0.01	94.92	0.00	94.03	0.00	91.94	0.00			94.95	0.00	96.50	0.00	99.47	0.01	/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.3802686855
95.30	0.01	94.92	0.00	94.03	0.00	91.94	0.00			94.95	0.00	96.50	0.00	99.48	0.01	/workspace/coverage/default/53.chip_sw_all_escalation_resets.4070445288
95.31	0.01	94.92	0.00	94.03	0.00	91.94	0.00			94.95	0.00	96.50	0.00	99.49	0.01	/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.687296465
95.31	0.01	94.92	0.00	94.03	0.00	91.94	0.00			94.95	0.00	96.50	0.00	99.51	0.01	/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.2637493540
95.31	0.01	94.92	0.00	94.03	0.00	91.94	0.00			94.95	0.00	96.50	0.00	99.52	0.01	/workspace/coverage/default/68.chip_sw_all_escalation_resets.344946089
95.31	0.01	94.92	0.00	94.03	0.00	91.94	0.00			94.95	0.00	96.50	0.00	99.53	0.01	/workspace/coverage/default/7.chip_sw_all_escalation_resets.3869552812
95.31	0.01	94.92	0.00	94.03	0.00	91.94	0.00			94.95	0.00	96.50	0.00	99.54	0.01	/workspace/coverage/default/71.chip_sw_all_escalation_resets.3138573815
95.31	0.01	94.92	0.00	94.03	0.00	91.94	0.00			94.95	0.00	96.50	0.00	99.55	0.01	/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.1883224177
95.32	0.01	94.92	0.00	94.03	0.00	91.94	0.00			94.95	0.00	96.50	0.00	99.57	0.01	/workspace/coverage/default/76.chip_sw_all_escalation_resets.1390736600
95.32	0.01	94.92	0.00	94.03	0.00	91.94	0.00			94.95	0.00	96.50	0.00	99.58	0.01	/workspace/coverage/default/77.chip_sw_all_escalation_resets.649978649
95.32	0.01	94.92	0.00	94.03	0.00	91.94	0.00			94.95	0.00	96.50	0.00	99.59	0.01	/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.904949211
95.32	0.01	94.92	0.00	94.04	0.01	91.94	0.00			94.95	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/cover_reg_top/59.xbar_access_same_device.3367590566
95.32	0.01	94.92	0.00	94.05	0.01	91.94	0.00			94.95	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1120385500
95.33	0.01	94.92	0.01	94.05	0.00	91.95	0.01			94.95	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/default/58.chip_sw_all_escalation_resets.2030650741
95.33	0.01	94.92	0.00	94.05	0.00	91.96	0.01			94.95	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.1919287735
95.33	0.01	94.92	0.00	94.05	0.00	91.97	0.01			94.95	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.4235278264
95.33	0.01	94.92	0.01	94.05	0.00	91.97	0.01			94.95	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.3514980958
95.33	0.01	94.92	0.00	94.05	0.00	91.97	0.00			94.96	0.01	96.50	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.2008744761
95.33	0.01	94.92	0.00	94.05	0.00	91.97	0.00			94.96	0.01	96.50	0.00	99.59	0.00	/workspace/coverage/default/0.chip_tap_straps_dev.2264645747
95.33	0.01	94.92	0.00	94.06	0.01	91.97	0.00			94.96	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/cover_reg_top/11.chip_tl_errors.2198753985
95.34	0.01	94.92	0.00	94.06	0.01	91.97	0.00			94.96	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_gpio.658347372
95.34	0.01	94.92	0.00	94.07	0.01	91.97	0.00			94.96	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.1443732685
95.34	0.01	94.92	0.00	94.07	0.00	91.98	0.01			94.96	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.2964681366
95.34	0.01	94.92	0.00	94.07	0.00	91.99	0.01			94.96	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3849677483
95.34	0.01	94.93	0.01	94.08	0.01	91.99	0.00			94.96	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.4206654386
95.34	0.01	94.93	0.00	94.08	0.00	91.99	0.01			94.96	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.3354848284
95.34	0.01	94.93	0.00	94.08	0.00	92.00	0.01			94.96	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_aes_enc.3775875738
95.34	0.01	94.93	0.00	94.08	0.00	92.00	0.01			94.96	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.756309374
95.34	0.01	94.93	0.00	94.08	0.00	92.01	0.01			94.96	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_kmac_idle.1351734067
95.34	0.01	94.93	0.00	94.08	0.00	92.01	0.01			94.96	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.4106016343
95.35	0.01	94.93	0.00	94.08	0.00	92.01	0.01			94.96	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.1641891277
95.35	0.01	94.93	0.00	94.08	0.01	92.01	0.00			94.96	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/cover_reg_top/1.xbar_error_random.1951378131
95.35	0.01	94.93	0.00	94.08	0.01	92.01	0.00			94.96	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.661426663
95.35	0.01	94.93	0.00	94.09	0.01	92.01	0.00			94.96	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/cover_reg_top/10.chip_csr_rw.1248183247
95.35	0.01	94.93	0.00	94.09	0.01	92.01	0.00			94.96	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/cover_reg_top/16.xbar_stress_all_with_error.871281525
95.35	0.01	94.93	0.00	94.09	0.01	92.01	0.00			94.96	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/cover_reg_top/22.xbar_stress_all_with_error.3265413708
95.35	0.01	94.93	0.00	94.10	0.01	92.01	0.00			94.96	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/cover_reg_top/28.xbar_error_random.4162676105
95.35	0.01	94.93	0.00	94.10	0.01	92.01	0.00			94.96	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/cover_reg_top/36.xbar_stress_all_with_reset_error.1889748424
95.35	0.01	94.93	0.00	94.10	0.01	92.01	0.00			94.96	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/cover_reg_top/39.xbar_stress_all_with_reset_error.588307117
95.35	0.01	94.93	0.00	94.11	0.01	92.01	0.00			94.96	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/cover_reg_top/46.xbar_stress_all_with_error.480480036
95.35	0.01	94.93	0.00	94.11	0.01	92.01	0.00			94.96	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/cover_reg_top/48.xbar_stress_all.1524079029
95.35	0.01	94.93	0.00	94.11	0.01	92.01	0.00			94.96	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/cover_reg_top/56.xbar_stress_all_with_error.1456956291
95.35	0.01	94.93	0.00	94.12	0.01	92.01	0.00			94.96	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/cover_reg_top/71.xbar_stress_all_with_error.3387012139
95.35	0.01	94.93	0.00	94.12	0.01	92.01	0.00			94.96	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/cover_reg_top/76.xbar_stress_all_with_error.1741439072
95.35	0.01	94.93	0.00	94.12	0.01	92.01	0.00			94.96	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/cover_reg_top/83.xbar_stress_all_with_error.3247598284
95.35	0.01	94.93	0.00	94.13	0.01	92.01	0.00			94.96	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.3984438846
95.35	0.01	94.93	0.00	94.13	0.01	92.01	0.00			94.96	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.915589475
95.36	0.01	94.93	0.00	94.13	0.00	92.02	0.01			94.96	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/default/0.chip_tap_straps_rma.3040477823
95.36	0.01	94.93	0.01	94.13	0.00	92.02	0.00			94.96	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.1048994938
95.36	0.01	94.93	0.00	94.13	0.00	92.02	0.01			94.96	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.547524449
95.36	0.01	94.93	0.00	94.13	0.00	92.02	0.01			94.96	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_edn_boot_mode.2899474934
95.36	0.01	94.93	0.00	94.13	0.00	92.03	0.01			94.96	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.2968156903
95.36	0.01	94.93	0.00	94.13	0.00	92.03	0.01			94.96	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.399828503
95.36	0.01	94.93	0.00	94.13	0.00	92.03	0.01			94.96	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.1826010357

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.3482157236
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.2108664482
/workspace/coverage/cover_reg_top/0.chip_csr_rw.1143700563
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.4063664131
/workspace/coverage/cover_reg_top/0.chip_tl_errors.3385588505
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.1199465098
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.2689290548
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.16101190
/workspace/coverage/cover_reg_top/0.xbar_error_random.983062923
/workspace/coverage/cover_reg_top/0.xbar_random.1025500602
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.404883031
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.347308616
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.1549311086
/workspace/coverage/cover_reg_top/0.xbar_same_source.2055088868
/workspace/coverage/cover_reg_top/0.xbar_smoke.186418567
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.3489678517
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.3224930350
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.4214382282
/workspace/coverage/cover_reg_top/0.xbar_stress_all.1919457595
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.3992805310
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.2285403564
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.1867972028
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.411298671
/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.2626091974
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.2769844803
/workspace/coverage/cover_reg_top/1.chip_csr_rw.1596883102
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.392408644
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.1088004927
/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.2155692085
/workspace/coverage/cover_reg_top/1.chip_tl_errors.1519366710
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.1930605063
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.3244626435
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.2858760663
/workspace/coverage/cover_reg_top/1.xbar_random.3336021291
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.826441516
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.1183133420
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.1310605667
/workspace/coverage/cover_reg_top/1.xbar_same_source.227898837
/workspace/coverage/cover_reg_top/1.xbar_smoke.2306403252
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.3491521332
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.2608833500
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.4095947247
/workspace/coverage/cover_reg_top/1.xbar_stress_all.1417289590
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.3230215
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.978916240
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.1007025349
/workspace/coverage/cover_reg_top/10.chip_tl_errors.1315156972
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.3919479943
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.3338854624
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.2177625564
/workspace/coverage/cover_reg_top/10.xbar_error_random.1017133900
/workspace/coverage/cover_reg_top/10.xbar_random.64635242
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.2700295514
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.3096548248
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.4259376113
/workspace/coverage/cover_reg_top/10.xbar_same_source.334952510
/workspace/coverage/cover_reg_top/10.xbar_smoke.3830418444
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.1324816448
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.2943078626
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.2969563647
/workspace/coverage/cover_reg_top/10.xbar_stress_all.4216116243
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.2859548574
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.3791831538
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.428910988
/workspace/coverage/cover_reg_top/11.chip_csr_rw.1879487040
/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.2644669808
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.1851041661
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.2150603144
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.276678973
/workspace/coverage/cover_reg_top/11.xbar_error_random.1699879999
/workspace/coverage/cover_reg_top/11.xbar_random.2440703150
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.2042674787
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.46254009
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.2328786777
/workspace/coverage/cover_reg_top/11.xbar_same_source.3709916975
/workspace/coverage/cover_reg_top/11.xbar_smoke.705342594
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.2005697908
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.3394104537
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.3460008944
/workspace/coverage/cover_reg_top/11.xbar_stress_all.1624203362
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.2003609401
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.850327983
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.701838225
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.2989236327
/workspace/coverage/cover_reg_top/12.chip_csr_rw.938076058
/workspace/coverage/cover_reg_top/12.chip_tl_errors.767687867
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.1094897393
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.2761327003
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.1950886877
/workspace/coverage/cover_reg_top/12.xbar_error_random.2673438049
/workspace/coverage/cover_reg_top/12.xbar_random.2821885025
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.2687640797
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.3838902173
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.587508156
/workspace/coverage/cover_reg_top/12.xbar_same_source.64092422
/workspace/coverage/cover_reg_top/12.xbar_smoke.3457315696
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.4073497514
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.3555824516
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.1426612859
/workspace/coverage/cover_reg_top/12.xbar_stress_all.1152221952
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.2698815678
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.3070229352
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.2113743079
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.3084815174
/workspace/coverage/cover_reg_top/13.chip_csr_rw.3683269878
/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.2529726579
/workspace/coverage/cover_reg_top/13.chip_tl_errors.3359590095
/workspace/coverage/cover_reg_top/13.xbar_access_same_device.1446152500
/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.3314589357
/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.1110926446
/workspace/coverage/cover_reg_top/13.xbar_error_random.2568329750
/workspace/coverage/cover_reg_top/13.xbar_random.1771948374
/workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.2209262275
/workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.1451334086
/workspace/coverage/cover_reg_top/13.xbar_same_source.22807412
/workspace/coverage/cover_reg_top/13.xbar_smoke.4220781723
/workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.3198459201
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/workspace/coverage/default/4.chip_sw_uart_tx_rx.1744552169
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.4097349801
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.255833279
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.3816916239
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.2695482046
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.3774534951
/workspace/coverage/default/4.chip_tap_straps_dev.531714893
/workspace/coverage/default/4.chip_tap_straps_prod.3596075200
/workspace/coverage/default/4.chip_tap_straps_rma.369530680
/workspace/coverage/default/4.chip_tap_straps_testunlock0.1474238704
/workspace/coverage/default/40.chip_sw_all_escalation_resets.745514637
/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.2407520318
/workspace/coverage/default/42.chip_sw_all_escalation_resets.4185474576
/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.3102949983
/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.2179016055
/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.2860926167
/workspace/coverage/default/47.chip_sw_all_escalation_resets.2093740438
/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.2845790061
/workspace/coverage/default/48.chip_sw_all_escalation_resets.821463150
/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.3623690625
/workspace/coverage/default/49.chip_sw_all_escalation_resets.44719710
/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.4017484796
/workspace/coverage/default/5.chip_sw_all_escalation_resets.2941455936
/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.2406415042
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.2562182935
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.2829765224
/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.2575140370
/workspace/coverage/default/51.chip_sw_all_escalation_resets.536704563
/workspace/coverage/default/52.chip_sw_all_escalation_resets.1766510469
/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.867714653
/workspace/coverage/default/54.chip_sw_all_escalation_resets.3110832900
/workspace/coverage/default/55.chip_sw_all_escalation_resets.3623131581
/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.2943362598
/workspace/coverage/default/56.chip_sw_all_escalation_resets.3161163269
/workspace/coverage/default/57.chip_sw_all_escalation_resets.3046692654
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.439294264
/workspace/coverage/default/59.chip_sw_all_escalation_resets.1279558743
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.245835763
/workspace/coverage/default/6.chip_sw_all_escalation_resets.2598269693
/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.138979481
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.82534595
/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.2994116362
/workspace/coverage/default/60.chip_sw_all_escalation_resets.1182312696
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.4101834543
/workspace/coverage/default/61.chip_sw_all_escalation_resets.2327804979
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.679597700
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.4167531735
/workspace/coverage/default/63.chip_sw_all_escalation_resets.1133270567
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.1325394887
/workspace/coverage/default/64.chip_sw_all_escalation_resets.3045127151
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.3390805455
/workspace/coverage/default/65.chip_sw_all_escalation_resets.2053270333
/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.3112126956
/workspace/coverage/default/66.chip_sw_all_escalation_resets.2458479842
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.732496761
/workspace/coverage/default/67.chip_sw_all_escalation_resets.2584576192
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.2349758354
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.1241954065
/workspace/coverage/default/69.chip_sw_all_escalation_resets.1465540156
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.3561320877
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.2604992242
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.552210182
/workspace/coverage/default/70.chip_sw_all_escalation_resets.1701538481
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.2522151820
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.3138442485
/workspace/coverage/default/72.chip_sw_all_escalation_resets.3306563095
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.1156540669
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.1492855747
/workspace/coverage/default/74.chip_sw_all_escalation_resets.1107681805
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.454137795
/workspace/coverage/default/75.chip_sw_all_escalation_resets.1727227737
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.3351355758
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.2793736103
/workspace/coverage/default/78.chip_sw_all_escalation_resets.2566468908
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.1941885095
/workspace/coverage/default/79.chip_sw_all_escalation_resets.3184782322
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.2718600543
/workspace/coverage/default/8.chip_sw_all_escalation_resets.610144783
/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.608380489
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.3540425356
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.1128497299
/workspace/coverage/default/80.chip_sw_all_escalation_resets.2942050440
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.1672919651
/workspace/coverage/default/81.chip_sw_all_escalation_resets.2759775220
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.2825982822
/workspace/coverage/default/82.chip_sw_all_escalation_resets.2393057705
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.4031809555
/workspace/coverage/default/83.chip_sw_all_escalation_resets.1602945443
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.295450357
/workspace/coverage/default/84.chip_sw_all_escalation_resets.2756598986
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.187405929
/workspace/coverage/default/85.chip_sw_all_escalation_resets.1485997075
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.3510798497
/workspace/coverage/default/86.chip_sw_all_escalation_resets.3625961334
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.3206098094
/workspace/coverage/default/87.chip_sw_all_escalation_resets.3847674261
/workspace/coverage/default/88.chip_sw_all_escalation_resets.3575170720
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.604553456
/workspace/coverage/default/89.chip_sw_all_escalation_resets.1161958718
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.2214533234
/workspace/coverage/default/9.chip_sw_all_escalation_resets.406987498
/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.3583330910
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.1275169986
/workspace/coverage/default/90.chip_sw_all_escalation_resets.2764833436
/workspace/coverage/default/91.chip_sw_all_escalation_resets.1781816313
/workspace/coverage/default/93.chip_sw_all_escalation_resets.3202436044
/workspace/coverage/default/94.chip_sw_all_escalation_resets.603704137
/workspace/coverage/default/95.chip_sw_all_escalation_resets.2623661539
/workspace/coverage/default/96.chip_sw_all_escalation_resets.1996838614
/workspace/coverage/default/97.chip_sw_all_escalation_resets.3459195982
/workspace/coverage/default/98.chip_sw_all_escalation_resets.125469492
/workspace/coverage/default/99.chip_sw_all_escalation_resets.3116100163
/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.3260464896
/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.12884628
/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.570985916
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.3682532166
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.289928760
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.1471628819
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.22308284
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.3442259664

---

Total test records in report: 2816

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tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html | tests37.html | tests38.html | tests39.html | tests40.html | tests41.html | tests42.html | tests43.html | tests44.html | tests45.html | tests46.html | tests47.html | tests48.html | tests49.html | tests50.html | tests51.html | tests52.html | tests53.html | tests54.html | tests55.html | tests56.html | tests57.html | tests58.html | tests59.html

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T4	/workspace/coverage/default/0.chip_sw_aes_enc.3775875738			May 26 03:49:40 PM PDT 24	May 26 03:54:07 PM PDT 24	2560646520 ps
T5	/workspace/coverage/default/81.chip_sw_all_escalation_resets.2759775220			May 26 04:22:21 PM PDT 24	May 26 04:33:07 PM PDT 24	5690297694 ps
T6	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.988339763			May 26 03:58:08 PM PDT 24	May 26 04:26:47 PM PDT 24	24065294832 ps
T19	/workspace/coverage/default/0.chip_sw_rstmgr_sw_req.1845082531			May 26 03:48:04 PM PDT 24	May 26 03:54:29 PM PDT 24	3929836192 ps
T17	/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.3427444110			May 26 04:20:31 PM PDT 24	May 26 04:27:11 PM PDT 24	3878510920 ps
T18	/workspace/coverage/default/2.chip_sw_flash_crash_alert.737104901			May 26 04:11:21 PM PDT 24	May 26 04:23:32 PM PDT 24	5044906490 ps
T51	/workspace/coverage/default/62.chip_sw_all_escalation_resets.4172002272			May 26 04:20:27 PM PDT 24	May 26 04:32:05 PM PDT 24	5578920728 ps
T20	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.1756029151			May 26 03:56:22 PM PDT 24	May 26 04:49:01 PM PDT 24	12913445355 ps
T111	/workspace/coverage/default/2.chip_sw_kmac_idle.1738629204			May 26 04:09:45 PM PDT 24	May 26 04:14:52 PM PDT 24	2719849010 ps
T112	/workspace/coverage/default/1.chip_sw_clkmgr_jitter.856468445			May 26 04:01:44 PM PDT 24	May 26 04:05:32 PM PDT 24	2536473485 ps
T21	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.3313421950			May 26 03:55:09 PM PDT 24	May 26 04:53:33 PM PDT 24	14118661792 ps
T201	/workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.3497474356			May 26 03:49:46 PM PDT 24	May 26 03:58:45 PM PDT 24	4429655016 ps
T65	/workspace/coverage/default/46.chip_sw_all_escalation_resets.2440058883			May 26 04:18:47 PM PDT 24	May 26 04:29:25 PM PDT 24	4907204276 ps
T151	/workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.1826424306			May 26 03:53:07 PM PDT 24	May 26 03:57:18 PM PDT 24	2736658902 ps
T71	/workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.1122643311			May 26 03:52:48 PM PDT 24	May 26 03:59:48 PM PDT 24	4321688619 ps
T224	/workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.267934280			May 26 04:08:17 PM PDT 24	May 26 04:13:27 PM PDT 24	2645041056 ps
T202	/workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.2239561956			May 26 04:07:32 PM PDT 24	May 26 04:32:17 PM PDT 24	10310529365 ps
T22	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.3007631235			May 26 03:56:22 PM PDT 24	May 26 04:52:55 PM PDT 24	14422269884 ps
T238	/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.604553456			May 26 04:23:00 PM PDT 24	May 26 04:28:38 PM PDT 24	3897735000 ps
T36	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.3483338014			May 26 04:02:07 PM PDT 24	May 26 04:52:47 PM PDT 24	10026007378 ps
T166	/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.1846308214			May 26 04:15:38 PM PDT 24	May 26 05:18:04 PM PDT 24	18070528660 ps
T285	/workspace/coverage/default/23.chip_sw_all_escalation_resets.3669007004			May 26 04:18:43 PM PDT 24	May 26 04:28:54 PM PDT 24	4638075996 ps
T37	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.932886166			May 26 03:55:46 PM PDT 24	May 26 04:16:08 PM PDT 24	6653255944 ps
T179	/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.3671534798			May 26 04:14:22 PM PDT 24	May 26 04:21:36 PM PDT 24	3485779120 ps
T50	/workspace/coverage/default/16.chip_sw_all_escalation_resets.4077558308			May 26 04:18:07 PM PDT 24	May 26 04:29:08 PM PDT 24	5459517094 ps
T144	/workspace/coverage/default/33.chip_sw_all_escalation_resets.1391008873			May 26 04:17:13 PM PDT 24	May 26 04:28:00 PM PDT 24	5715258400 ps
T297	/workspace/coverage/default/15.chip_sw_all_escalation_resets.1295992022			May 26 04:16:58 PM PDT 24	May 26 04:27:06 PM PDT 24	4541123420 ps
T383	/workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.168957385			May 26 03:55:27 PM PDT 24	May 26 04:01:27 PM PDT 24	3468356004 ps
T147	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2410523614			May 26 03:57:24 PM PDT 24	May 26 04:05:54 PM PDT 24	6614642544 ps
T161	/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.505846273			May 26 03:59:16 PM PDT 24	May 26 04:05:41 PM PDT 24	3187782059 ps
T279	/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.2407520318			May 26 04:18:26 PM PDT 24	May 26 04:25:34 PM PDT 24	3874401460 ps
T235	/workspace/coverage/default/30.chip_sw_all_escalation_resets.2252528646			May 26 04:21:33 PM PDT 24	May 26 04:31:41 PM PDT 24	4547816564 ps
T384	/workspace/coverage/default/1.rom_e2e_asm_init_rma.37019452			May 26 04:07:31 PM PDT 24	May 26 05:02:10 PM PDT 24	14258679406 ps
T191	/workspace/coverage/default/10.chip_sw_uart_rand_baudrate.1946573616			May 26 04:16:12 PM PDT 24	May 26 04:25:30 PM PDT 24	4133529752 ps
T314	/workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.3383810386			May 26 04:10:59 PM PDT 24	May 26 04:19:00 PM PDT 24	3964822034 ps
T148	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3849677483			May 26 03:49:50 PM PDT 24	May 26 04:01:45 PM PDT 24	18386727850 ps
T387	/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.4031809555			May 26 04:23:10 PM PDT 24	May 26 04:30:22 PM PDT 24	3639723210 ps
T397	/workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.121912358			May 26 03:58:35 PM PDT 24	May 26 04:07:56 PM PDT 24	5540844168 ps
T721	/workspace/coverage/default/1.chip_sw_aes_entropy.892363601			May 26 03:59:02 PM PDT 24	May 26 04:02:42 PM PDT 24	2738314860 ps
T472	/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.3112126956			May 26 04:20:45 PM PDT 24	May 26 04:29:24 PM PDT 24	4169941160 ps
T167	/workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.546109320			May 26 03:52:03 PM PDT 24	May 26 04:08:20 PM PDT 24	5533979952 ps
T163	/workspace/coverage/default/1.chip_sw_entropy_src_csrng.2117543861			May 26 03:59:08 PM PDT 24	May 26 04:19:58 PM PDT 24	6030360200 ps
T713	/workspace/coverage/default/0.chip_sw_all_escalation_resets.414844506			May 26 03:46:28 PM PDT 24	May 26 04:00:42 PM PDT 24	4949261770 ps
T232	/workspace/coverage/default/4.chip_sw_uart_tx_rx.1744552169			May 26 04:14:12 PM PDT 24	May 26 04:25:35 PM PDT 24	4376274760 ps
T194	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.2290276279			May 26 03:48:33 PM PDT 24	May 26 03:54:18 PM PDT 24	3129995913 ps
T236	/workspace/coverage/default/95.chip_sw_all_escalation_resets.2623661539			May 26 04:22:50 PM PDT 24	May 26 04:30:52 PM PDT 24	5397684610 ps
T42	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3362028775			May 26 04:09:51 PM PDT 24	May 26 04:21:24 PM PDT 24	4561587128 ps
T62	/workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.2170845994			May 26 04:09:34 PM PDT 24	May 26 05:04:09 PM PDT 24	17078143080 ps
T64	/workspace/coverage/default/0.chip_tap_straps_prod.3952928984			May 26 03:50:15 PM PDT 24	May 26 04:02:42 PM PDT 24	7113787901 ps
T108	/workspace/coverage/default/3.chip_tap_straps_dev.125384179			May 26 04:13:23 PM PDT 24	May 26 04:35:07 PM PDT 24	10521081862 ps
T465	/workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.1735664791			May 26 03:53:35 PM PDT 24	May 26 03:56:44 PM PDT 24	2868592988 ps
T164	/workspace/coverage/default/2.chip_sw_edn_auto_mode.2400102008			May 26 04:08:47 PM PDT 24	May 26 04:28:13 PM PDT 24	5147024296 ps
T138	/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.150645572			May 26 04:18:00 PM PDT 24	May 26 05:14:20 PM PDT 24	15923299270 ps
T43	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2334606224			May 26 03:51:52 PM PDT 24	May 26 04:02:09 PM PDT 24	3699529768 ps
T142	/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.3226257391			May 26 03:58:30 PM PDT 24	May 26 04:23:46 PM PDT 24	13485998400 ps
T74	/workspace/coverage/default/18.chip_sw_uart_rand_baudrate.2953734053			May 26 04:16:34 PM PDT 24	May 26 04:24:13 PM PDT 24	3611133216 ps
T63	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1528852530			May 26 04:02:58 PM PDT 24	May 26 04:39:31 PM PDT 24	12430824139 ps
T59	/workspace/coverage/default/2.chip_sw_flash_init.18183692			May 26 04:04:04 PM PDT 24	May 26 04:38:07 PM PDT 24	19891341518 ps
T168	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.1919287735			May 26 03:51:39 PM PDT 24	May 26 04:00:07 PM PDT 24	7520266920 ps
T324	/workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.3514980958			May 26 04:03:57 PM PDT 24	May 26 04:06:24 PM PDT 24	2045289664 ps
T134	/workspace/coverage/default/0.chip_sw_otbn_smoketest.639064414			May 26 03:53:32 PM PDT 24	May 26 04:36:17 PM PDT 24	10454423682 ps
T227	/workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.987869963			May 26 04:06:16 PM PDT 24	May 26 04:30:02 PM PDT 24	8013404790 ps
T60	/workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.1641891277			May 26 04:01:44 PM PDT 24	May 26 04:33:30 PM PDT 24	20420124305 ps
T47	/workspace/coverage/default/92.chip_sw_all_escalation_resets.1358075400			May 26 04:24:59 PM PDT 24	May 26 04:35:17 PM PDT 24	6182859108 ps
T405	/workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.2434896148			May 26 04:02:33 PM PDT 24	May 26 04:21:51 PM PDT 24	4801358760 ps
T896	/workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.2015370423			May 26 04:14:12 PM PDT 24	May 26 04:29:58 PM PDT 24	5648582660 ps
T388	/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.359578110			May 26 04:16:35 PM PDT 24	May 26 04:23:15 PM PDT 24	3890071076 ps
T72	/workspace/coverage/default/1.chip_sw_spi_device_pass_through.4075289703			May 26 03:54:32 PM PDT 24	May 26 04:05:21 PM PDT 24	5852105274 ps
T135	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.2957055808			May 26 03:50:42 PM PDT 24	May 26 04:50:22 PM PDT 24	17455447038 ps
T38	/workspace/coverage/default/0.chip_sw_alert_handler_escalation.2187280245			May 26 03:50:09 PM PDT 24	May 26 03:59:12 PM PDT 24	5066122600 ps
T275	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2628007504			May 26 03:54:58 PM PDT 24	May 26 04:41:16 PM PDT 24	27290715427 ps
T52	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.1412435501			May 26 03:58:19 PM PDT 24	May 26 04:19:56 PM PDT 24	6558886480 ps
T298	/workspace/coverage/default/41.chip_sw_all_escalation_resets.3916040214			May 26 04:27:52 PM PDT 24	May 26 04:36:41 PM PDT 24	4690362890 ps
T897	/workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.2352768804			May 26 03:56:21 PM PDT 24	May 26 04:17:12 PM PDT 24	5883125423 ps
T53	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.1878085286			May 26 03:58:46 PM PDT 24	May 26 04:26:01 PM PDT 24	7443135408 ps
T740	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2703527604			May 26 03:47:52 PM PDT 24	May 26 04:30:35 PM PDT 24	20749512603 ps
T395	/workspace/coverage/default/2.chip_sw_ast_clk_outputs.3599929402			May 26 04:09:39 PM PDT 24	May 26 04:26:38 PM PDT 24	7503656600 ps
T898	/workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.2554729189			May 26 04:07:40 PM PDT 24	May 26 04:13:44 PM PDT 24	2391529970 ps
T372	/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.2179016055			May 26 04:19:09 PM PDT 24	May 26 04:27:47 PM PDT 24	3493102004 ps
T165	/workspace/coverage/default/1.chip_sw_edn_auto_mode.4183937401			May 26 03:59:30 PM PDT 24	May 26 04:24:49 PM PDT 24	6954343800 ps
T375	/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.2211377296			May 26 04:10:05 PM PDT 24	May 26 05:07:27 PM PDT 24	14301185230 ps
T376	/workspace/coverage/default/2.chip_sw_csrng_smoketest.1096248441			May 26 04:12:18 PM PDT 24	May 26 04:16:59 PM PDT 24	2887655320 ps
T55	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.4196262666			May 26 03:58:53 PM PDT 24	May 26 04:55:24 PM PDT 24	10399089720 ps
T226	/workspace/coverage/default/2.chip_sw_uart_rand_baudrate.2255145483			May 26 04:05:22 PM PDT 24	May 26 04:16:44 PM PDT 24	4563317026 ps
T192	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.626568271			May 26 03:55:33 PM PDT 24	May 26 04:06:17 PM PDT 24	4340072952 ps
T377	/workspace/coverage/default/1.chip_sw_uart_smoketest.4149481928			May 26 04:03:46 PM PDT 24	May 26 04:07:47 PM PDT 24	2483176580 ps
T26	/workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1686198989			May 26 04:01:57 PM PDT 24	May 26 04:12:14 PM PDT 24	4116356268 ps
T378	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.3529780073			May 26 03:59:38 PM PDT 24	May 26 05:04:11 PM PDT 24	13703202624 ps
T899	/workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.3827694122			May 26 03:53:50 PM PDT 24	May 26 03:57:29 PM PDT 24	2696020044 ps
T715	/workspace/coverage/default/99.chip_sw_all_escalation_resets.3116100163			May 26 04:25:35 PM PDT 24	May 26 04:38:33 PM PDT 24	4941355700 ps
T159	/workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.4063176199			May 26 04:12:00 PM PDT 24	May 26 04:26:00 PM PDT 24	6489971557 ps
T193	/workspace/coverage/default/19.chip_sw_uart_rand_baudrate.2257293931			May 26 04:17:16 PM PDT 24	May 26 04:26:33 PM PDT 24	3633148486 ps
T219	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.1050379278			May 26 03:51:55 PM PDT 24	May 26 03:57:13 PM PDT 24	2994730455 ps
T900	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.2843178672			May 26 03:48:53 PM PDT 24	May 26 04:02:46 PM PDT 24	7552846040 ps
T719	/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.2718600543			May 26 04:18:04 PM PDT 24	May 26 04:26:14 PM PDT 24	3845696508 ps
T99	/workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.3891775122			May 26 04:04:14 PM PDT 24	May 26 04:14:17 PM PDT 24	6193294618 ps
T398	/workspace/coverage/default/1.chip_sw_all_escalation_resets.1471902396			May 26 03:52:46 PM PDT 24	May 26 04:03:44 PM PDT 24	5787605970 ps
T288	/workspace/coverage/default/94.chip_sw_all_escalation_resets.603704137			May 26 04:22:34 PM PDT 24	May 26 04:29:53 PM PDT 24	4943366840 ps
T258	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.3984438846			May 26 03:48:24 PM PDT 24	May 26 03:59:56 PM PDT 24	4077976599 ps
T281	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.3267306660			May 26 04:05:38 PM PDT 24	May 26 04:18:20 PM PDT 24	4005984492 ps
T75	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.1748829371			May 26 03:48:55 PM PDT 24	May 26 04:00:22 PM PDT 24	4535975288 ps
T98	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.847267392			May 26 03:55:44 PM PDT 24	May 26 04:58:14 PM PDT 24	13424555211 ps
T214	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.2686623984			May 26 04:06:57 PM PDT 24	May 26 04:14:02 PM PDT 24	3044303369 ps
T39	/workspace/coverage/default/1.chip_sw_alert_handler_escalation.1672093506			May 26 03:57:47 PM PDT 24	May 26 04:04:08 PM PDT 24	4650526120 ps
T259	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.3426446449			May 26 03:52:50 PM PDT 24	May 26 04:02:02 PM PDT 24	4266947436 ps
T386	/workspace/coverage/default/22.chip_sw_all_escalation_resets.765175939			May 26 04:16:33 PM PDT 24	May 26 04:24:54 PM PDT 24	4311382582 ps
T215	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.2673108995			May 26 04:00:40 PM PDT 24	May 26 04:11:34 PM PDT 24	4556098597 ps
T221	/workspace/coverage/default/1.rom_keymgr_functest.2869653538			May 26 04:07:41 PM PDT 24	May 26 04:17:39 PM PDT 24	5783632836 ps
T720	/workspace/coverage/default/44.chip_sw_all_escalation_resets.4100949523			May 26 04:28:41 PM PDT 24	May 26 04:39:46 PM PDT 24	5963655164 ps
T66	/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.3948779201			May 26 03:49:02 PM PDT 24	May 26 04:09:04 PM PDT 24	9840218380 ps
T143	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.1443732685			May 26 03:47:51 PM PDT 24	May 26 04:15:38 PM PDT 24	12687362130 ps
T154	/workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2105105821			May 26 03:57:34 PM PDT 24	May 26 04:07:08 PM PDT 24	18167543928 ps
T413	/workspace/coverage/default/1.chip_sw_kmac_app_rom.1720001763			May 26 03:59:47 PM PDT 24	May 26 04:03:21 PM PDT 24	2926173340 ps
T136	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.2975630175			May 26 03:49:50 PM PDT 24	May 26 04:09:42 PM PDT 24	6634554680 ps
T92	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3033786975			May 26 03:55:48 PM PDT 24	May 26 04:05:29 PM PDT 24	5486721576 ps
T233	/workspace/coverage/default/14.chip_sw_uart_rand_baudrate.104099985			May 26 04:18:40 PM PDT 24	May 26 05:05:46 PM PDT 24	12502011864 ps
T145	/workspace/coverage/default/37.chip_sw_all_escalation_resets.526408583			May 26 04:18:16 PM PDT 24	May 26 04:29:26 PM PDT 24	5823202308 ps
T712	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.297895940			May 26 03:56:42 PM PDT 24	May 26 04:50:25 PM PDT 24	13916956220 ps
T901	/workspace/coverage/default/2.chip_sw_example_flash.3529963992			May 26 04:03:24 PM PDT 24	May 26 04:06:54 PM PDT 24	2119899376 ps
T299	/workspace/coverage/default/63.chip_sw_all_escalation_resets.1133270567			May 26 04:22:07 PM PDT 24	May 26 04:30:31 PM PDT 24	5895095790 ps
T225	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.4206654386			May 26 03:47:24 PM PDT 24	May 26 04:00:18 PM PDT 24	5034512068 ps
T253	/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.1241954065			May 26 04:23:12 PM PDT 24	May 26 04:28:43 PM PDT 24	3629910900 ps
T902	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.1201812199			May 26 03:50:13 PM PDT 24	May 26 03:57:33 PM PDT 24	6290566244 ps
T56	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.3806169808			May 26 03:56:42 PM PDT 24	May 26 04:51:32 PM PDT 24	10497124373 ps
T903	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac.1703078107			May 26 04:09:14 PM PDT 24	May 26 04:14:02 PM PDT 24	3233189080 ps
T155	/workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1332202075			May 26 04:07:48 PM PDT 24	May 26 04:15:46 PM PDT 24	18194722200 ps
T162	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2856487221			May 26 03:47:45 PM PDT 24	May 26 04:09:00 PM PDT 24	9083416179 ps
T1	/workspace/coverage/default/1.chip_sw_sleep_pin_retention.2398293334			May 26 03:54:43 PM PDT 24	May 26 04:00:30 PM PDT 24	3899773000 ps
T44	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.2150599064			May 26 03:58:43 PM PDT 24	May 26 04:25:54 PM PDT 24	10574918408 ps
T126	/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3305268267			May 26 03:52:09 PM PDT 24	May 26 04:13:11 PM PDT 24	7431441551 ps
T127	/workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.376034532			May 26 04:02:48 PM PDT 24	May 26 04:09:47 PM PDT 24	9128516444 ps
T128	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.1055524246			May 26 03:50:17 PM PDT 24	May 26 04:01:34 PM PDT 24	3745966400 ps
T129	/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.892169854			May 26 04:14:38 PM PDT 24	May 26 04:53:10 PM PDT 24	13498600248 ps
T130	/workspace/coverage/default/0.chip_sw_csrng_smoketest.3414025910			May 26 03:52:54 PM PDT 24	May 26 03:56:42 PM PDT 24	3082251464 ps
T131	/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.2575140370			May 26 04:21:18 PM PDT 24	May 26 04:28:34 PM PDT 24	4270314040 ps
T132	/workspace/coverage/default/24.chip_sw_all_escalation_resets.4097320058			May 26 04:17:03 PM PDT 24	May 26 04:27:16 PM PDT 24	5450178098 ps
T133	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.3193115489			May 26 04:07:49 PM PDT 24	May 26 04:16:37 PM PDT 24	4309748478 ps
T229	/workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.2084104648			May 26 04:05:21 PM PDT 24	May 26 04:16:40 PM PDT 24	4606741752 ps
T256	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.2754993662			May 26 04:12:56 PM PDT 24	May 26 04:21:54 PM PDT 24	3435013702 ps
T282	/workspace/coverage/default/3.chip_sw_uart_rand_baudrate.1113334781			May 26 04:13:14 PM PDT 24	May 26 04:35:03 PM PDT 24	8232261960 ps
T40	/workspace/coverage/default/2.chip_tap_straps_dev.317619210			May 26 04:09:19 PM PDT 24	May 26 04:11:22 PM PDT 24	2268332040 ps
T904	/workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.4217524796			May 26 04:11:53 PM PDT 24	May 26 04:16:36 PM PDT 24	2569859358 ps
T801	/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.2973823821			May 26 04:17:30 PM PDT 24	May 26 04:23:40 PM PDT 24	3953169580 ps
T828	/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.8882751			May 26 04:17:29 PM PDT 24	May 26 04:23:47 PM PDT 24	3188921172 ps
T753	/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.915803425			May 26 04:17:54 PM PDT 24	May 26 04:24:36 PM PDT 24	3045244900 ps
T261	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.3924705840			May 26 03:51:36 PM PDT 24	May 26 04:03:22 PM PDT 24	3892215452 ps
T905	/workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.3740749025			May 26 03:57:45 PM PDT 24	May 26 04:14:11 PM PDT 24	6645995002 ps
T276	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.2772542647			May 26 04:07:34 PM PDT 24	May 26 05:03:27 PM PDT 24	17017371128 ps
T906	/workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.1073470209			May 26 04:11:30 PM PDT 24	May 26 04:16:42 PM PDT 24	2867222820 ps
T169	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.2948285017			May 26 04:12:22 PM PDT 24	May 26 04:21:29 PM PDT 24	5707324872 ps
T31	/workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.1075775350			May 26 03:50:57 PM PDT 24	May 26 04:03:00 PM PDT 24	6578708144 ps
T321	/workspace/coverage/default/1.chip_sw_rv_timer_smoketest.1831876333			May 26 04:04:53 PM PDT 24	May 26 04:08:37 PM PDT 24	2883275840 ps
T242	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.3994919739			May 26 03:47:17 PM PDT 24	May 26 04:09:48 PM PDT 24	7146342616 ps
T907	/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.1221034990			May 26 03:47:42 PM PDT 24	May 26 04:04:32 PM PDT 24	5991912232 ps
T908	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.4193731093			May 26 04:01:03 PM PDT 24	May 26 05:31:46 PM PDT 24	17238361132 ps
T27	/workspace/coverage/default/0.chip_jtag_csr_rw.4010497237			May 26 03:41:45 PM PDT 24	May 26 04:25:50 PM PDT 24	18006125320 ps
T170	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.2240272074			May 26 04:01:16 PM PDT 24	May 26 04:08:59 PM PDT 24	5110900248 ps
T41	/workspace/coverage/default/3.chip_tap_straps_testunlock0.2251967065			May 26 04:12:53 PM PDT 24	May 26 04:15:27 PM PDT 24	3194054913 ps
T237	/workspace/coverage/default/2.chip_plic_all_irqs_20.634297233			May 26 04:09:47 PM PDT 24	May 26 04:21:50 PM PDT 24	5111003748 ps
T812	/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.3138442485			May 26 04:22:18 PM PDT 24	May 26 04:28:12 PM PDT 24	3905667100 ps
T467	/workspace/coverage/default/2.chip_sw_otbn_randomness.2434482641			May 26 04:08:48 PM PDT 24	May 26 04:24:42 PM PDT 24	5962024752 ps
T756	/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.2793736103			May 26 04:25:01 PM PDT 24	May 26 04:31:54 PM PDT 24	3776352200 ps
T300	/workspace/coverage/default/84.chip_sw_all_escalation_resets.2756598986			May 26 04:22:39 PM PDT 24	May 26 04:32:56 PM PDT 24	5482580866 ps
T909	/workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.2899949580			May 26 04:15:24 PM PDT 24	May 26 05:16:22 PM PDT 24	16130621784 ps
T160	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2143963850			May 26 04:13:14 PM PDT 24	May 26 04:32:58 PM PDT 24	6383350808 ps
T335	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.2966387121			May 26 03:59:14 PM PDT 24	May 26 05:28:59 PM PDT 24	21548032033 ps
T910	/workspace/coverage/default/2.rom_e2e_asm_init_dev.3988375520			May 26 04:18:07 PM PDT 24	May 26 05:11:47 PM PDT 24	14005507172 ps
T765	/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.4142831578			May 26 04:17:12 PM PDT 24	May 26 04:22:36 PM PDT 24	3312960296 ps
T414	/workspace/coverage/default/2.chip_sw_kmac_app_rom.2125742763			May 26 04:12:28 PM PDT 24	May 26 04:16:34 PM PDT 24	2619091112 ps
T471	/workspace/coverage/default/0.chip_sw_aes_masking_off.3366797799			May 26 03:49:28 PM PDT 24	May 26 03:54:34 PM PDT 24	3171965968 ps
T911	/workspace/coverage/default/0.chip_sw_rstmgr_smoketest.3326276653			May 26 03:57:57 PM PDT 24	May 26 04:01:00 PM PDT 24	2509437512 ps
T89	/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.1524590530			May 26 03:47:43 PM PDT 24	May 26 03:51:22 PM PDT 24	2967767870 ps
T110	/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.3802686855			May 26 04:20:30 PM PDT 24	May 26 04:25:56 PM PDT 24	3701975894 ps
T115	/workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.2158821572			May 26 04:11:11 PM PDT 24	May 26 04:17:46 PM PDT 24	3244329910 ps
T116	/workspace/coverage/default/1.rom_e2e_asm_init_dev.1169700417			May 26 04:08:33 PM PDT 24	May 26 05:01:36 PM PDT 24	14760766685 ps
T117	/workspace/coverage/default/0.chip_sw_aon_timer_irq.1046294767			May 26 03:53:14 PM PDT 24	May 26 04:00:52 PM PDT 24	3886429186 ps
T118	/workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.2272013701			May 26 04:11:40 PM PDT 24	May 26 04:22:56 PM PDT 24	4357538002 ps
T119	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.3865570973			May 26 03:50:56 PM PDT 24	May 26 04:01:44 PM PDT 24	5666273713 ps
T120	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.404440114			May 26 04:01:30 PM PDT 24	May 26 04:12:41 PM PDT 24	4676887516 ps
T76	/workspace/coverage/default/0.chip_sw_usbdev_pullup.655639486			May 26 03:48:02 PM PDT 24	May 26 03:52:13 PM PDT 24	3093508860 ps
T121	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.1970094525			May 26 04:00:21 PM PDT 24	May 26 05:01:21 PM PDT 24	13960048706 ps
T122	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.597060673			May 26 03:48:49 PM PDT 24	May 26 04:54:55 PM PDT 24	16838972622 ps
T82	/workspace/coverage/default/1.chip_sw_gpio_smoketest.3773596607			May 26 04:03:47 PM PDT 24	May 26 04:08:48 PM PDT 24	2874041284 ps
T352	/workspace/coverage/default/90.chip_sw_all_escalation_resets.2764833436			May 26 04:22:54 PM PDT 24	May 26 04:32:09 PM PDT 24	4701351936 ps
T353	/workspace/coverage/default/18.chip_sw_all_escalation_resets.1598694402			May 26 04:16:06 PM PDT 24	May 26 04:29:12 PM PDT 24	4782597568 ps
T354	/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.2120422446			May 26 04:16:53 PM PDT 24	May 26 04:22:49 PM PDT 24	3781226492 ps
T355	/workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.1912249357			May 26 03:49:43 PM PDT 24	May 26 03:56:52 PM PDT 24	3935308760 ps
T78	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.2572783072			May 26 04:06:13 PM PDT 24	May 26 04:52:23 PM PDT 24	20749305126 ps
T68	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.1048194308			May 26 03:53:30 PM PDT 24	May 26 03:58:24 PM PDT 24	3463926352 ps
T2	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.3486603438			May 26 03:53:22 PM PDT 24	May 26 03:58:48 PM PDT 24	3390538310 ps
T447	/workspace/coverage/default/1.chip_sw_edn_kat.136212702			May 26 03:59:56 PM PDT 24	May 26 04:12:50 PM PDT 24	3154467136 ps
T149	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.4273724931			May 26 03:47:58 PM PDT 24	May 26 03:56:16 PM PDT 24	3903481350 ps
T293	/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.4284602481			May 26 04:02:05 PM PDT 24	May 26 04:06:38 PM PDT 24	3136367353 ps
T289	/workspace/coverage/default/49.chip_sw_all_escalation_resets.44719710			May 26 04:19:28 PM PDT 24	May 26 04:29:58 PM PDT 24	4645761602 ps
T448	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac.375856884			May 26 03:51:13 PM PDT 24	May 26 03:58:00 PM PDT 24	3397792840 ps
T449	/workspace/coverage/default/0.rom_e2e_asm_init_rma.4181900238			May 26 04:02:22 PM PDT 24	May 26 05:22:18 PM PDT 24	14176494544 ps
T336	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.2672858714			May 26 03:54:37 PM PDT 24	May 26 05:00:53 PM PDT 24	13488817896 ps
T171	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2621689776			May 26 04:01:02 PM PDT 24	May 26 04:08:14 PM PDT 24	4712707574 ps
T48	/workspace/coverage/default/55.chip_sw_all_escalation_resets.3623131581			May 26 04:20:14 PM PDT 24	May 26 04:28:19 PM PDT 24	4981052200 ps
T912	/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1950399590			May 26 04:11:47 PM PDT 24	May 26 04:31:14 PM PDT 24	6834284570 ps
T755	/workspace/coverage/default/12.chip_sw_all_escalation_resets.4127732292			May 26 04:15:53 PM PDT 24	May 26 04:23:56 PM PDT 24	4912501510 ps
T913	/workspace/coverage/default/1.chip_sw_clkmgr_smoketest.179160585			May 26 04:03:05 PM PDT 24	May 26 04:07:12 PM PDT 24	3264463048 ps
T914	/workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.3402591888			May 26 04:06:40 PM PDT 24	May 26 04:24:34 PM PDT 24	7119485352 ps
T216	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.3320747218			May 26 03:50:00 PM PDT 24	May 26 04:01:57 PM PDT 24	4532247653 ps
T915	/workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.4279184948			May 26 04:12:51 PM PDT 24	May 26 04:18:54 PM PDT 24	5780844480 ps
T323	/workspace/coverage/default/58.chip_sw_all_escalation_resets.2030650741			May 26 04:20:59 PM PDT 24	May 26 04:30:19 PM PDT 24	5810787534 ps
T826	/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.1492855747			May 26 04:22:39 PM PDT 24	May 26 04:29:20 PM PDT 24	3711610418 ps
T692	/workspace/coverage/default/2.chip_sw_aes_masking_off.937761460			May 26 04:08:06 PM PDT 24	May 26 04:15:21 PM PDT 24	3120571009 ps
T294	/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.3463537840			May 26 04:10:42 PM PDT 24	May 26 04:15:14 PM PDT 24	3380611873 ps
T714	/workspace/coverage/default/50.chip_sw_all_escalation_resets.1675898852			May 26 04:19:11 PM PDT 24	May 26 04:29:30 PM PDT 24	5638561500 ps
T770	/workspace/coverage/default/74.chip_sw_all_escalation_resets.1107681805			May 26 04:21:40 PM PDT 24	May 26 04:35:17 PM PDT 24	5011706272 ps
T367	/workspace/coverage/default/1.rom_e2e_shutdown_output.915984227			May 26 04:07:26 PM PDT 24	May 26 04:57:32 PM PDT 24	23304170629 ps
T809	/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.2994116362			May 26 04:22:56 PM PDT 24	May 26 04:28:30 PM PDT 24	3557517780 ps
T790	/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.439294264			May 26 04:23:23 PM PDT 24	May 26 04:29:02 PM PDT 24	4352800458 ps
T173	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3740632390			May 26 04:11:04 PM PDT 24	May 26 04:20:08 PM PDT 24	5028335768 ps
T222	/workspace/coverage/default/1.chip_sw_kmac_entropy.4175870958			May 26 03:54:27 PM PDT 24	May 26 03:58:43 PM PDT 24	2282107852 ps
T254	/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.329306276			May 26 04:06:38 PM PDT 24	May 26 04:38:31 PM PDT 24	14685230588 ps
T916	/workspace/coverage/default/0.chip_sw_clkmgr_jitter.2795617280			May 26 03:48:46 PM PDT 24	May 26 03:53:31 PM PDT 24	2925562318 ps
T917	/workspace/coverage/default/0.chip_sw_aon_timer_smoketest.1878512215			May 26 03:54:10 PM PDT 24	May 26 03:59:32 PM PDT 24	3681417520 ps
T918	/workspace/coverage/default/0.chip_sw_example_rom.2436652200			May 26 03:46:28 PM PDT 24	May 26 03:48:55 PM PDT 24	3077432022 ps
T792	/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.4196919362			May 26 04:25:24 PM PDT 24	May 26 04:32:02 PM PDT 24	3344899846 ps
T195	/workspace/coverage/default/1.chip_tap_straps_dev.3145481348			May 26 04:02:28 PM PDT 24	May 26 04:08:35 PM PDT 24	4316977862 ps
T337	/workspace/coverage/default/2.rom_e2e_shutdown_output.1550660395			May 26 04:16:35 PM PDT 24	May 26 05:15:53 PM PDT 24	22083026155 ps
T919	/workspace/coverage/default/2.rom_e2e_smoke.3133012811			May 26 04:16:42 PM PDT 24	May 26 05:26:32 PM PDT 24	14521928676 ps
T920	/workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.1981298128			May 26 03:50:55 PM PDT 24	May 26 03:57:33 PM PDT 24	3652958872 ps
T921	/workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.2847603509			May 26 03:51:44 PM PDT 24	May 26 04:12:49 PM PDT 24	5414212938 ps
T767	/workspace/coverage/default/91.chip_sw_all_escalation_resets.1781816313			May 26 04:23:05 PM PDT 24	May 26 04:33:12 PM PDT 24	5363526204 ps
T95	/workspace/coverage/default/2.chip_sw_spi_device_tpm.549836035			May 26 04:05:59 PM PDT 24	May 26 04:12:21 PM PDT 24	3685159859 ps
T922	/workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.1197410402			May 26 03:49:13 PM PDT 24	May 26 03:56:18 PM PDT 24	4482295048 ps
T923	/workspace/coverage/default/0.rom_e2e_asm_init_prod.3158658204			May 26 04:01:30 PM PDT 24	May 26 05:11:46 PM PDT 24	14096655705 ps
T107	/workspace/coverage/default/4.chip_tap_straps_rma.369530680			May 26 04:14:29 PM PDT 24	May 26 04:17:29 PM PDT 24	2551448595 ps
T73	/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.1080346638			May 26 03:53:44 PM PDT 24	May 26 03:57:19 PM PDT 24	2579287712 ps
T322	/workspace/coverage/default/2.chip_sw_rv_timer_smoketest.1321535189			May 26 04:12:42 PM PDT 24	May 26 04:17:02 PM PDT 24	2648798348 ps
T693	/workspace/coverage/default/10.chip_sw_all_escalation_resets.1405079745			May 26 04:16:07 PM PDT 24	May 26 04:28:07 PM PDT 24	4872176500 ps
T391	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.2242148945			May 26 03:55:56 PM PDT 24	May 26 05:47:35 PM PDT 24	22794777572 ps
T243	/workspace/coverage/default/2.chip_sw_alert_handler_escalation.1884944952			May 26 04:07:55 PM PDT 24	May 26 04:16:41 PM PDT 24	5057634976 ps
T369	/workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3315180170			May 26 04:03:11 PM PDT 24	May 26 04:11:37 PM PDT 24	4658667000 ps
T924	/workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.799333469			May 26 03:49:53 PM PDT 24	May 26 03:56:32 PM PDT 24	4403224330 ps
T718	/workspace/coverage/default/79.chip_sw_all_escalation_resets.3184782322			May 26 04:22:07 PM PDT 24	May 26 04:30:12 PM PDT 24	3857886430 ps
T810	/workspace/coverage/default/83.chip_sw_all_escalation_resets.1602945443			May 26 04:23:04 PM PDT 24	May 26 04:30:42 PM PDT 24	5406347848 ps
T925	/workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.95931047			May 26 04:03:55 PM PDT 24	May 26 04:08:40 PM PDT 24	3502471680 ps
T228	/workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.1142722959			May 26 03:46:52 PM PDT 24	May 26 04:10:39 PM PDT 24	9458041780 ps
T926	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.47052059			May 26 03:59:55 PM PDT 24	May 26 04:55:55 PM PDT 24	10704519052 ps
T280	/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.3540425356			May 26 04:16:28 PM PDT 24	May 26 04:57:17 PM PDT 24	13705985096 ps
T373	/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.1491802239			May 26 04:18:54 PM PDT 24	May 26 04:25:47 PM PDT 24	3493017540 ps
T927	/workspace/coverage/default/1.chip_sw_flash_ctrl_access.3700695398			May 26 03:56:00 PM PDT 24	May 26 04:15:55 PM PDT 24	4950013246 ps
T928	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.1494282982			May 26 03:48:19 PM PDT 24	May 26 04:09:10 PM PDT 24	8524584036 ps
T929	/workspace/coverage/default/0.rom_e2e_asm_init_prod_end.2985295598			May 26 03:59:04 PM PDT 24	May 26 04:53:42 PM PDT 24	14718872447 ps
T262	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops.3531514453			May 26 04:06:15 PM PDT 24	May 26 04:18:23 PM PDT 24	4195252770 ps
T930	/workspace/coverage/default/1.chip_sw_example_flash.2238456954			May 26 03:52:50 PM PDT 24	May 26 03:57:26 PM PDT 24	2120723992 ps