Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.spi_device_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	139236	1			T23	17		T24	90		T25	3
values[2]	9757	1			T23	1		T137	1		T451	3
values[3]	3908	1			T550	1		T474	44		T558	101
values[4]	2466	1			T550	1		T474	25		T558	57
values[5]	1523	1			T550	1		T474	5		T558	34
values[6]	1061	1			T550	1		T474	1		T558	18
values[7]	881	1			T550	1		T558	3		T554	13
values[8]	648	1			T550	1		T554	7		T683	14
values[9]	543	1			T550	1		T554	3		T683	19
values[10]	399	1			T550	1		T683	11		T838	1
values[11]	426	1			T550	1		T683	11		T838	1
values[12]	377	1			T550	1		T683	19		T838	1
values[13]	356	1			T550	1		T683	11		T838	1
values[14]	316	1			T550	1		T683	8		T838	1
values[15]	305	1			T550	1		T683	17		T838	1
values[16]	307	1			T550	1		T683	21		T838	1
values[17]	265	1			T550	1		T683	18		T838	1
values[18]	326	1			T550	1		T683	31		T838	1
values[19]	256	1			T550	1		T683	14		T838	1
values[20]	286	1			T550	1		T683	8		T838	1
values[21]	246	1			T550	1		T683	5		T838	1
values[22]	236	1			T550	1		T683	11		T838	1
values[23]	268	1			T550	1		T683	9		T838	1
values[24]	254	1			T550	1		T683	25		T838	1
values[25]	301	1			T550	1		T683	12		T838	1
values[26]	294	1			T550	1		T683	11		T838	1
values[27]	277	1			T550	1		T683	10		T838	1
values[28]	255	1			T550	1		T683	8		T838	1
values[29]	288	1			T550	1		T683	14		T838	1
values[30]	303	1			T550	1		T683	15		T838	1
values[31]	239	1			T550	1		T683	16		T838	1
values[32]	258	1			T550	1		T683	17		T838	1
values[33]	283	1			T550	1		T683	15		T838	1
values[34]	226	1			T550	1		T683	14		T838	1
values[35]	253	1			T550	1		T683	18		T838	1
values[36]	280	1			T550	1		T683	8		T838	1
values[37]	261	1			T550	1		T683	10		T838	1
values[38]	266	1			T550	1		T683	10		T838	1
values[39]	317	1			T550	1		T683	9		T838	1
values[40]	288	1			T550	1		T683	9		T838	1
values[41]	278	1			T550	1		T683	19		T838	1
values[42]	242	1			T550	1		T683	14		T838	1
values[43]	254	1			T550	1		T683	23		T838	1
values[44]	248	1			T550	1		T683	19		T838	1
values[45]	266	1			T550	1		T683	26		T838	2
values[46]	239	1			T550	1		T683	23		T838	1
values[47]	261	1			T550	1		T683	12		T838	1
values[48]	228	1			T550	1		T683	21		T838	1
values[49]	252	1			T550	1		T683	14		T838	1
values[50]	263	1			T550	1		T683	10		T838	1
values[51]	234	1			T550	1		T683	22		T838	1
values[52]	206	1			T550	1		T683	7		T838	1
values[53]	258	1			T550	1		T683	17		T838	1
values[54]	279	1			T550	1		T683	10		T838	1
values[55]	296	1			T550	1		T683	18		T838	1
values[56]	258	1			T550	1		T683	15		T838	1
values[57]	235	1			T550	1		T683	18		T838	1
values[58]	226	1			T550	1		T683	18		T838	1
values[59]	200	1			T550	1		T683	14		T838	1
values[60]	226	1			T550	1		T683	15		T838	1
values[61]	216	1			T550	1		T683	22		T838	1
values[62]	180	1			T550	1		T683	24		T838	1
values[63]	155	1			T550	1		T683	11		T838	1
values[64]	156	1			T550	1		T683	13		T838	1
values[65]	145	1			T550	1		T683	6		T838	1
values[66]	177	1			T550	1		T683	15		T838	1
values[67]	169	1			T550	1		T683	7		T838	1
values[68]	160	1			T550	1		T683	6		T838	2
values[69]	148	1			T550	1		T683	6		T838	1
values[70]	127	1			T550	1		T683	4		T838	1
values[71]	112	1			T550	1		T683	6		T838	1
values[72]	84	1			T550	1		T838	1		T835	14
values[73]	81	1			T550	1		T838	1		T835	12
values[74]	79	1			T550	1		T838	1		T835	13
values[75]	94	1			T550	1		T838	1		T835	6
values[76]	96	1			T550	1		T838	1		T835	6
values[77]	96	1			T550	1		T838	1		T835	9
values[78]	86	1			T550	1		T838	1		T835	8
values[79]	98	1			T550	1		T838	1		T835	11
values[80]	105	1			T550	1		T838	1		T835	5
values[81]	95	1			T550	1		T838	1		T835	14
values[82]	72	1			T550	1		T838	1		T835	3
values[83]	61	1			T550	1		T838	1		T835	2
values[84]	95	1			T550	1		T838	1		T835	6
values[85]	81	1			T550	1		T838	1		T835	3
values[86]	82	1			T550	1		T838	1		T835	4
values[87]	90	1			T550	1		T838	1		T835	5
values[88]	101	1			T550	1		T838	3		T835	1
values[89]	91	1			T550	1		T838	5		T835	9
values[90]	82	1			T550	1		T838	1		T835	4
values[91]	82	1			T550	1		T838	1		T835	3
values[92]	83	1			T550	1		T838	6		T835	6
values[93]	87	1			T550	1		T838	1		T835	4
values[94]	70	1			T550	1		T838	2		T835	4
values[95]	80	1			T550	1		T838	1		T835	3
values[96]	77	1			T550	1		T838	2		T835	5
values[97]	92	1			T550	1		T838	5		T835	5
values[98]	98	1			T550	1		T838	3		T835	5
values[99]	74	1			T550	1		T838	1		T835	5
values[100]	67	1			T550	1		T838	2		T835	6
values[101]	87	1			T550	1		T838	7		T835	5
values[102]	88	1			T550	3		T838	1		T835	1
values[103]	80	1			T550	1		T838	1		T835	3
values[104]	73	1			T550	3		T838	1		T835	3
values[105]	65	1			T550	2		T838	1		T835	5
values[106]	58	1			T550	1		T838	2		T835	2
values[107]	58	1			T550	4		T838	4		T836	2
values[108]	79	1			T550	5		T838	2		T836	2
values[109]	70	1			T550	1		T838	6		T836	1
values[110]	83	1			T550	1		T838	4		T836	6
values[111]	77	1			T550	1		T838	2		T836	3
values[112]	63	1			T550	2		T838	4		T836	4
values[113]	57	1			T550	1		T838	8		T836	1
values[114]	53	1			T550	4		T838	1		T836	1
values[115]	59	1			T550	2		T838	4		T836	4
values[116]	62	1			T550	1		T838	1		T836	3
values[117]	81	1			T550	3		T838	3		T836	1
values[118]	64	1			T550	1		T838	1		T836	2
values[119]	62	1			T550	1		T838	1		T836	2
values[120]	59	1			T550	3		T838	5		T836	2
values[121]	66	1			T550	3		T838	2		T836	4
values[122]	55	1			T550	1		T838	1		T836	1
values[123]	44	1			T550	1		T838	1		T836	1
values[124]	59	1			T550	1		T838	4		T836	3
values[125]	81	1			T550	1		T838	1		T836	1
values[126]	104	1			T550	3		T838	1		T836	1
values[127]	744	1			T550	26		T838	35		T836	29
values[128]	6333	1			T550	317		T838	308		T836	262