Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.spi_host1_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	144309	1			T23	14		T24	116		T25	8
values[2]	10168	1			T23	1		T137	2		T550	1
values[3]	4925	1			T550	1		T554	96		T683	9
values[4]	2697	1			T550	1		T554	35		T683	15
values[5]	1636	1			T550	1		T554	11		T683	8
values[6]	1048	1			T550	1		T683	9		T850	11
values[7]	881	1			T550	1		T683	9		T850	13
values[8]	671	1			T550	1		T683	4		T850	3
values[9]	645	1			T550	1		T683	11		T850	14
values[10]	584	1			T550	1		T683	8		T850	13
values[11]	485	1			T550	1		T683	12		T850	11
values[12]	510	1			T550	1		T683	8		T850	5
values[13]	500	1			T550	1		T683	17		T850	6
values[14]	501	1			T550	1		T683	9		T850	11
values[15]	444	1			T550	2		T683	6		T850	5
values[16]	459	1			T550	1		T683	7		T850	6
values[17]	462	1			T550	1		T683	5		T850	20
values[18]	483	1			T550	1		T683	20		T850	14
values[19]	418	1			T550	1		T683	11		T850	7
values[20]	453	1			T550	1		T683	9		T850	10
values[21]	419	1			T550	1		T683	4		T850	9
values[22]	420	1			T550	1		T683	10		T850	11
values[23]	434	1			T550	1		T683	8		T850	9
values[24]	408	1			T550	1		T683	30		T850	16
values[25]	396	1			T550	1		T683	17		T850	10
values[26]	394	1			T550	1		T683	7		T850	6
values[27]	354	1			T550	1		T683	3		T850	8
values[28]	338	1			T550	1		T683	5		T850	5
values[29]	315	1			T550	1		T683	3		T850	4
values[30]	333	1			T550	1		T683	12		T850	17
values[31]	371	1			T550	1		T683	25		T850	32
values[32]	316	1			T550	1		T683	10		T850	5
values[33]	366	1			T550	1		T683	7		T850	9
values[34]	295	1			T550	1		T683	5		T850	5
values[35]	381	1			T550	1		T683	11		T850	15
values[36]	321	1			T550	1		T683	21		T850	14
values[37]	326	1			T550	1		T683	18		T850	13
values[38]	343	1			T550	1		T683	12		T850	5
values[39]	287	1			T550	1		T683	4		T850	10
values[40]	269	1			T550	1		T683	4		T850	19
values[41]	317	1			T550	1		T683	6		T850	16
values[42]	267	1			T550	1		T683	3		T850	4
values[43]	243	1			T550	1		T850	8		T857	17
values[44]	245	1			T550	1		T850	5		T857	11
values[45]	260	1			T550	1		T850	10		T857	11
values[46]	261	1			T550	1		T850	8		T857	9
values[47]	257	1			T550	1		T850	27		T857	8
values[48]	254	1			T550	1		T850	6		T857	14
values[49]	172	1			T550	1		T857	6		T492	6
values[50]	155	1			T550	1		T857	6		T492	3
values[51]	143	1			T550	1		T857	6		T492	4
values[52]	165	1			T550	1		T857	14		T492	10
values[53]	110	1			T550	1		T857	15		T492	9
values[54]	113	1			T550	1		T857	6		T492	45
values[55]	85	1			T550	1		T857	20		T492	8
values[56]	86	1			T550	1		T857	19		T671	4
values[57]	74	1			T550	1		T857	7		T671	1
values[58]	59	1			T550	1		T671	1		T866	1
values[59]	50	1			T550	1		T671	6		T866	1
values[60]	43	1			T550	1		T671	3		T866	1
values[61]	40	1			T550	1		T671	8		T866	1
values[62]	40	1			T550	1		T671	2		T866	1
values[63]	42	1			T550	1		T671	1		T866	1
values[64]	42	1			T550	1		T671	3		T866	1
values[65]	48	1			T550	1		T671	2		T866	1
values[66]	59	1			T550	1		T671	4		T866	1
values[67]	50	1			T550	1		T671	1		T866	1
values[68]	43	1			T550	1		T671	5		T866	1
values[69]	35	1			T550	1		T671	2		T866	2
values[70]	39	1			T550	1		T671	7		T866	1
values[71]	44	1			T550	1		T671	2		T866	1
values[72]	44	1			T550	1		T671	1		T866	1
values[73]	60	1			T550	1		T671	5		T866	1
values[74]	44	1			T550	1		T671	2		T866	1
values[75]	34	1			T550	1		T671	3		T866	1
values[76]	37	1			T550	1		T671	2		T866	1
values[77]	37	1			T550	1		T671	3		T866	1
values[78]	39	1			T550	1		T671	4		T866	1
values[79]	42	1			T550	1		T671	5		T866	1
values[80]	39	1			T550	1		T671	5		T866	1
values[81]	63	1			T550	1		T671	8		T866	1
values[82]	55	1			T550	1		T671	7		T866	1
values[83]	45	1			T550	1		T671	12		T866	1
values[84]	37	1			T550	1		T671	2		T866	1
values[85]	43	1			T550	1		T671	3		T866	1
values[86]	57	1			T550	1		T671	9		T866	1
values[87]	48	1			T550	1		T671	9		T866	1
values[88]	59	1			T550	1		T671	17		T866	1
values[89]	52	1			T550	1		T671	14		T866	1
values[90]	45	1			T550	1		T671	13		T866	1
values[91]	44	1			T550	1		T671	12		T866	1
values[92]	59	1			T550	1		T671	16		T866	1
values[93]	39	1			T550	1		T671	3		T866	1
values[94]	57	1			T550	1		T671	7		T866	1
values[95]	51	1			T550	1		T671	6		T866	1
values[96]	45	1			T550	1		T671	3		T866	1
values[97]	44	1			T550	1		T671	4		T866	1
values[98]	36	1			T550	1		T671	1		T866	1
values[99]	44	1			T550	1		T671	2		T866	1
values[100]	31	1			T550	1		T671	3		T866	1
values[101]	51	1			T550	1		T671	4		T866	1
values[102]	38	1			T550	1		T671	1		T866	1
values[103]	37	1			T550	1		T671	1		T866	1
values[104]	33	1			T550	1		T671	4		T866	2
values[105]	31	1			T550	1		T671	4		T866	2
values[106]	33	1			T550	1		T671	3		T866	2
values[107]	37	1			T550	1		T671	4		T866	1
values[108]	32	1			T550	1		T671	3		T866	1
values[109]	45	1			T550	1		T671	6		T866	1
values[110]	39	1			T550	1		T671	10		T866	1
values[111]	47	1			T550	1		T671	9		T866	1
values[112]	32	1			T550	1		T671	10		T866	1
values[113]	37	1			T550	1		T671	4		T866	4
values[114]	36	1			T550	2		T671	3		T866	1
values[115]	41	1			T550	1		T671	6		T866	1
values[116]	38	1			T550	1		T671	2		T866	1
values[117]	21	1			T550	1		T866	1		T860	1
values[118]	33	1			T550	2		T866	1		T860	1
values[119]	39	1			T550	5		T866	2		T860	2
values[120]	35	1			T550	3		T866	4		T860	2
values[121]	36	1			T550	1		T866	6		T860	1
values[122]	48	1			T550	4		T866	1		T860	1
values[123]	31	1			T550	1		T866	1		T860	3
values[124]	30	1			T550	1		T866	1		T860	1
values[125]	39	1			T550	3		T866	1		T860	1
values[126]	84	1			T550	4		T866	5		T860	5
values[127]	1000	1			T550	55		T866	69		T860	76
values[128]	4766	1			T550	311		T866	308		T860	296