Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_ret_aon__ram_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	141322	1			T23	15		T24	90		T25	5
values[2]	9996	1			T137	2		T451	1		T550	1
values[3]	3724	1			T137	2		T550	1		T475	72
values[4]	2251	1			T550	1		T475	25		T554	11
values[5]	1466	1			T550	1		T475	7		T554	15
values[6]	1016	1			T550	1		T475	11		T554	15
values[7]	673	1			T550	1		T475	16		T554	10
values[8]	481	1			T550	1		T475	12		T554	12
values[9]	384	1			T550	1		T475	1		T554	8
values[10]	423	1			T550	1		T554	10		T839	1
values[11]	356	1			T550	1		T554	4		T839	1
values[12]	346	1			T550	1		T554	2		T839	1
values[13]	348	1			T550	1		T554	9		T839	1
values[14]	310	1			T550	1		T554	5		T839	1
values[15]	298	1			T550	1		T554	5		T839	1
values[16]	276	1			T550	1		T554	2		T839	1
values[17]	302	1			T550	1		T554	2		T839	1
values[18]	245	1			T550	1		T554	2		T839	1
values[19]	264	1			T550	1		T554	4		T839	1
values[20]	270	1			T550	1		T554	3		T839	1
values[21]	299	1			T550	1		T554	2		T839	1
values[22]	311	1			T550	1		T554	3		T839	1
values[23]	291	1			T550	2		T554	2		T839	1
values[24]	243	1			T550	1		T554	5		T839	1
values[25]	246	1			T550	1		T554	3		T839	1
values[26]	294	1			T550	1		T554	7		T839	1
values[27]	308	1			T550	1		T554	7		T839	1
values[28]	320	1			T550	1		T554	2		T839	1
values[29]	305	1			T550	1		T554	2		T839	1
values[30]	265	1			T550	1		T554	3		T839	1
values[31]	278	1			T550	1		T554	6		T839	1
values[32]	280	1			T550	1		T554	8		T839	1
values[33]	246	1			T550	1		T554	6		T839	1
values[34]	295	1			T550	1		T554	7		T839	1
values[35]	279	1			T550	1		T554	7		T839	1
values[36]	268	1			T550	1		T554	5		T839	1
values[37]	301	1			T550	1		T554	2		T839	1
values[38]	268	1			T550	1		T554	2		T839	1
values[39]	272	1			T550	1		T554	6		T839	1
values[40]	257	1			T550	1		T554	2		T839	1
values[41]	281	1			T550	1		T554	4		T839	1
values[42]	273	1			T550	1		T554	7		T839	1
values[43]	229	1			T550	1		T554	3		T839	1
values[44]	248	1			T550	1		T554	5		T839	1
values[45]	248	1			T550	1		T554	4		T839	1
values[46]	237	1			T550	1		T554	2		T839	1
values[47]	223	1			T550	1		T554	2		T839	1
values[48]	255	1			T550	1		T554	2		T839	1
values[49]	238	1			T550	1		T554	3		T839	1
values[50]	242	1			T550	1		T554	2		T839	1
values[51]	248	1			T550	1		T554	1		T839	1
values[52]	262	1			T550	1		T554	2		T839	1
values[53]	253	1			T550	1		T554	1		T839	1
values[54]	227	1			T550	1		T554	2		T839	1
values[55]	187	1			T550	1		T554	1		T839	1
values[56]	223	1			T550	1		T554	5		T839	1
values[57]	195	1			T550	1		T554	1		T839	1
values[58]	181	1			T550	1		T554	1		T839	1
values[59]	247	1			T550	1		T554	4		T839	1
values[60]	188	1			T550	1		T554	2		T839	1
values[61]	196	1			T550	1		T554	1		T839	1
values[62]	216	1			T550	1		T554	3		T839	1
values[63]	207	1			T550	1		T554	1		T839	1
values[64]	150	1			T550	1		T554	2		T839	1
values[65]	175	1			T550	1		T554	4		T839	1
values[66]	187	1			T550	1		T554	4		T839	1
values[67]	195	1			T550	1		T554	13		T839	1
values[68]	193	1			T550	1		T554	17		T839	1
values[69]	149	1			T550	1		T554	20		T839	1
values[70]	148	1			T550	1		T554	7		T839	1
values[71]	141	1			T550	1		T554	5		T839	1
values[72]	127	1			T550	1		T554	3		T839	1
values[73]	120	1			T550	1		T554	19		T839	1
values[74]	111	1			T550	1		T554	13		T839	1
values[75]	105	1			T550	1		T554	10		T839	1
values[76]	86	1			T550	1		T554	11		T839	1
values[77]	57	1			T550	1		T554	3		T839	1
values[78]	58	1			T550	1		T554	9		T839	1
values[79]	69	1			T550	1		T554	9		T839	1
values[80]	62	1			T550	1		T554	3		T839	1
values[81]	68	1			T550	1		T554	7		T839	1
values[82]	58	1			T550	1		T554	1		T839	1
values[83]	63	1			T550	1		T554	2		T839	1
values[84]	90	1			T550	1		T554	10		T839	1
values[85]	70	1			T550	1		T554	7		T839	1
values[86]	76	1			T550	1		T554	6		T839	1
values[87]	52	1			T550	1		T839	1		T847	6
values[88]	88	1			T550	1		T839	1		T847	3
values[89]	63	1			T550	1		T839	1		T847	4
values[90]	71	1			T550	1		T839	1		T847	3
values[91]	61	1			T550	1		T839	1		T847	3
values[92]	70	1			T550	1		T839	1		T847	6
values[93]	61	1			T550	1		T839	1		T847	2
values[94]	79	1			T550	1		T839	1		T847	2
values[95]	71	1			T550	1		T839	1		T847	4
values[96]	82	1			T550	1		T839	1		T847	5
values[97]	72	1			T550	1		T839	1		T847	4
values[98]	75	1			T550	1		T839	1		T847	5
values[99]	59	1			T550	1		T839	1		T847	2
values[100]	61	1			T550	1		T839	1		T847	3
values[101]	64	1			T550	1		T839	1		T847	3
values[102]	61	1			T550	1		T839	1		T847	4
values[103]	64	1			T550	1		T839	3		T847	7
values[104]	49	1			T550	1		T839	1		T847	7
values[105]	67	1			T550	1		T839	1		T847	2
values[106]	72	1			T550	1		T839	4		T847	4
values[107]	66	1			T550	1		T839	2		T847	4
values[108]	67	1			T550	4		T839	1		T847	6
values[109]	82	1			T550	4		T839	2		T847	2
values[110]	82	1			T550	4		T839	7		T847	3
values[111]	88	1			T550	1		T839	4		T847	7
values[112]	57	1			T550	4		T839	1		T847	4
values[113]	83	1			T550	1		T839	2		T847	6
values[114]	75	1			T550	2		T839	2		T847	3
values[115]	64	1			T550	7		T839	1		T847	4
values[116]	68	1			T550	1		T839	2		T847	5
values[117]	72	1			T550	2		T839	2		T847	3
values[118]	74	1			T550	3		T839	4		T847	5
values[119]	60	1			T550	2		T839	3		T847	9
values[120]	68	1			T550	2		T839	1		T847	4
values[121]	94	1			T550	1		T839	2		T847	4
values[122]	64	1			T550	1		T839	1		T847	4
values[123]	62	1			T550	2		T839	2		T847	4
values[124]	67	1			T550	1		T839	1		T847	2
values[125]	87	1			T550	2		T839	3		T847	6
values[126]	132	1			T550	2		T839	1		T847	3
values[127]	925	1			T550	39		T839	40		T847	52
values[128]	7119	1			T550	349		T839	393		T847	524