Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	470	1			T23	4		T475	2		T464	2
all_values[1]	472	1			T23	7		T318	1		T475	4
all_values[2]	481	1			T23	5		T475	2		T462	5
all_values[3]	480	1			T23	3		T474	1		T854	1
all_values[4]	513	1			T23	2		T474	2		T475	2
all_values[5]	462	1			T23	5		T25	1		T550	1
all_values[6]	508	1			T23	4		T318	1		T474	4
all_values[7]	516	1			T23	2		T318	1		T474	2
all_values[8]	481	1			T23	3		T318	1		T550	1
all_values[9]	502	1			T23	4		T318	1		T474	2
all_values[10]	467	1			T23	7		T474	3		T475	2
all_values[11]	458	1			T23	3		T475	3		T462	4
all_values[12]	480	1			T23	4		T474	3		T475	1
all_values[13]	481	1			T23	1		T474	4		T475	5
all_values[14]	515	1			T23	4		T474	4		T475	4
all_values[15]	466	1			T23	3		T318	1		T550	1
all_values[16]	514	1			T23	2		T474	3		T475	5
all_values[17]	431	1			T23	3		T550	1		T474	1
all_values[18]	472	1			T23	3		T475	1		T462	4
all_values[19]	466	1			T23	4		T474	2		T475	5
all_values[20]	472	1			T23	1		T318	1		T558	1
all_values[21]	461	1			T23	1		T474	1		T475	2
all_values[22]	527	1			T23	3		T475	5		T464	1
all_values[23]	471	1			T23	1		T318	1		T550	1
all_values[24]	478	1			T23	4		T474	1		T475	2
all_values[25]	506	1			T23	2		T318	1		T474	1
all_values[26]	493	1			T23	1		T474	1		T475	1
all_values[27]	462	1			T23	2		T475	5		T462	7
all_values[28]	508	1			T23	4		T25	1		T318	1
all_values[29]	453	1			T23	2		T475	1		T464	1
all_values[30]	510	1			T23	4		T318	1		T462	5
all_values[31]	483	1			T23	2		T318	1		T474	1
all_values[32]	503	1			T23	3		T550	1		T474	2
all_values[33]	473	1			T23	4		T550	1		T474	4
all_values[34]	466	1			T23	2		T474	2		T475	3
all_values[35]	482	1			T23	3		T318	2		T474	3
all_values[36]	475	1			T23	4		T474	5		T475	3
all_values[37]	450	1			T23	5		T475	3		T462	3
all_values[38]	507	1			T23	6		T474	1		T475	3
all_values[39]	473	1			T23	2		T462	3		T557	1
all_values[40]	479	1			T474	3		T475	2		T464	1
all_values[41]	502	1			T23	1		T318	2		T475	1
all_values[42]	486	1			T23	2		T550	2		T475	4
all_values[43]	470	1			T23	5		T474	1		T475	2
all_values[44]	511	1			T23	1		T474	3		T475	2
all_values[45]	492	1			T23	3		T550	1		T474	2
all_values[46]	495	1			T23	3		T550	1		T474	3
all_values[47]	460	1			T23	3		T318	1		T474	1
all_values[48]	453	1			T23	1		T474	2		T475	1
all_values[49]	466	1			T23	5		T474	2		T475	1