Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3778	1			T23	20		T24	1		T25	3
all_values[1]	3766	1			T23	25		T24	4		T25	6
all_values[2]	3713	1			T23	21		T24	1		T25	1
all_values[3]	3809	1			T23	16		T24	3		T25	4
all_values[4]	3720	1			T23	31		T25	4		T535	2
all_values[5]	3656	1			T23	27		T24	1		T25	2
all_values[6]	3694	1			T23	21		T24	9		T25	6
all_values[7]	3832	1			T23	20		T24	3		T25	4
all_values[8]	3811	1			T23	29		T24	1		T25	5
all_values[9]	3698	1			T23	37		T24	2		T25	6
all_values[10]	3731	1			T23	25		T24	4		T25	2
all_values[11]	3709	1			T23	22		T24	3		T25	5
all_values[12]	3698	1			T23	25		T24	2		T25	7
all_values[13]	3734	1			T23	25		T24	5		T25	1
all_values[14]	3647	1			T23	20		T25	5		T535	2
all_values[15]	3721	1			T23	31		T24	5		T25	1
all_values[16]	3728	1			T23	21		T24	3		T25	1
all_values[17]	3732	1			T23	23		T24	5		T25	6
all_values[18]	3753	1			T23	21		T24	4		T25	5
all_values[19]	3720	1			T23	18		T24	3		T25	3
all_values[20]	3720	1			T23	26		T24	4		T25	2
all_values[21]	3674	1			T23	25		T24	4		T25	5
all_values[22]	3746	1			T23	20		T24	3		T25	3
all_values[23]	3765	1			T23	26		T24	2		T25	4
all_values[24]	3748	1			T23	16		T24	4		T25	7
all_values[25]	3781	1			T23	16		T24	3		T25	3
all_values[26]	3810	1			T23	34		T25	2		T474	14
all_values[27]	3683	1			T23	19		T24	1		T25	3
all_values[28]	3575	1			T23	32		T24	3		T25	3
all_values[29]	3663	1			T23	19		T24	4		T25	2
all_values[30]	3780	1			T23	21		T24	2		T25	4
all_values[31]	3715	1			T23	31		T24	5		T25	4
all_values[32]	3733	1			T23	19		T24	3		T25	4
all_values[33]	3742	1			T23	27		T24	2		T25	6
all_values[34]	3771	1			T23	22		T24	3		T25	6
all_values[35]	3687	1			T23	26		T24	3		T25	5
all_values[36]	3738	1			T23	22		T24	2		T25	1
all_values[37]	3862	1			T23	26		T24	1		T25	7
all_values[38]	3704	1			T23	15		T24	1		T25	2
all_values[39]	3702	1			T23	18		T24	5		T25	4
all_values[40]	3806	1			T23	24		T24	4		T25	4
all_values[41]	3756	1			T23	24		T24	2		T25	6
all_values[42]	3735	1			T23	19		T24	2		T25	5
all_values[43]	3782	1			T23	28		T24	4		T25	2
all_values[44]	3669	1			T23	23		T24	2		T25	4
all_values[45]	3689	1			T23	18		T24	3		T25	5
all_values[46]	3859	1			T23	29		T24	3		T25	7
all_values[47]	3671	1			T23	21		T24	1		T25	5
all_values[48]	3839	1			T23	22		T24	3		T25	5
all_values[49]	3826	1			T23	22		T24	1		T25	2
all_values[50]	3667	1			T23	18		T24	2		T25	3
all_values[51]	3732	1			T23	21		T24	5		T25	3
all_values[52]	3753	1			T23	23		T24	4		T25	5
all_values[53]	3631	1			T23	24		T24	1		T25	1
all_values[54]	3700	1			T23	27		T24	2		T25	2
all_values[55]	3677	1			T23	23		T24	3		T25	3
all_values[56]	3728	1			T23	26		T24	1		T25	3
all_values[57]	3687	1			T23	27		T24	5		T25	2
all_values[58]	3714	1			T23	27		T24	2		T25	2
all_values[59]	3682	1			T23	24		T24	1		T25	3
all_values[60]	3734	1			T23	25		T24	3		T25	7
all_values[61]	3625	1			T23	18		T24	3		T25	2
all_values[62]	3715	1			T23	23		T25	4		T535	2
all_values[63]	3813	1			T23	24		T24	4		T25	4