Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_main__regs_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	154316	1			T73	256		T74	2		T75	54
values[2]	4711	1			T73	3		T75	3		T79	6
values[3]	2135	1			T663	20		T827	1		T789	1
values[4]	1507	1			T663	20		T789	1		T452	57
values[5]	1213	1			T663	11		T789	1		T452	68
values[6]	963	1			T663	12		T789	1		T452	73
values[7]	778	1			T663	35		T789	1		T452	44
values[8]	737	1			T663	53		T789	1		T452	20
values[9]	617	1			T663	28		T789	1		T452	12
values[10]	606	1			T663	30		T789	1		T452	4
values[11]	602	1			T663	19		T789	1		T452	4
values[12]	542	1			T663	17		T789	1		T452	1
values[13]	477	1			T663	6		T789	1		T452	13
values[14]	431	1			T663	3		T789	1		T452	10
values[15]	407	1			T789	1		T452	6		T502	1
values[16]	326	1			T789	1		T452	1		T502	1
values[17]	253	1			T789	1		T502	1		T812	1
values[18]	201	1			T789	1		T502	1		T812	1
values[19]	183	1			T789	1		T502	1		T812	1
values[20]	194	1			T789	1		T502	1		T812	1
values[21]	157	1			T789	1		T502	1		T812	1
values[22]	123	1			T789	1		T502	1		T812	1
values[23]	116	1			T789	1		T502	1		T812	1
values[24]	87	1			T789	1		T502	1		T812	1
values[25]	94	1			T789	1		T502	1		T812	1
values[26]	96	1			T789	1		T502	1		T812	1
values[27]	91	1			T789	1		T502	1		T812	1
values[28]	118	1			T789	1		T502	1		T812	1
values[29]	100	1			T789	1		T502	1		T812	1
values[30]	106	1			T789	1		T502	1		T812	1
values[31]	96	1			T789	1		T502	1		T812	1
values[32]	95	1			T789	1		T502	1		T812	1
values[33]	133	1			T789	1		T502	1		T812	1
values[34]	132	1			T789	1		T502	1		T812	1
values[35]	147	1			T789	1		T502	1		T812	1
values[36]	138	1			T789	1		T502	1		T812	1
values[37]	118	1			T789	1		T502	1		T812	1
values[38]	93	1			T789	1		T502	1		T812	1
values[39]	93	1			T789	1		T502	1		T812	1
values[40]	76	1			T789	1		T502	1		T812	1
values[41]	67	1			T789	1		T502	1		T812	1
values[42]	71	1			T789	1		T502	1		T812	1
values[43]	87	1			T789	1		T502	1		T812	1
values[44]	85	1			T789	1		T502	1		T812	1
values[45]	75	1			T789	1		T502	1		T812	1
values[46]	69	1			T789	1		T502	1		T812	1
values[47]	72	1			T789	1		T502	1		T812	1
values[48]	64	1			T789	1		T502	1		T812	1
values[49]	46	1			T789	1		T502	1		T812	1
values[50]	54	1			T789	1		T502	1		T812	1
values[51]	59	1			T789	1		T502	1		T812	1
values[52]	59	1			T789	1		T502	1		T812	1
values[53]	65	1			T789	1		T502	1		T812	1
values[54]	69	1			T789	1		T502	1		T812	1
values[55]	77	1			T789	1		T502	1		T812	1
values[56]	75	1			T789	1		T502	1		T812	1
values[57]	71	1			T789	1		T502	1		T812	1
values[58]	60	1			T789	1		T502	1		T812	1
values[59]	57	1			T789	1		T502	1		T812	1
values[60]	61	1			T789	1		T502	1		T812	1
values[61]	63	1			T789	1		T502	1		T812	1
values[62]	55	1			T789	1		T502	1		T812	1
values[63]	66	1			T789	1		T502	1		T812	1
values[64]	68	1			T789	1		T502	1		T812	1
values[65]	64	1			T789	1		T502	1		T812	1
values[66]	56	1			T789	1		T502	1		T812	1
values[67]	60	1			T789	1		T502	1		T812	1
values[68]	79	1			T789	1		T502	1		T812	1
values[69]	76	1			T789	1		T502	1		T812	1
values[70]	66	1			T789	1		T502	1		T812	1
values[71]	81	1			T789	1		T502	1		T812	1
values[72]	95	1			T789	1		T502	1		T812	1
values[73]	73	1			T789	1		T502	1		T812	1
values[74]	93	1			T789	1		T502	1		T812	1
values[75]	75	1			T789	1		T502	1		T812	1
values[76]	84	1			T789	1		T502	1		T812	1
values[77]	92	1			T789	1		T502	1		T812	1
values[78]	97	1			T789	1		T502	2		T812	1
values[79]	84	1			T789	1		T502	1		T812	1
values[80]	90	1			T789	1		T502	1		T812	1
values[81]	82	1			T789	1		T502	1		T812	1
values[82]	77	1			T789	1		T502	1		T812	1
values[83]	89	1			T789	1		T502	1		T812	1
values[84]	104	1			T789	1		T502	1		T812	1
values[85]	94	1			T789	1		T502	1		T812	1
values[86]	86	1			T789	1		T502	1		T812	1
values[87]	92	1			T789	1		T502	1		T812	1
values[88]	111	1			T789	1		T502	1		T812	1
values[89]	99	1			T789	1		T502	1		T812	1
values[90]	94	1			T789	1		T502	1		T812	1
values[91]	82	1			T789	1		T502	1		T812	3
values[92]	97	1			T789	1		T502	1		T812	5
values[93]	93	1			T789	1		T502	1		T812	5
values[94]	85	1			T789	1		T502	1		T812	1
values[95]	101	1			T789	1		T502	1		T812	1
values[96]	90	1			T789	1		T502	1		T812	5
values[97]	103	1			T789	1		T502	1		T812	4
values[98]	108	1			T789	1		T502	1		T812	2
values[99]	101	1			T789	1		T502	1		T812	1
values[100]	87	1			T789	1		T502	1		T812	1
values[101]	103	1			T789	1		T502	1		T812	1
values[102]	104	1			T789	1		T502	2		T812	1
values[103]	69	1			T789	1		T502	1		T812	1
values[104]	95	1			T789	1		T502	1		T812	5
values[105]	102	1			T789	2		T502	1		T812	1
values[106]	114	1			T789	2		T502	6		T812	2
values[107]	101	1			T789	1		T502	4		T812	7
values[108]	93	1			T789	1		T502	4		T812	1
values[109]	110	1			T789	3		T502	5		T812	1
values[110]	111	1			T789	2		T502	3		T812	4
values[111]	119	1			T789	1		T502	2		T812	5
values[112]	100	1			T789	3		T502	1		T812	1
values[113]	99	1			T789	3		T502	2		T812	3
values[114]	108	1			T789	4		T502	1		T812	2
values[115]	124	1			T789	1		T502	2		T812	2
values[116]	117	1			T789	3		T502	2		T812	3
values[117]	105	1			T789	2		T502	5		T812	4
values[118]	103	1			T789	1		T502	1		T812	1
values[119]	104	1			T789	1		T502	3		T812	2
values[120]	117	1			T789	1		T502	2		T812	2
values[121]	119	1			T789	1		T502	2		T812	1
values[122]	133	1			T789	2		T502	2		T812	1
values[123]	161	1			T789	4		T502	2		T812	1
values[124]	224	1			T789	1		T502	1		T812	2
values[125]	480	1			T789	4		T502	2		T812	3
values[126]	764	1			T789	19		T502	12		T812	11
values[127]	2458	1			T789	128		T502	101		T812	97
values[128]	4233	1			T789	240		T502	186		T812	150