Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.13	95.57	94.38	95.52		95.30	96.47	99.58

Total tests in report: 2874

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
39.81	39.81	45.02	45.02	43.04	43.04	33.06	33.06			58.06	58.06	59.27	59.27	0.39	0.39	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.4025569188
50.59	10.79	53.80	8.77	59.56	16.52	37.49	4.43			68.87	10.82	82.34	23.08	1.49	1.10	/workspace/coverage/cover_reg_top/3.chip_csr_rw.1474063326
57.26	6.67	63.78	9.98	61.15	1.59	42.49	5.00			69.23	0.36	82.34	0.00	24.56	23.06	/workspace/coverage/cover_reg_top/24.xbar_stress_all_with_error.1227764513
61.73	4.47	73.70	9.92	67.50	6.36	44.33	1.84			77.75	8.52	82.52	0.17	24.56	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_10.1359490297
65.17	3.44	73.70	0.00	67.50	0.00	44.33	0.00			77.75	0.00	82.52	0.00	45.19	20.63	/workspace/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.3305502177
68.49	3.33	79.81	6.11	71.87	4.37	48.28	3.95			79.80	2.04	86.01	3.50	45.19	0.00	/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.481505429
71.17	2.68	79.81	0.00	71.87	0.00	64.30	16.02			79.80	0.00	86.01	0.00	45.24	0.05	/workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.3303783661
73.58	2.41	79.81	0.00	71.87	0.00	64.30	0.00			79.80	0.00	86.01	0.00	59.70	14.46	/workspace/coverage/cover_reg_top/50.xbar_access_same_device_slow_rsp.1903978873
75.76	2.17	81.00	1.19	74.35	2.48	69.73	5.42			81.53	1.73	86.19	0.17	61.76	2.06	/workspace/coverage/default/0.chip_sw_alert_test.2595960547
77.63	1.87	83.72	2.73	78.14	3.79	70.19	0.47			84.88	3.35	87.06	0.87	61.76	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.3303016173
79.23	1.60	83.72	0.00	78.36	0.22	70.19	0.00			84.88	0.00	87.06	0.00	71.13	9.38	/workspace/coverage/cover_reg_top/73.xbar_stress_all_with_reset_error.2190590216
80.80	1.58	83.84	0.11	78.45	0.09	79.11	8.92			85.05	0.17	87.24	0.17	71.13	0.00	/workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.442172792
82.20	1.40	83.84	0.00	78.45	0.00	79.11	0.00			85.05	0.00	87.24	0.00	79.52	8.39	/workspace/coverage/cover_reg_top/33.xbar_access_same_device_slow_rsp.4064809813
83.58	1.38	85.44	1.61	79.72	1.27	79.96	0.85			86.47	1.41	90.38	3.15	79.52	0.00	/workspace/coverage/default/0.chip_jtag_csr_rw.3081121853
84.77	1.18	87.56	2.11	81.65	1.93	80.70	0.73			88.80	2.33	90.38	0.00	79.52	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_0.3278467739
85.75	0.98	88.25	0.69	81.94	0.29	85.22	4.52			89.00	0.20	90.56	0.17	79.52	0.00	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.2721688570
86.51	0.76	88.66	0.41	82.09	0.15	85.23	0.01			89.16	0.16	94.41	3.85	79.52	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.1441209509
87.26	0.75	88.66	0.00	82.10	0.01	85.23	0.00			89.16	0.00	94.41	0.00	84.03	4.51	/workspace/coverage/cover_reg_top/61.xbar_access_same_device_slow_rsp.138641844
87.93	0.67	89.82	1.17	83.05	0.96	85.97	0.74			90.29	1.13	94.41	0.00	84.03	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_20.2089444832
88.53	0.60	89.82	0.00	83.05	0.00	85.97	0.00			90.29	0.00	94.41	0.00	87.63	3.60	/workspace/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.2338654005
89.09	0.56	89.82	0.00	83.31	0.26	85.97	0.00			90.34	0.05	94.41	0.00	90.71	3.08	/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.3057571140
89.58	0.49	90.74	0.92	84.20	0.89	86.37	0.39			91.06	0.72	94.41	0.00	90.71	0.00	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3773361687
90.05	0.48	90.75	0.01	86.63	2.43	86.37	0.00			91.06	0.00	94.41	0.00	91.12	0.41	/workspace/coverage/cover_reg_top/0.chip_tl_errors.1576708760
90.52	0.46	91.28	0.53	87.59	0.95	86.79	0.42			91.92	0.87	94.41	0.00	91.12	0.00	/workspace/coverage/default/1.chip_sw_gpio_smoketest.1729523393
90.89	0.37	92.01	0.73	88.05	0.47	87.02	0.23			92.72	0.79	94.41	0.00	91.12	0.00	/workspace/coverage/default/1.chip_sw_plic_sw_irq.3867289078
91.25	0.36	92.01	0.00	88.38	0.32	87.02	0.00			92.72	0.01	94.41	0.00	92.97	1.86	/workspace/coverage/cover_reg_top/70.xbar_access_same_device.3821589695
91.57	0.32	92.90	0.89	88.79	0.41	87.37	0.35			92.98	0.25	94.41	0.00	92.99	0.01	/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.3028648427
91.87	0.30	92.90	0.00	88.90	0.11	87.37	0.00			92.98	0.00	94.41	0.00	94.67	1.68	/workspace/coverage/cover_reg_top/71.xbar_stress_all_with_error.3587098334
92.14	0.28	93.14	0.24	89.07	0.17	87.94	0.57			93.12	0.15	94.93	0.52	94.67	0.00	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.4060958121
92.41	0.27	93.15	0.01	89.08	0.01	89.52	1.58			93.12	0.00	94.93	0.00	94.67	0.00	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.1127816375
92.65	0.24	93.46	0.32	89.96	0.88	89.56	0.04			93.30	0.17	94.93	0.00	94.67	0.00	/workspace/coverage/cover_reg_top/16.chip_same_csr_outstanding.2831076890
92.87	0.22	93.46	0.00	90.05	0.09	89.56	0.00			93.30	0.00	94.93	0.00	95.91	1.25	/workspace/coverage/cover_reg_top/98.xbar_random_large_delays.3123096337
93.06	0.19	93.51	0.05	90.39	0.34	89.91	0.35			93.67	0.38	94.93	0.00	95.96	0.05	/workspace/coverage/default/1.chip_jtag_csr_rw.2086984306
93.24	0.18	93.51	0.00	90.39	0.00	90.98	1.07			93.67	0.00	94.93	0.00	95.96	0.00	/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.1247453378
93.41	0.17	93.51	0.00	90.39	0.00	90.98	0.00			93.67	0.00	94.93	0.00	96.99	1.03	/workspace/coverage/cover_reg_top/83.xbar_access_same_device_slow_rsp.1070449860
93.58	0.16	93.67	0.15	90.51	0.11	91.26	0.28			93.77	0.10	95.28	0.35	96.99	0.00	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.3485545225
93.71	0.14	93.77	0.10	90.60	0.09	91.81	0.56			93.84	0.07	95.28	0.00	96.99	0.00	/workspace/coverage/default/3.chip_sw_all_escalation_resets.3527791789
93.84	0.13	93.77	0.00	90.60	0.00	91.81	0.00			93.84	0.00	95.28	0.00	97.77	0.78	/workspace/coverage/cover_reg_top/68.xbar_access_same_device_slow_rsp.1630225156
93.97	0.13	93.99	0.23	90.79	0.19	91.83	0.02			94.15	0.32	95.28	0.00	97.77	0.00	/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.2168140122
94.09	0.12	94.04	0.05	91.09	0.31	91.86	0.03			94.46	0.31	95.28	0.00	97.77	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1235196643
94.19	0.11	94.04	0.00	91.09	0.00	92.52	0.66			94.46	0.00	95.28	0.00	97.77	0.00	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.3768741533
94.30	0.11	94.11	0.07	91.11	0.02	93.06	0.55			94.47	0.01	95.28	0.00	97.77	0.00	/workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.3586839302
94.40	0.10	94.11	0.00	91.34	0.23	93.06	0.00			94.49	0.02	95.28	0.00	98.11	0.34	/workspace/coverage/cover_reg_top/49.xbar_stress_all.3291665804
94.48	0.08	94.11	0.00	91.82	0.48	93.06	0.00			94.49	0.00	95.28	0.00	98.11	0.00	/workspace/coverage/cover_reg_top/9.chip_tl_errors.247020437
94.55	0.08	94.15	0.04	92.01	0.20	93.07	0.01			94.70	0.21	95.28	0.00	98.11	0.00	/workspace/coverage/default/2.chip_jtag_csr_rw.1396873104
94.62	0.07	94.21	0.07	92.06	0.05	93.18	0.11			94.72	0.02	95.45	0.17	98.11	0.00	/workspace/coverage/default/4.chip_sw_data_integrity_escalation.4170844596
94.69	0.07	94.38	0.17	92.21	0.15	93.18	0.00			94.80	0.08	95.45	0.00	98.11	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_retention.29725494
94.75	0.06	94.45	0.07	92.34	0.13	93.28	0.10			94.86	0.06	95.45	0.00	98.11	0.00	/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.3365036702
94.80	0.05	94.50	0.05	92.40	0.06	93.44	0.16			94.91	0.05	95.45	0.00	98.11	0.00	/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2850284154
94.85	0.05	94.50	0.00	92.55	0.16	93.44	0.00			94.94	0.03	95.45	0.00	98.24	0.13	/workspace/coverage/cover_reg_top/69.xbar_stress_all_with_rand_reset.2990304630
94.90	0.05	94.50	0.00	92.58	0.03	93.53	0.09			94.94	0.00	95.63	0.17	98.24	0.00	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1487290751
94.95	0.05	94.50	0.00	92.58	0.00	93.81	0.27			94.94	0.00	95.63	0.00	98.24	0.00	/workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.1412601368
94.99	0.04	94.50	0.01	92.60	0.01	93.84	0.04			94.95	0.01	95.80	0.17	98.25	0.01	/workspace/coverage/default/24.chip_sw_all_escalation_resets.2857656701
95.03	0.04	94.50	0.00	92.85	0.25	93.84	0.00			94.95	0.00	95.80	0.00	98.25	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_0.1189013651
95.07	0.04	94.50	0.00	92.85	0.00	94.09	0.25			94.95	0.00	95.80	0.00	98.25	0.00	/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.700780624
95.11	0.04	94.50	0.00	92.85	0.00	94.33	0.25			94.95	0.00	95.80	0.00	98.25	0.00	/workspace/coverage/default/2.chip_sw_kmac_entropy.1516758579
95.15	0.04	94.51	0.01	92.86	0.01	94.33	0.00			94.97	0.02	95.98	0.17	98.26	0.01	/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.3160230083
95.19	0.04	94.54	0.03	92.86	0.01	94.34	0.01			94.98	0.01	96.15	0.17	98.27	0.01	/workspace/coverage/default/56.chip_sw_all_escalation_resets.594171910
95.23	0.04	94.54	0.01	92.87	0.01	94.34	0.01			94.99	0.01	96.33	0.17	98.28	0.01	/workspace/coverage/default/1.chip_sw_all_escalation_resets.11441257
95.26	0.04	94.55	0.01	92.89	0.01	94.34	0.00			95.00	0.01	96.50	0.17	98.30	0.01	/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.4203698072
95.29	0.03	94.55	0.00	93.05	0.16	94.34	0.00			95.01	0.02	96.50	0.00	98.31	0.01	/workspace/coverage/cover_reg_top/15.xbar_stress_all.1976332368
95.32	0.03	94.55	0.00	93.05	0.00	94.52	0.17			95.01	0.00	96.50	0.00	98.31	0.00	/workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.2937937753
95.35	0.03	94.55	0.00	93.14	0.09	94.52	0.00			95.09	0.08	96.50	0.00	98.31	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.476013744
95.38	0.03	94.62	0.07	93.14	0.00	94.60	0.08			95.10	0.01	96.50	0.00	98.31	0.00	/workspace/coverage/default/1.chip_tap_straps_rma.1222652276
95.40	0.03	94.62	0.00	93.29	0.15	94.60	0.00			95.10	0.00	96.50	0.00	98.31	0.00	/workspace/coverage/cover_reg_top/2.chip_tl_errors.2267014943
95.43	0.02	94.62	0.00	93.29	0.00	94.74	0.14			95.10	0.00	96.50	0.00	98.31	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.1051125643
95.45	0.02	94.67	0.05	93.35	0.06	94.75	0.02			95.11	0.01	96.50	0.00	98.31	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.1154409977
95.47	0.02	94.67	0.00	93.41	0.06	94.75	0.00			95.13	0.02	96.50	0.00	98.37	0.06	/workspace/coverage/cover_reg_top/41.xbar_stress_all_with_rand_reset.3463812333
95.49	0.02	94.73	0.05	93.46	0.05	94.75	0.00			95.15	0.02	96.50	0.00	98.37	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.1511184325
95.51	0.02	94.76	0.03	93.52	0.06	94.76	0.01			95.18	0.02	96.50	0.00	98.37	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.646455140
95.53	0.02	94.76	0.00	93.53	0.01	94.76	0.00			95.18	0.00	96.50	0.00	98.47	0.11	/workspace/coverage/cover_reg_top/8.xbar_stress_all_with_rand_reset.1180066430
95.55	0.02	94.76	0.00	93.53	0.00	94.87	0.11			95.18	0.00	96.50	0.00	98.47	0.00	/workspace/coverage/default/2.chip_sw_flash_init.4270656048
95.57	0.02	94.76	0.01	93.61	0.07	94.87	0.00			95.20	0.02	96.50	0.00	98.47	0.00	/workspace/coverage/cover_reg_top/7.chip_csr_rw.1258774426
95.59	0.02	94.77	0.01	93.61	0.01	94.95	0.08			95.21	0.01	96.50	0.00	98.47	0.00	/workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.1545801394
95.60	0.01	94.77	0.00	93.61	0.00	95.04	0.08			95.21	0.00	96.50	0.00	98.47	0.00	/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.4042606821
95.61	0.01	94.77	0.00	93.61	0.00	95.04	0.00			95.21	0.00	96.50	0.00	98.55	0.08	/workspace/coverage/cover_reg_top/84.xbar_stress_all_with_reset_error.2032455254
95.63	0.01	94.77	0.00	93.68	0.07	95.04	0.00			95.21	0.00	96.50	0.00	98.55	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_0.4130697781
95.64	0.01	94.77	0.00	93.76	0.07	95.04	0.00			95.21	0.00	96.50	0.00	98.55	0.00	/workspace/coverage/cover_reg_top/27.chip_tl_errors.216603974
95.65	0.01	94.79	0.01	93.78	0.03	95.04	0.01			95.23	0.02	96.50	0.00	98.55	0.00	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.1143664125
95.66	0.01	94.82	0.03	93.81	0.02	95.04	0.00			95.23	0.01	96.50	0.00	98.55	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.2571574610
95.67	0.01	94.85	0.03	93.83	0.02	95.04	0.00			95.24	0.01	96.50	0.00	98.55	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_wake.2306866470
95.68	0.01	94.86	0.01	93.86	0.03	95.07	0.03			95.24	0.00	96.50	0.00	98.55	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.3864348934
95.69	0.01	94.86	0.00	93.86	0.01	95.07	0.00			95.24	0.00	96.50	0.00	98.61	0.06	/workspace/coverage/cover_reg_top/50.xbar_stress_all_with_rand_reset.2360026659
95.70	0.01	94.86	0.00	93.92	0.06	95.07	0.00			95.24	0.00	96.50	0.00	98.61	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_20.3835949351
95.71	0.01	94.88	0.02	93.93	0.01	95.08	0.01			95.26	0.02	96.50	0.00	98.61	0.00	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.1371177402
95.72	0.01	94.91	0.02	93.93	0.01	95.08	0.01			95.27	0.02	96.50	0.00	98.61	0.00	/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.3607929083
95.73	0.01	94.91	0.00	93.94	0.01	95.08	0.00			95.27	0.00	96.50	0.00	98.66	0.05	/workspace/coverage/cover_reg_top/61.xbar_stress_all_with_rand_reset.3306151329
95.74	0.01	94.91	0.00	93.94	0.00	95.14	0.05			95.27	0.00	96.50	0.00	98.66	0.00	/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.2312159085
95.75	0.01	94.93	0.02	93.95	0.01	95.14	0.01			95.29	0.02	96.50	0.00	98.66	0.00	/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.533121725
95.75	0.01	94.93	0.00	93.95	0.00	95.18	0.04			95.29	0.00	96.50	0.00	98.66	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.2363401521
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95.99	0.01	94.96	0.00	94.27	0.00	95.43	0.00			95.30	0.00	96.50	0.00	99.49	0.01	/workspace/coverage/default/71.chip_sw_all_escalation_resets.3881376955
96.00	0.01	94.96	0.00	94.27	0.00	95.43	0.00			95.30	0.00	96.50	0.00	99.51	0.01	/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.446880634
96.00	0.01	94.96	0.00	94.27	0.00	95.43	0.00			95.30	0.00	96.50	0.00	99.52	0.01	/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.793281380
96.00	0.01	94.96	0.00	94.27	0.00	95.43	0.00			95.30	0.00	96.50	0.00	99.53	0.01	/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.1817555789
96.00	0.01	94.96	0.00	94.27	0.00	95.43	0.00			95.30	0.00	96.50	0.00	99.54	0.01	/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.2868897928
96.00	0.01	94.96	0.00	94.27	0.00	95.43	0.00			95.30	0.00	96.50	0.00	99.55	0.01	/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.4280558396
96.01	0.01	94.96	0.00	94.27	0.00	95.43	0.00			95.30	0.00	96.50	0.00	99.57	0.01	/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.3414957386
96.01	0.01	94.96	0.00	94.27	0.00	95.43	0.00			95.30	0.00	96.50	0.00	99.58	0.01	/workspace/coverage/default/9.chip_sw_all_escalation_resets.2578445731
96.01	0.01	94.96	0.00	94.28	0.01	95.43	0.00			95.30	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1856056324
96.01	0.01	94.96	0.00	94.29	0.01	95.43	0.00			95.30	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.876084629
96.01	0.01	94.96	0.00	94.30	0.01	95.44	0.01			95.30	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.862135281
96.01	0.01	94.97	0.01	94.30	0.00	95.45	0.01			95.30	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/default/23.chip_sw_all_escalation_resets.3959634344
96.02	0.01	94.97	0.00	94.30	0.00	95.45	0.01			95.30	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.491136340
96.02	0.01	94.97	0.00	94.30	0.00	95.46	0.01			95.30	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_hmac_enc_idle.2992791558
96.02	0.01	94.97	0.00	94.30	0.00	95.47	0.01			95.30	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.2977894005
96.02	0.01	94.97	0.00	94.30	0.01	95.47	0.00			95.30	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/11.chip_tl_errors.702361316
96.02	0.01	94.97	0.00	94.31	0.01	95.47	0.00			95.30	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/12.xbar_stress_all.2897767293
96.02	0.01	94.97	0.00	94.32	0.01	95.47	0.00			95.30	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/61.xbar_stress_all_with_error.1466060051
96.02	0.01	94.97	0.00	94.32	0.01	95.47	0.00			95.30	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_entropy_src_csrng.1113895113
96.02	0.01	94.97	0.00	94.33	0.01	95.47	0.00			95.30	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.762622579
96.03	0.01	94.97	0.00	94.34	0.01	95.47	0.00			95.30	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/default/1.chip_sw_gpio.2627285285
96.03	0.01	94.97	0.00	94.34	0.01	95.47	0.00			95.30	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/default/2.chip_sw_gpio.4272683807
96.03	0.01	94.97	0.00	94.34	0.00	95.48	0.01			95.30	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1679729334
96.03	0.01	94.97	0.01	94.34	0.00	95.48	0.00			95.30	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_pattgen_ios.1939778900
96.03	0.01	94.98	0.01	94.34	0.00	95.48	0.00			95.30	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/default/1.chip_sw_pattgen_ios.789768730
96.03	0.01	94.98	0.00	94.34	0.00	95.48	0.01			95.30	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.903235604
96.03	0.01	94.98	0.00	94.34	0.00	95.49	0.01			95.30	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1271959140
96.03	0.01	94.98	0.00	94.34	0.00	95.49	0.01			95.30	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/default/1.chip_sw_edn_entropy_reqs.2278270994
96.03	0.01	94.98	0.00	94.34	0.00	95.50	0.01			95.30	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.4119739212
96.03	0.01	94.98	0.00	94.35	0.01	95.50	0.00			95.30	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/11.xbar_stress_all.2489762348
96.03	0.01	94.98	0.00	94.35	0.01	95.50	0.00			95.30	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/14.chip_tl_errors.983099746
96.04	0.01	94.98	0.00	94.36	0.01	95.50	0.00			95.30	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/27.xbar_stress_all_with_error.3513892904
96.04	0.01	94.98	0.00	94.36	0.01	95.50	0.00			95.30	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/30.xbar_stress_all_with_error.4101317666
96.04	0.01	94.98	0.00	94.36	0.01	95.50	0.00			95.30	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/33.xbar_stress_all_with_reset_error.2550944870
96.04	0.01	94.98	0.00	94.37	0.01	95.50	0.00			95.30	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/42.xbar_stress_all_with_error.1171694778
96.04	0.01	94.98	0.00	94.37	0.01	95.50	0.00			95.30	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/65.xbar_stress_all_with_error.954712974
96.04	0.01	94.98	0.00	94.37	0.01	95.50	0.00			95.30	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_10.106567894
96.04	0.01	94.98	0.00	94.38	0.01	95.50	0.00			95.30	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.169170451
96.04	0.01	94.98	0.00	94.38	0.00	95.50	0.01			95.30	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/default/1.chip_tap_straps_testunlock0.3627178125
96.04	0.01	94.98	0.01	94.38	0.00	95.50	0.00			95.30	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.1806482241
96.04	0.01	94.98	0.00	94.38	0.00	95.50	0.01			95.30	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.4244330930
96.04	0.01	94.98	0.00	94.38	0.00	95.51	0.01			95.30	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_aes_enc.2202278874
96.04	0.01	94.98	0.00	94.38	0.00	95.51	0.01			95.30	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_aon_timer_irq.535807177
96.04	0.01	94.98	0.00	94.38	0.00	95.51	0.01			95.30	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.3090811811
96.04	0.01	94.98	0.00	94.38	0.00	95.51	0.01			95.30	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_edn_boot_mode.1943316000
96.04	0.01	94.98	0.00	94.38	0.00	95.52	0.01			95.30	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.3106311458

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.645635006
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.4182690945
/workspace/coverage/cover_reg_top/0.chip_csr_rw.2106456761
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.2873896821
/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.225239955
/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.1504642145
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.1933470915
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.2348819636
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.1479088771
/workspace/coverage/cover_reg_top/0.xbar_error_random.720411559
/workspace/coverage/cover_reg_top/0.xbar_random.3666388696
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.1883309075
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.3036459229
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.2673447243
/workspace/coverage/cover_reg_top/0.xbar_same_source.98743534
/workspace/coverage/cover_reg_top/0.xbar_smoke.1129738446
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.3063697405
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.1707240062
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.432660403
/workspace/coverage/cover_reg_top/0.xbar_stress_all.30878064
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.1293315630
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.1320977803
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.1762598395
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.543255932
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.1804048129
/workspace/coverage/cover_reg_top/1.chip_csr_rw.3237858874
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.898094976
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.2750662472
/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.485872528
/workspace/coverage/cover_reg_top/1.chip_tl_errors.3973283769
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.4009625121
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.2270617706
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.2310963379
/workspace/coverage/cover_reg_top/1.xbar_error_random.3450202816
/workspace/coverage/cover_reg_top/1.xbar_random.3806570691
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.592843013
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.4241130519
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.2089561170
/workspace/coverage/cover_reg_top/1.xbar_same_source.2515824830
/workspace/coverage/cover_reg_top/1.xbar_smoke.1966777632
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.1381023129
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.3920621564
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.4102219844
/workspace/coverage/cover_reg_top/1.xbar_stress_all.2088743706
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.3454566116
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.2890358361
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.1686987294
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.2513484468
/workspace/coverage/cover_reg_top/10.chip_csr_rw.1932055544
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.3051457586
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.1731465709
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.3375289362
/workspace/coverage/cover_reg_top/10.xbar_error_random.2361076604
/workspace/coverage/cover_reg_top/10.xbar_random.1950555250
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.887202195
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.1700350131
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.3325452910
/workspace/coverage/cover_reg_top/10.xbar_same_source.3129615370
/workspace/coverage/cover_reg_top/10.xbar_smoke.4068786876
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.3074053738
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.3270494099
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.1401783760
/workspace/coverage/cover_reg_top/10.xbar_stress_all.1834961774
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.2034428566
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.2384053874
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.2696396637
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.3432220479
/workspace/coverage/cover_reg_top/11.chip_csr_rw.4106634700
/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.116944678
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.2207686198
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.2014796783
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.1040222912
/workspace/coverage/cover_reg_top/11.xbar_error_random.3787400254
/workspace/coverage/cover_reg_top/11.xbar_random.2402221842
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.1520224933
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.2104647700
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.4265708305
/workspace/coverage/cover_reg_top/11.xbar_same_source.4120305852
/workspace/coverage/cover_reg_top/11.xbar_smoke.3337474923
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.4270726534
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.237042419
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.3163691769
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.3496909598
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.1070869876
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.1414574113
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.1032766844
/workspace/coverage/cover_reg_top/12.chip_csr_rw.774856251
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.3800400059
/workspace/coverage/cover_reg_top/12.chip_tl_errors.3210788054
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.629242428
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.87596179
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.237826640
/workspace/coverage/cover_reg_top/12.xbar_error_random.4017563956
/workspace/coverage/cover_reg_top/12.xbar_random.2818886195
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.2143271007
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.2508278392
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.2815325513
/workspace/coverage/cover_reg_top/12.xbar_same_source.443283999
/workspace/coverage/cover_reg_top/12.xbar_smoke.3517405800
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.3235199680
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.3525978585
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.292154093
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.2336183516
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.4278712006
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.2586209765
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.1159882469
/workspace/coverage/cover_reg_top/13.chip_csr_rw.859858219
/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.1580007135
/workspace/coverage/cover_reg_top/13.chip_tl_errors.790300054
/workspace/coverage/cover_reg_top/13.xbar_access_same_device.4081895368
/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.915664136
/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.470482071
/workspace/coverage/cover_reg_top/13.xbar_error_random.1064701792
/workspace/coverage/cover_reg_top/13.xbar_random.612683944
/workspace/coverage/cover_reg_top/13.xbar_random_large_delays.1029618735
/workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.2759178278
/workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.3221212444
/workspace/coverage/cover_reg_top/13.xbar_same_source.1210857390
/workspace/coverage/cover_reg_top/13.xbar_smoke.1638047884
/workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.4095072797
/workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.2863022404
/workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.2216276706
/workspace/coverage/cover_reg_top/13.xbar_stress_all.130895264
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.3064543871
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.1997338543
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.3769133073
/workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.2338600029
/workspace/coverage/cover_reg_top/14.chip_csr_rw.2494509008
/workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.2882424739
/workspace/coverage/cover_reg_top/14.xbar_access_same_device.3614609841
/workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.1065315043
/workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.739537917
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/workspace/coverage/default/31.chip_sw_all_escalation_resets.4073281017
/workspace/coverage/default/33.chip_sw_all_escalation_resets.449966064
/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.3926125560
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/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.3234231071
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/workspace/coverage/default/37.chip_sw_all_escalation_resets.4264299679
/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.1498269827
/workspace/coverage/default/4.chip_sw_all_escalation_resets.3359062827
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.2911847588
/workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.3249376089
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.2920019496
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.2121146525
/workspace/coverage/default/4.chip_sw_uart_tx_rx.2619241032
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.4169118404
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/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.2003134786
/workspace/coverage/default/47.chip_sw_all_escalation_resets.2171527125
/workspace/coverage/default/48.chip_sw_all_escalation_resets.2405595339
/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.118168097
/workspace/coverage/default/49.chip_sw_all_escalation_resets.4123931658
/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.2394171825
/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.1694046912
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.965057168
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.522218117
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.2033805935
/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.1573056527
/workspace/coverage/default/50.chip_sw_all_escalation_resets.3701781586
/workspace/coverage/default/51.chip_sw_all_escalation_resets.1335607681
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.289435210
/workspace/coverage/default/53.chip_sw_all_escalation_resets.2713127627
/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.1969176013
/workspace/coverage/default/54.chip_sw_all_escalation_resets.4162523593
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.3763306812
/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.2472153445
/workspace/coverage/default/57.chip_sw_all_escalation_resets.1554648331
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.2879292842
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.1935232806
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.627715166
/workspace/coverage/default/6.chip_sw_all_escalation_resets.1905446006
/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.260161271
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.1943915753
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.2343072930
/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.1688793627
/workspace/coverage/default/60.chip_sw_all_escalation_resets.1908387921
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.4077856300
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.2344909956
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.78759527
/workspace/coverage/default/64.chip_sw_all_escalation_resets.2757032842
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.1278270783
/workspace/coverage/default/65.chip_sw_all_escalation_resets.2778484999
/workspace/coverage/default/66.chip_sw_all_escalation_resets.4191121714
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.133507767
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.1531397496
/workspace/coverage/default/69.chip_sw_all_escalation_resets.4195840523
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.1115583381
/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.3791805169
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.309576589
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.3727802378
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.3386945158
/workspace/coverage/default/70.chip_sw_all_escalation_resets.802552954
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.1436865057
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.2503077085
/workspace/coverage/default/73.chip_sw_all_escalation_resets.168091671
/workspace/coverage/default/74.chip_sw_all_escalation_resets.447260656
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.2894019064
/workspace/coverage/default/75.chip_sw_all_escalation_resets.1620831390
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.2596638519
/workspace/coverage/default/76.chip_sw_all_escalation_resets.1795222279
/workspace/coverage/default/77.chip_sw_all_escalation_resets.2546669080
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.3879369151
/workspace/coverage/default/78.chip_sw_all_escalation_resets.1236962791
/workspace/coverage/default/79.chip_sw_all_escalation_resets.1477875588
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.1294596023
/workspace/coverage/default/8.chip_sw_all_escalation_resets.16694476
/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.2973766170
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.2745489876
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.2802631271
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.207289854
/workspace/coverage/default/80.chip_sw_all_escalation_resets.2833934548
/workspace/coverage/default/81.chip_sw_all_escalation_resets.3100691800
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.2830497868
/workspace/coverage/default/82.chip_sw_all_escalation_resets.3344022435
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.1136748820
/workspace/coverage/default/83.chip_sw_all_escalation_resets.1692923504
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.2151569594
/workspace/coverage/default/84.chip_sw_all_escalation_resets.3372663187
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.1651611181
/workspace/coverage/default/85.chip_sw_all_escalation_resets.3306210295
/workspace/coverage/default/86.chip_sw_all_escalation_resets.2437260928
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.260389457
/workspace/coverage/default/87.chip_sw_all_escalation_resets.646349275
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.1446192071
/workspace/coverage/default/88.chip_sw_all_escalation_resets.3983015006
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.4144013496
/workspace/coverage/default/89.chip_sw_all_escalation_resets.920041640
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.1804971740
/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.3620986090
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.4180409132
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.811354858
/workspace/coverage/default/90.chip_sw_all_escalation_resets.1120847974
/workspace/coverage/default/91.chip_sw_all_escalation_resets.3347656023
/workspace/coverage/default/92.chip_sw_all_escalation_resets.2071937415
/workspace/coverage/default/93.chip_sw_all_escalation_resets.3410661463
/workspace/coverage/default/94.chip_sw_all_escalation_resets.3932240959
/workspace/coverage/default/95.chip_sw_all_escalation_resets.998342975
/workspace/coverage/default/96.chip_sw_all_escalation_resets.651336699
/workspace/coverage/default/97.chip_sw_all_escalation_resets.3168478625
/workspace/coverage/default/98.chip_sw_all_escalation_resets.3988578182
/workspace/coverage/default/99.chip_sw_all_escalation_resets.2508292432
/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.2819108315
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.1341210892
/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.3431310560
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.3465449281
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.3573255103
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.3671563782
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.704438347
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.3542712953

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Total test records in report: 2874

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T4	/workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.1734961486			May 30 04:09:55 PM PDT 24	May 30 04:18:05 PM PDT 24	4163199622 ps
T5	/workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.3176673966			May 30 04:29:20 PM PDT 24	May 30 04:35:10 PM PDT 24	3807101140 ps
T6	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.4025569188			May 30 04:20:29 PM PDT 24	May 30 04:58:12 PM PDT 24	24297064426 ps
T43	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1271959140			May 30 04:12:21 PM PDT 24	May 30 04:21:52 PM PDT 24	6598739576 ps
T17	/workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.1548404301			May 30 04:26:26 PM PDT 24	May 30 04:48:43 PM PDT 24	9104138640 ps
T84	/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.2868897928			May 30 04:42:46 PM PDT 24	May 30 04:50:16 PM PDT 24	3811249820 ps
T50	/workspace/coverage/default/1.chip_sw_spi_device_tpm.1725304865			May 30 04:16:45 PM PDT 24	May 30 04:22:07 PM PDT 24	2579712806 ps
T61	/workspace/coverage/default/72.chip_sw_all_escalation_resets.3697151083			May 30 04:41:34 PM PDT 24	May 30 04:52:28 PM PDT 24	5684026320 ps
T31	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.3485545225			May 30 04:28:07 PM PDT 24	May 30 04:54:00 PM PDT 24	21589579336 ps
T85	/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.3028648427			May 30 04:35:46 PM PDT 24	May 30 04:42:09 PM PDT 24	3550608972 ps
T194	/workspace/coverage/default/1.chip_sw_rv_timer_smoketest.133672008			May 30 04:22:34 PM PDT 24	May 30 04:26:12 PM PDT 24	2545412792 ps
T103	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.1572384368			May 30 04:11:23 PM PDT 24	May 30 04:46:02 PM PDT 24	9267347307 ps
T181	/workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.3698740085			May 30 04:26:41 PM PDT 24	May 30 04:39:13 PM PDT 24	6448757692 ps
T18	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.2721688570			May 30 04:22:48 PM PDT 24	May 30 05:16:51 PM PDT 24	13694827084 ps
T105	/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.254699985			May 30 04:31:19 PM PDT 24	May 30 04:35:47 PM PDT 24	2895072901 ps
T1	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.4060958121			May 30 04:20:23 PM PDT 24	May 30 04:47:14 PM PDT 24	18848866992 ps
T98	/workspace/coverage/default/1.chip_sw_plic_sw_irq.3867289078			May 30 04:19:34 PM PDT 24	May 30 04:24:00 PM PDT 24	2479758876 ps
T80	/workspace/coverage/default/24.chip_sw_all_escalation_resets.2857656701			May 30 04:37:32 PM PDT 24	May 30 04:46:34 PM PDT 24	4984438448 ps
T91	/workspace/coverage/default/2.chip_sw_otbn_mem_scramble.682982298			May 30 04:26:54 PM PDT 24	May 30 04:34:02 PM PDT 24	3018644200 ps
T58	/workspace/coverage/default/0.chip_sw_alert_test.2595960547			May 30 04:11:55 PM PDT 24	May 30 04:18:08 PM PDT 24	3214120648 ps
T92	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.1151013261			May 30 04:10:47 PM PDT 24	May 30 04:19:50 PM PDT 24	6551286892 ps
T93	/workspace/coverage/default/1.chip_sw_power_sleep_load.3832144845			May 30 04:21:44 PM PDT 24	May 30 04:30:14 PM PDT 24	10646650104 ps
T19	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.1435683895			May 30 04:19:16 PM PDT 24	May 30 05:22:17 PM PDT 24	13443633732 ps
T94	/workspace/coverage/default/3.chip_sw_uart_tx_rx.1542563806			May 30 04:35:39 PM PDT 24	May 30 04:46:28 PM PDT 24	4439756588 ps
T95	/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.2151569594			May 30 04:42:03 PM PDT 24	May 30 04:48:27 PM PDT 24	3883693358 ps
T20	/workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.3586839302			May 30 04:23:56 PM PDT 24	May 30 07:07:52 PM PDT 24	58225587792 ps
T96	/workspace/coverage/default/0.chip_sw_hmac_enc_idle.2992791558			May 30 04:18:50 PM PDT 24	May 30 04:25:15 PM PDT 24	3126371160 ps
T286	/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.4257958456			May 30 04:38:02 PM PDT 24	May 30 04:44:29 PM PDT 24	3188550748 ps
T57	/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2344005037			May 30 04:16:00 PM PDT 24	May 30 04:17:52 PM PDT 24	1893309291 ps
T21	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.3303016173			May 30 04:25:29 PM PDT 24	May 30 04:30:28 PM PDT 24	2463234726 ps
T106	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.1532572425			May 30 04:28:31 PM PDT 24	May 30 04:33:58 PM PDT 24	2912158804 ps
T248	/workspace/coverage/default/4.chip_sw_data_integrity_escalation.4170844596			May 30 04:33:34 PM PDT 24	May 30 04:46:06 PM PDT 24	5457590670 ps
T223	/workspace/coverage/default/34.chip_sw_all_escalation_resets.1146478672			May 30 04:36:22 PM PDT 24	May 30 04:48:04 PM PDT 24	6004276488 ps
T277	/workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.3570538491			May 30 04:16:41 PM PDT 24	May 30 04:24:26 PM PDT 24	3634886732 ps
T203	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.1237421444			May 30 04:16:32 PM PDT 24	May 30 04:28:10 PM PDT 24	4625771930 ps
T54	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.3022902981			May 30 04:17:33 PM PDT 24	May 30 05:20:14 PM PDT 24	14414020244 ps
T278	/workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.1340027978			May 30 04:20:20 PM PDT 24	May 30 04:27:13 PM PDT 24	3691397064 ps
T55	/workspace/coverage/default/0.chip_sw_lc_ctrl_transition.379758170			May 30 04:09:49 PM PDT 24	May 30 04:18:55 PM PDT 24	6592419753 ps
T279	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1998792840			May 30 04:13:15 PM PDT 24	May 30 04:25:32 PM PDT 24	5231794121 ps
T47	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.985323300			May 30 04:13:15 PM PDT 24	May 30 04:20:29 PM PDT 24	4597974832 ps
T280	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.862135281			May 30 04:13:00 PM PDT 24	May 30 04:27:53 PM PDT 24	5234560074 ps
T393	/workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.1063646326			May 30 04:27:24 PM PDT 24	May 30 04:46:14 PM PDT 24	5772258125 ps
T116	/workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.3154550050			May 30 04:17:17 PM PDT 24	May 30 04:32:17 PM PDT 24	5572427992 ps
T158	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2460661159			May 30 04:15:28 PM PDT 24	May 30 04:26:45 PM PDT 24	4380546930 ps
T519	/workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.200587390			May 30 04:17:04 PM PDT 24	May 30 04:53:43 PM PDT 24	13210346833 ps
T670	/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.703040679			May 30 04:38:27 PM PDT 24	May 30 04:45:12 PM PDT 24	3401095110 ps
T218	/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.811354858			May 30 04:34:01 PM PDT 24	May 30 04:58:08 PM PDT 24	8496691200 ps
T674	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.3249375268			May 30 04:11:21 PM PDT 24	May 30 04:16:27 PM PDT 24	3098771000 ps
T101	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.1127816375			May 30 04:12:44 PM PDT 24	May 30 05:26:22 PM PDT 24	30079727007 ps
T56	/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.4180409132			May 30 04:33:42 PM PDT 24	May 30 04:41:31 PM PDT 24	5864136219 ps
T27	/workspace/coverage/default/1.chip_sw_gpio_smoketest.1729523393			May 30 04:22:44 PM PDT 24	May 30 04:28:41 PM PDT 24	3409937456 ps
T215	/workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.1468050149			May 30 04:15:02 PM PDT 24	May 30 04:39:43 PM PDT 24	9249057064 ps
T252	/workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.3106311458			May 30 04:21:55 PM PDT 24	May 30 04:26:12 PM PDT 24	2757195760 ps
T227	/workspace/coverage/default/89.chip_sw_all_escalation_resets.920041640			May 30 04:42:58 PM PDT 24	May 30 04:53:23 PM PDT 24	4111598048 ps
T109	/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2850284154			May 30 04:33:13 PM PDT 24	May 30 04:43:30 PM PDT 24	4777584008 ps
T24	/workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.285696106			May 30 04:15:34 PM PDT 24	May 30 04:24:24 PM PDT 24	3907059251 ps
T110	/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.4169118404			May 30 04:34:25 PM PDT 24	May 30 04:58:43 PM PDT 24	8020041574 ps
T226	/workspace/coverage/default/1.rom_e2e_asm_init_dev.3781875479			May 30 04:28:43 PM PDT 24	May 30 05:26:11 PM PDT 24	15055537762 ps
T348	/workspace/coverage/default/51.chip_sw_all_escalation_resets.1335607681			May 30 04:41:16 PM PDT 24	May 30 04:49:34 PM PDT 24	4813404724 ps
T383	/workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.2342217697			May 30 04:28:20 PM PDT 24	May 30 04:36:25 PM PDT 24	4637604120 ps
T108	/workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.442172792			May 30 04:28:39 PM PDT 24	May 30 05:52:11 PM PDT 24	46705541102 ps
T856	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.1798072574			May 30 04:16:00 PM PDT 24	May 30 04:25:13 PM PDT 24	6714856341 ps
T123	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.1371177402			May 30 04:10:34 PM PDT 24	May 30 04:21:04 PM PDT 24	5782239360 ps
T225	/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.3248252172			May 30 04:27:46 PM PDT 24	May 30 05:23:15 PM PDT 24	15501678136 ps
T2	/workspace/coverage/default/2.chip_sw_sleep_pin_retention.957607366			May 30 04:27:24 PM PDT 24	May 30 04:34:40 PM PDT 24	4399709160 ps
T396	/workspace/coverage/default/2.chip_sw_hmac_smoketest.3235977903			May 30 04:32:30 PM PDT 24	May 30 04:36:57 PM PDT 24	3170371488 ps
T397	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2445862661			May 30 04:15:28 PM PDT 24	May 30 04:38:32 PM PDT 24	16663158149 ps
T398	/workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.2833618432			May 30 04:09:26 PM PDT 24	May 30 04:13:29 PM PDT 24	3420995106 ps
T311	/workspace/coverage/default/39.chip_sw_all_escalation_resets.2408185079			May 30 04:37:29 PM PDT 24	May 30 04:49:33 PM PDT 24	4892179074 ps
T316	/workspace/coverage/default/1.chip_sw_otbn_randomness.340979656			May 30 04:18:06 PM PDT 24	May 30 04:34:54 PM PDT 24	5122059664 ps
T157	/workspace/coverage/default/3.chip_sw_all_escalation_resets.3527791789			May 30 04:31:58 PM PDT 24	May 30 04:43:45 PM PDT 24	5495474072 ps
T99	/workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3927787384			May 30 04:17:41 PM PDT 24	May 30 04:27:34 PM PDT 24	19074667732 ps
T151	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.762622579			May 30 04:11:28 PM PDT 24	May 30 04:35:36 PM PDT 24	11825691360 ps
T317	/workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.3753135248			May 30 04:10:38 PM PDT 24	May 30 04:17:47 PM PDT 24	3428219814 ps
T318	/workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.504576008			May 30 04:26:50 PM PDT 24	May 30 04:29:47 PM PDT 24	2070120632 ps
T53	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.2477891953			May 30 04:18:45 PM PDT 24	May 30 05:47:58 PM PDT 24	21730191258 ps
T152	/workspace/coverage/default/40.chip_sw_all_escalation_resets.670476672			May 30 04:38:01 PM PDT 24	May 30 04:50:25 PM PDT 24	5735930712 ps
T258	/workspace/coverage/default/1.chip_sw_rv_timer_irq.3337382334			May 30 04:16:57 PM PDT 24	May 30 04:21:52 PM PDT 24	2878957000 ps
T163	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.3254133138			May 30 04:14:19 PM PDT 24	May 30 04:40:49 PM PDT 24	9347235200 ps
T651	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.3275573640			May 30 04:19:13 PM PDT 24	May 30 05:24:22 PM PDT 24	14227526688 ps
T167	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.3170152037			May 30 04:28:41 PM PDT 24	May 30 04:49:27 PM PDT 24	11640188113 ps
T332	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.3945091280			May 30 04:25:01 PM PDT 24	May 30 04:37:04 PM PDT 24	4217722423 ps
T224	/workspace/coverage/default/45.chip_sw_all_escalation_resets.4013848968			May 30 04:37:35 PM PDT 24	May 30 04:47:16 PM PDT 24	6112739800 ps
T437	/workspace/coverage/default/1.chip_sw_flash_ctrl_access.2385659637			May 30 04:18:19 PM PDT 24	May 30 04:36:50 PM PDT 24	5276208110 ps
T335	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.3652636565			May 30 04:32:53 PM PDT 24	May 30 04:42:26 PM PDT 24	4426706292 ps
T683	/workspace/coverage/default/2.chip_sw_power_sleep_load.2816570229			May 30 04:30:41 PM PDT 24	May 30 04:41:28 PM PDT 24	11106370000 ps
T111	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.4288510829			May 30 04:12:02 PM PDT 24	May 30 04:24:17 PM PDT 24	4108449950 ps
T857	/workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.3814918999			May 30 04:20:04 PM PDT 24	May 30 04:26:57 PM PDT 24	4756451880 ps
T3	/workspace/coverage/default/0.chip_sw_sleep_pin_retention.29725494			May 30 04:09:06 PM PDT 24	May 30 04:16:06 PM PDT 24	4351348768 ps
T228	/workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.3303783661			May 30 04:19:08 PM PDT 24	May 30 05:02:46 PM PDT 24	12141236664 ps
T657	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.2843912497			May 30 04:18:30 PM PDT 24	May 30 05:19:54 PM PDT 24	14096620208 ps
T249	/workspace/coverage/default/0.chip_sw_otbn_mem_scramble.3564652775			May 30 04:11:50 PM PDT 24	May 30 04:18:23 PM PDT 24	3462139146 ps
T208	/workspace/coverage/default/14.chip_sw_uart_rand_baudrate.3419128925			May 30 04:35:41 PM PDT 24	May 30 04:44:19 PM PDT 24	4045569176 ps
T178	/workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.3090811811			May 30 04:18:01 PM PDT 24	May 30 04:24:11 PM PDT 24	3433018540 ps
T229	/workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.2053098234			May 30 04:27:41 PM PDT 24	May 30 05:16:12 PM PDT 24	12759326050 ps
T858	/workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.676250702			May 30 04:10:03 PM PDT 24	May 30 04:15:19 PM PDT 24	4299392846 ps
T32	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.2340446331			May 30 04:11:40 PM PDT 24	May 30 04:47:28 PM PDT 24	22270848250 ps
T159	/workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.1752786514			May 30 04:19:39 PM PDT 24	May 30 05:43:50 PM PDT 24	47036218453 ps
T264	/workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.2526831692			May 30 04:13:22 PM PDT 24	May 30 04:33:47 PM PDT 24	5971619158 ps
T520	/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.1410417460			May 30 04:19:27 PM PDT 24	May 30 04:33:18 PM PDT 24	8276949880 ps
T230	/workspace/coverage/default/79.chip_sw_all_escalation_resets.1477875588			May 30 04:42:43 PM PDT 24	May 30 04:51:55 PM PDT 24	4715084500 ps
T682	/workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.1126409687			May 30 04:11:52 PM PDT 24	May 30 04:21:59 PM PDT 24	5428592936 ps
T381	/workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.1896655089			May 30 04:30:13 PM PDT 24	May 30 04:34:34 PM PDT 24	2950931166 ps
T438	/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.129422011			May 30 04:09:53 PM PDT 24	May 30 04:26:44 PM PDT 24	5795019662 ps
T364	/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.3160230083			May 30 04:37:33 PM PDT 24	May 30 04:46:32 PM PDT 24	3398452248 ps
T112	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1743248984			May 30 04:21:12 PM PDT 24	May 30 04:32:22 PM PDT 24	3908645832 ps
T150	/workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1825690998			May 30 04:16:50 PM PDT 24	May 30 07:23:30 PM PDT 24	254899740338 ps
T372	/workspace/coverage/default/2.chip_sw_kmac_mode_cshake.3746504762			May 30 04:28:21 PM PDT 24	May 30 04:31:36 PM PDT 24	2436243400 ps
T373	/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3605393053			May 30 04:24:07 PM PDT 24	May 30 04:29:37 PM PDT 24	3649693352 ps
T328	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.623198561			May 30 04:33:08 PM PDT 24	May 30 04:43:22 PM PDT 24	4253324712 ps
T104	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.4013895997			May 30 04:11:44 PM PDT 24	May 30 04:30:56 PM PDT 24	8069129683 ps
T374	/workspace/coverage/default/0.chip_sw_ast_clk_outputs.2396916606			May 30 04:11:31 PM PDT 24	May 30 04:30:30 PM PDT 24	7954009832 ps
T270	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.574941143			May 30 04:19:10 PM PDT 24	May 30 05:15:00 PM PDT 24	13189969621 ps
T375	/workspace/coverage/default/0.chip_sw_hmac_smoketest.3042521317			May 30 04:14:27 PM PDT 24	May 30 04:19:39 PM PDT 24	2635346720 ps
T10	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.2571574610			May 30 04:11:13 PM PDT 24	May 30 04:17:17 PM PDT 24	3247107070 ps
T414	/workspace/coverage/default/0.chip_sw_edn_sw_mode.2105369996			May 30 04:18:47 PM PDT 24	May 30 04:57:45 PM PDT 24	10542291096 ps
T329	/workspace/coverage/default/13.chip_sw_uart_rand_baudrate.1810756692			May 30 04:34:58 PM PDT 24	May 30 05:15:59 PM PDT 24	12956044740 ps
T274	/workspace/coverage/default/5.chip_sw_data_integrity_escalation.965057168			May 30 04:32:58 PM PDT 24	May 30 04:47:36 PM PDT 24	6150579410 ps
T145	/workspace/coverage/default/1.chip_plic_all_irqs_10.1359490297			May 30 04:17:24 PM PDT 24	May 30 04:24:33 PM PDT 24	3741957496 ps
T262	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.2167823714			May 30 04:12:05 PM PDT 24	May 30 06:28:22 PM PDT 24	38380297208 ps
T62	/workspace/coverage/default/4.chip_tap_straps_rma.2646686232			May 30 04:31:52 PM PDT 24	May 30 04:45:55 PM PDT 24	9695809102 ps
T271	/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.4228633186			May 30 04:09:34 PM PDT 24	May 30 04:11:11 PM PDT 24	2461799162 ps
T415	/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.285375492			May 30 04:41:29 PM PDT 24	May 30 04:47:01 PM PDT 24	3104207870 ps
T416	/workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.1655524572			May 30 04:24:23 PM PDT 24	May 30 04:30:01 PM PDT 24	3024900056 ps
T154	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.4119739212			May 30 04:25:53 PM PDT 24	May 30 04:28:01 PM PDT 24	2141965154 ps
T272	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.830454555			May 30 04:19:17 PM PDT 24	May 30 05:30:53 PM PDT 24	13413498296 ps
T859	/workspace/coverage/default/2.chip_sw_aon_timer_smoketest.1918951195			May 30 04:31:49 PM PDT 24	May 30 04:37:05 PM PDT 24	2928000710 ps
T428	/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.4117688525			May 30 04:37:20 PM PDT 24	May 30 04:43:26 PM PDT 24	3782214444 ps
T860	/workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.1807811875			May 30 04:20:01 PM PDT 24	May 30 04:36:19 PM PDT 24	6482889104 ps
T231	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.516671634			May 30 04:27:59 PM PDT 24	May 30 05:01:03 PM PDT 24	9816697134 ps
T861	/workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.2337083770			May 30 04:24:24 PM PDT 24	May 30 04:32:27 PM PDT 24	3817294088 ps
T862	/workspace/coverage/default/2.chip_sw_ast_clk_outputs.3831253883			May 30 04:33:06 PM PDT 24	May 30 04:48:32 PM PDT 24	7122218608 ps
T263	/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.1694046912			May 30 04:35:14 PM PDT 24	May 30 05:32:46 PM PDT 24	14565677438 ps
T322	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.3990368817			May 30 04:11:52 PM PDT 24	May 30 04:34:09 PM PDT 24	6241466770 ps
T219	/workspace/coverage/default/3.chip_tap_straps_prod.3978497717			May 30 04:32:49 PM PDT 24	May 30 04:34:53 PM PDT 24	2602720501 ps
T863	/workspace/coverage/default/1.chip_sw_aon_timer_smoketest.4257826455			May 30 04:22:58 PM PDT 24	May 30 04:28:27 PM PDT 24	2707735400 ps
T117	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.3577554198			May 30 04:19:57 PM PDT 24	May 30 04:29:39 PM PDT 24	5472994858 ps
T214	/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.2822128432			May 30 04:26:19 PM PDT 24	May 30 04:40:52 PM PDT 24	4684318120 ps
T690	/workspace/coverage/default/26.chip_sw_all_escalation_resets.3813922942			May 30 04:36:04 PM PDT 24	May 30 04:48:23 PM PDT 24	4563325360 ps
T864	/workspace/coverage/default/1.chip_sw_aon_timer_irq.889941612			May 30 04:18:03 PM PDT 24	May 30 04:24:24 PM PDT 24	4116175912 ps
T378	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.1154409977			May 30 04:21:42 PM PDT 24	May 30 05:57:34 PM PDT 24	17656059500 ps
T347	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.4200245383			May 30 04:31:53 PM PDT 24	May 30 04:41:33 PM PDT 24	3870931090 ps
T865	/workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.4280583367			May 30 04:11:00 PM PDT 24	May 30 04:18:58 PM PDT 24	6592783900 ps
T334	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops.415396433			May 30 04:16:15 PM PDT 24	May 30 04:27:28 PM PDT 24	3960250240 ps
T25	/workspace/coverage/default/0.chip_sw_spi_device_pass_through.789101508			May 30 04:10:13 PM PDT 24	May 30 04:24:12 PM PDT 24	7128513048 ps
T65	/workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.3438907290			May 30 04:30:04 PM PDT 24	May 30 04:40:46 PM PDT 24	5741711390 ps
T672	/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.1608934383			May 30 04:38:18 PM PDT 24	May 30 04:43:29 PM PDT 24	4147862520 ps
T174	/workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.3563012842			May 30 04:19:54 PM PDT 24	May 30 04:35:56 PM PDT 24	9972392588 ps
T168	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.195070017			May 30 04:13:41 PM PDT 24	May 30 04:26:17 PM PDT 24	12872238465 ps
T164	/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.1247453378			May 30 04:25:25 PM PDT 24	May 30 05:36:43 PM PDT 24	43495762492 ps
T306	/workspace/coverage/default/1.chip_sw_uart_smoketest.929500852			May 30 04:23:53 PM PDT 24	May 30 04:29:20 PM PDT 24	2717524368 ps
T307	/workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.888827912			May 30 04:12:57 PM PDT 24	May 30 04:22:14 PM PDT 24	4474509812 ps
T308	/workspace/coverage/default/2.rom_e2e_smoke.1658375147			May 30 04:33:43 PM PDT 24	May 30 05:28:24 PM PDT 24	14220427000 ps
T309	/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.1374858192			May 30 04:22:01 PM PDT 24	May 30 04:27:16 PM PDT 24	2707103296 ps
T66	/workspace/coverage/default/0.chip_tap_straps_testunlock0.1107589275			May 30 04:10:16 PM PDT 24	May 30 04:21:24 PM PDT 24	6644572720 ps
T28	/workspace/coverage/default/0.chip_sw_usbdev_pullup.1361618295			May 30 04:11:51 PM PDT 24	May 30 04:17:53 PM PDT 24	3202456852 ps
T310	/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.1115583381			May 30 04:33:22 PM PDT 24	May 30 04:41:17 PM PDT 24	3385716206 ps
T866	/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.1863104315			May 30 04:28:06 PM PDT 24	May 30 04:33:10 PM PDT 24	2357462778 ps
T867	/workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.2831990311			May 30 04:17:43 PM PDT 24	May 30 04:27:10 PM PDT 24	5389827288 ps
T868	/workspace/coverage/default/0.chip_sw_aes_enc.2202278874			May 30 04:11:05 PM PDT 24	May 30 04:16:46 PM PDT 24	3832652100 ps
T352	/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.3933536175			May 30 04:23:44 PM PDT 24	May 30 04:28:47 PM PDT 24	2496830629 ps
T869	/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.2047014235			May 30 04:31:03 PM PDT 24	May 30 04:35:47 PM PDT 24	3242647823 ps
T695	/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.133507767			May 30 04:42:35 PM PDT 24	May 30 04:48:57 PM PDT 24	3473610940 ps
T673	/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.3214675965			May 30 04:40:47 PM PDT 24	May 30 04:46:59 PM PDT 24	4159992716 ps
T354	/workspace/coverage/default/74.chip_sw_all_escalation_resets.447260656			May 30 04:41:51 PM PDT 24	May 30 04:51:19 PM PDT 24	5922714846 ps
T870	/workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.2280024731			May 30 04:31:42 PM PDT 24	May 30 04:36:07 PM PDT 24	2612716493 ps
T204	/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.2058060232			May 30 04:37:23 PM PDT 24	May 30 04:42:31 PM PDT 24	3416409172 ps
T216	/workspace/coverage/default/0.chip_sw_inject_scramble_seed.3956316870			May 30 04:10:46 PM PDT 24	May 30 07:29:37 PM PDT 24	65505072356 ps
T26	/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.398721076			May 30 04:25:05 PM PDT 24	May 30 04:33:54 PM PDT 24	4668957298 ps
T121	/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.3607929083			May 30 04:20:01 PM PDT 24	May 30 04:33:47 PM PDT 24	4955171112 ps
T351	/workspace/coverage/default/13.chip_sw_all_escalation_resets.606682589			May 30 04:35:02 PM PDT 24	May 30 04:44:09 PM PDT 24	5932492014 ps
T265	/workspace/coverage/default/23.chip_sw_all_escalation_resets.3959634344			May 30 04:35:27 PM PDT 24	May 30 04:45:57 PM PDT 24	5504194080 ps
T44	/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.3285918314			May 30 04:17:16 PM PDT 24	May 30 04:21:56 PM PDT 24	2130580060 ps
T871	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.270153715			May 30 04:18:33 PM PDT 24	May 30 05:03:38 PM PDT 24	10831590128 ps
T160	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.2121200143			May 30 04:18:00 PM PDT 24	May 30 05:03:37 PM PDT 24	10365557869 ps
T872	/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.1813139202			May 30 04:15:59 PM PDT 24	May 30 04:34:40 PM PDT 24	5219446411 ps
T363	/workspace/coverage/default/0.chip_tap_straps_dev.34468406			May 30 04:19:49 PM PDT 24	May 30 04:23:59 PM PDT 24	3255114139 ps
T873	/workspace/coverage/default/0.chip_sw_aon_timer_smoketest.2426735416			May 30 04:14:40 PM PDT 24	May 30 04:19:34 PM PDT 24	3342263640 ps
T165	/workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.792466464			May 30 04:20:38 PM PDT 24	May 30 04:56:04 PM PDT 24	20177848027 ps
T235	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.1902166596			May 30 04:16:26 PM PDT 24	May 30 04:42:01 PM PDT 24	9493881988 ps
T874	/workspace/coverage/default/12.chip_sw_uart_rand_baudrate.206666945			May 30 04:34:31 PM PDT 24	May 30 04:58:37 PM PDT 24	8105865912 ps
T648	/workspace/coverage/default/43.chip_sw_all_escalation_resets.3353671319			May 30 04:37:33 PM PDT 24	May 30 04:46:46 PM PDT 24	5051036024 ps
T440	/workspace/coverage/default/2.chip_sw_kmac_entropy.1516758579			May 30 04:25:20 PM PDT 24	May 30 04:31:17 PM PDT 24	2950587898 ps
T698	/workspace/coverage/default/25.chip_sw_all_escalation_resets.230527762			May 30 04:36:14 PM PDT 24	May 30 04:48:22 PM PDT 24	4814730800 ps
T875	/workspace/coverage/default/0.chip_sw_rstmgr_smoketest.4040957269			May 30 04:15:29 PM PDT 24	May 30 04:19:43 PM PDT 24	3428831630 ps
T133	/workspace/coverage/default/2.chip_sw_sensor_ctrl_status.2728655871			May 30 04:29:29 PM PDT 24	May 30 04:33:44 PM PDT 24	3179495257 ps
T876	/workspace/coverage/default/1.chip_sw_entropy_src_kat_test.1977222118			May 30 04:19:21 PM PDT 24	May 30 04:22:42 PM PDT 24	2384424616 ps
T379	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.4013526314			May 30 04:21:49 PM PDT 24	May 30 06:20:13 PM PDT 24	23347458648 ps
T877	/workspace/coverage/default/0.chip_sw_alert_handler_escalation.3197319736			May 30 04:11:27 PM PDT 24	May 30 04:19:14 PM PDT 24	4194114280 ps
T273	/workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.4123915547			May 30 04:10:48 PM PDT 24	May 30 04:18:55 PM PDT 24	8712388375 ps
T643	/workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.2613248799			May 30 04:13:47 PM PDT 24	May 30 04:18:32 PM PDT 24	2642268836 ps
T184	/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.3365036702			May 30 04:09:04 PM PDT 24	May 30 04:17:27 PM PDT 24	4180825479 ps
T878	/workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.4289705284			May 30 04:26:02 PM PDT 24	May 30 04:34:33 PM PDT 24	5223829400 ps
T361	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.169170451			May 30 04:09:06 PM PDT 24	May 30 04:19:56 PM PDT 24	3856563910 ps
T166	/workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.2576543322			May 30 04:25:43 PM PDT 24	May 30 05:03:36 PM PDT 24	24685518160 ps
T879	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2324052354			May 30 04:11:15 PM PDT 24	May 30 05:04:13 PM PDT 24	31689118164 ps
T445	/workspace/coverage/default/0.chip_sw_aes_masking_off.2095073197			May 30 04:17:41 PM PDT 24	May 30 04:24:25 PM PDT 24	3209864897 ps
T68	/workspace/coverage/default/1.chip_tap_straps_testunlock0.3627178125			May 30 04:20:23 PM PDT 24	May 30 04:35:49 PM PDT 24	9434709982 ps
T319	/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.793281380			May 30 04:41:39 PM PDT 24	May 30 04:46:18 PM PDT 24	3601868500 ps
T237	/workspace/coverage/default/2.chip_sw_flash_init.4270656048			May 30 04:24:50 PM PDT 24	May 30 04:56:13 PM PDT 24	21889753516 ps
T238	/workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.2985709747			May 30 04:15:17 PM PDT 24	May 30 05:43:00 PM PDT 24	48165077879 ps
T239	/workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.1412601368			May 30 04:09:33 PM PDT 24	May 30 05:36:25 PM PDT 24	45289205375 ps
T880	/workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.878170983			May 30 04:23:25 PM PDT 24	May 30 04:39:18 PM PDT 24	5450572600 ps
T320	/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.852337591			May 30 04:38:00 PM PDT 24	May 30 04:44:34 PM PDT 24	3268103624 ps
T169	/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.1051125643			May 30 04:10:20 PM PDT 24	May 30 04:12:50 PM PDT 24	2687739953 ps
T881	/workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.2924385388			May 30 04:31:55 PM PDT 24	May 30 04:37:32 PM PDT 24	3137469536 ps
T882	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.2086740242			May 30 04:11:39 PM PDT 24	May 30 04:16:28 PM PDT 24	2763412024 ps
T883	/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.3242409672			May 30 04:19:40 PM PDT 24	May 30 05:19:47 PM PDT 24	14187409386 ps
T241	/workspace/coverage/default/0.chip_sw_flash_init.2788743877			May 30 04:09:37 PM PDT 24	May 30 04:42:11 PM PDT 24	16760977952 ps
T7	/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.1889888996			May 30 04:11:58 PM PDT 24	May 30 04:18:55 PM PDT 24	3223347900 ps
T422	/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.335740222			May 30 04:21:31 PM PDT 24	May 30 05:23:03 PM PDT 24	15675630780 ps
T423	/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.1294596023			May 30 04:33:58 PM PDT 24	May 30 04:41:23 PM PDT 24	3978428168 ps
T424	/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.3344055635			May 30 04:35:31 PM PDT 24	May 30 04:42:22 PM PDT 24	3406289536 ps
T324	/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.1929560459			May 30 04:26:36 PM PDT 24	May 30 04:56:52 PM PDT 24	11852897144 ps
T425	/workspace/coverage/default/1.chip_sw_aes_enc.859383538			May 30 04:22:13 PM PDT 24	May 30 04:27:36 PM PDT 24	2356328968 ps
T67	/workspace/coverage/default/3.chip_tap_straps_testunlock0.4081206287			May 30 04:32:12 PM PDT 24	May 30 04:40:54 PM PDT 24	5649145861 ps
T175	/workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.298223377			May 30 04:20:46 PM PDT 24	May 30 04:24:43 PM PDT 24	2591082136 ps
T298	/workspace/coverage/default/1.chip_sw_clkmgr_smoketest.1124115105			May 30 04:25:01 PM PDT 24	May 30 04:29:16 PM PDT 24	2093699896 ps
T299	/workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.2146863687			May 30 04:28:28 PM PDT 24	May 30 04:32:07 PM PDT 24	2226946640 ps
T170	/workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.2249150071			May 30 04:10:20 PM PDT 24	May 30 04:12:21 PM PDT 24	3063796504 ps
T300	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.3455045123			May 30 04:26:42 PM PDT 24	May 30 04:38:53 PM PDT 24	3906203346 ps
T161	/workspace/coverage/default/81.chip_sw_all_escalation_resets.3100691800			May 30 04:44:19 PM PDT 24	May 30 04:53:07 PM PDT 24	5378060344 ps
T301	/workspace/coverage/default/83.chip_sw_all_escalation_resets.1692923504			May 30 04:42:04 PM PDT 24	May 30 04:51:22 PM PDT 24	5012342754 ps
T302	/workspace/coverage/default/0.rom_e2e_asm_init_prod.614747640			May 30 04:19:30 PM PDT 24	May 30 05:11:30 PM PDT 24	14188210305 ps
T303	/workspace/coverage/default/1.chip_sw_example_concurrency.2030111281			May 30 04:14:01 PM PDT 24	May 30 04:18:11 PM PDT 24	2788423040 ps
T212	/workspace/coverage/default/0.chip_sw_pattgen_ios.1939778900			May 30 04:08:54 PM PDT 24	May 30 04:14:17 PM PDT 24	3052362384 ps
T767	/workspace/coverage/default/20.chip_sw_all_escalation_resets.4203951809			May 30 04:35:38 PM PDT 24	May 30 04:44:53 PM PDT 24	5037304936 ps
T884	/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.468420727			May 30 04:10:13 PM PDT 24	May 30 04:36:01 PM PDT 24	7996159880 ps
T885	/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.2033805935			May 30 04:34:31 PM PDT 24	May 30 05:18:29 PM PDT 24	12878015912 ps
T699	/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.1389571172			May 30 04:35:03 PM PDT 24	May 30 04:43:54 PM PDT 24	3491276438 ps
T118	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.3599319158			May 30 04:30:08 PM PDT 24	May 30 04:36:11 PM PDT 24	5933539560 ps
T886	/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.2343072930			May 30 04:34:38 PM PDT 24	May 30 04:46:08 PM PDT 24	4449705948 ps
T217	/workspace/coverage/default/2.chip_sw_inject_scramble_seed.2198674559			May 30 04:26:52 PM PDT 24	May 30 07:28:13 PM PDT 24	63400084483 ps
T887	/workspace/coverage/default/2.chip_sw_uart_tx_rx.3030091905			May 30 04:24:59 PM PDT 24	May 30 04:34:07 PM PDT 24	4020906364 ps
T333	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1701137191			May 30 04:31:29 PM PDT 24	May 30 04:41:50 PM PDT 24	4931528777 ps
T888	/workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.3889231818			May 30 04:18:50 PM PDT 24	May 30 04:23:17 PM PDT 24	2557677454 ps
T889	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.3047295954			May 30 04:26:26 PM PDT 24	May 30 04:38:35 PM PDT 24	6584087138 ps
T114	/workspace/coverage/default/1.chip_sw_edn_boot_mode.1683633139			May 30 04:17:33 PM PDT 24	May 30 04:25:22 PM PDT 24	3154865064 ps
T134	/workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.4191669100			May 30 04:26:28 PM PDT 24	May 30 04:35:25 PM PDT 24	7258379202 ps
T176	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.1441209509			May 30 04:13:15 PM PDT 24	May 30 04:17:50 PM PDT 24	2072824416 ps
T890	/workspace/coverage/default/0.chip_sw_clkmgr_jitter.1416691839			May 30 04:11:32 PM PDT 24	May 30 04:15:05 PM PDT 24	2758833538 ps
T666	/workspace/coverage/default/2.chip_sw_power_idle_load.2569258801			May 30 04:32:16 PM PDT 24	May 30 04:43:19 PM PDT 24	4508781240 ps
T69	/workspace/coverage/default/3.chip_tap_straps_rma.1868032434			May 30 04:31:54 PM PDT 24	May 30 04:40:39 PM PDT 24	4899980191 ps
T740	/workspace/coverage/default/47.chip_sw_all_escalation_resets.2171527125			May 30 04:40:48 PM PDT 24	May 30 04:51:34 PM PDT 24	4899021120 ps
T891	/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.8592364			May 30 04:23:50 PM PDT 24	May 30 04:32:23 PM PDT 24	4922081686 ps
T696	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.2273102873			May 30 04:11:37 PM PDT 24	May 30 04:17:44 PM PDT 24	3815258590 ps
T330	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.539887550			May 30 04:32:49 PM PDT 24	May 30 04:43:36 PM PDT 24	4245011218 ps
T29	/workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.3388958865			May 30 04:12:57 PM PDT 24	May 30 04:19:06 PM PDT 24	2887202404 ps
T892	/workspace/coverage/default/0.rom_e2e_asm_init_dev.2839715140			May 30 04:22:34 PM PDT 24	May 30 05:27:45 PM PDT 24	14115351409 ps
T59	/workspace/coverage/default/1.chip_sw_alert_test.2777495155			May 30 04:16:29 PM PDT 24	May 30 04:22:25 PM PDT 24	3155394610 ps