Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_ret_aon__ram_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	137801	1			T73	219		T74	7		T75	63
values[2]	10030	1			T73	2		T75	4		T79	6
values[3]	3773	1			T73	1		T79	1		T473	3
values[4]	2120	1			T79	1		T523	21		T463	89
values[5]	1491	1			T523	5		T463	62		T661	17
values[6]	1050	1			T523	3		T463	28		T685	11
values[7]	760	1			T463	23		T685	5		T828	4
values[8]	604	1			T463	14		T685	5		T828	5
values[9]	506	1			T463	8		T685	10		T828	1
values[10]	402	1			T685	12		T777	3		T455	17
values[11]	293	1			T685	8		T777	4		T455	7
values[12]	304	1			T685	3		T777	1		T455	5
values[13]	326	1			T685	8		T777	5		T455	3
values[14]	324	1			T685	12		T777	5		T455	6
values[15]	285	1			T685	3		T777	2		T455	7
values[16]	285	1			T685	5		T777	1		T455	15
values[17]	293	1			T685	8		T777	2		T455	10
values[18]	288	1			T685	7		T777	3		T455	7
values[19]	286	1			T685	8		T777	5		T455	11
values[20]	312	1			T685	7		T777	1		T455	6
values[21]	249	1			T685	3		T777	2		T455	5
values[22]	280	1			T685	11		T777	2		T455	7
values[23]	275	1			T685	6		T777	4		T455	16
values[24]	269	1			T685	23		T777	2		T455	13
values[25]	276	1			T685	6		T777	1		T455	11
values[26]	282	1			T685	9		T777	2		T455	9
values[27]	277	1			T685	7		T777	3		T455	8
values[28]	287	1			T685	3		T777	7		T455	18
values[29]	256	1			T685	7		T777	6		T455	6
values[30]	294	1			T685	4		T777	5		T455	7
values[31]	256	1			T685	7		T777	4		T455	4
values[32]	243	1			T685	5		T777	5		T455	4
values[33]	229	1			T685	6		T777	1		T455	5
values[34]	262	1			T685	4		T777	1		T455	2
values[35]	234	1			T685	4		T777	3		T455	3
values[36]	236	1			T685	6		T777	1		T455	5
values[37]	239	1			T685	3		T777	1		T455	6
values[38]	245	1			T685	8		T777	3		T455	4
values[39]	312	1			T685	16		T777	4		T455	8
values[40]	235	1			T685	4		T777	1		T455	3
values[41]	255	1			T685	6		T777	5		T455	6
values[42]	279	1			T685	19		T777	4		T455	8
values[43]	273	1			T685	6		T777	4		T455	9
values[44]	219	1			T685	5		T777	1		T455	9
values[45]	200	1			T685	7		T777	4		T455	4
values[46]	246	1			T685	5		T777	1		T455	6
values[47]	238	1			T685	11		T777	2		T455	9
values[48]	198	1			T685	9		T777	2		T455	7
values[49]	264	1			T685	2		T777	1		T455	10
values[50]	209	1			T777	1		T455	7		T470	5
values[51]	216	1			T777	1		T455	6		T470	15
values[52]	207	1			T777	2		T455	5		T470	14
values[53]	187	1			T777	2		T455	13		T470	11
values[54]	199	1			T777	1		T455	11		T470	4
values[55]	191	1			T777	4		T455	20		T470	2
values[56]	161	1			T777	4		T455	10		T470	2
values[57]	179	1			T777	2		T455	7		T470	6
values[58]	170	1			T777	1		T455	9		T470	4
values[59]	195	1			T777	3		T455	14		T470	3
values[60]	172	1			T777	7		T470	2		T797	1
values[61]	151	1			T777	5		T470	2		T797	1
values[62]	159	1			T777	4		T470	4		T797	1
values[63]	115	1			T777	5		T470	2		T797	1
values[64]	179	1			T777	2		T470	4		T797	1
values[65]	181	1			T777	4		T470	1		T797	1
values[66]	147	1			T777	1		T470	9		T797	1
values[67]	176	1			T777	5		T470	6		T797	1
values[68]	159	1			T777	2		T470	1		T797	1
values[69]	153	1			T777	1		T470	2		T797	1
values[70]	120	1			T777	2		T470	4		T797	1
values[71]	88	1			T777	5		T470	11		T797	1
values[72]	92	1			T777	2		T470	2		T797	1
values[73]	105	1			T777	2		T470	1		T797	1
values[74]	119	1			T777	3		T470	3		T797	1
values[75]	105	1			T777	3		T470	3		T797	1
values[76]	99	1			T777	1		T470	1		T797	1
values[77]	129	1			T777	4		T470	1		T797	1
values[78]	97	1			T777	4		T470	1		T797	2
values[79]	97	1			T777	3		T470	2		T797	1
values[80]	76	1			T777	4		T470	3		T797	1
values[81]	85	1			T777	2		T470	3		T797	1
values[82]	75	1			T777	1		T470	1		T797	1
values[83]	86	1			T777	1		T470	2		T797	1
values[84]	104	1			T777	2		T470	3		T797	1
values[85]	63	1			T777	1		T470	1		T797	1
values[86]	101	1			T777	2		T470	3		T797	1
values[87]	84	1			T777	1		T470	6		T797	1
values[88]	91	1			T777	2		T470	4		T797	1
values[89]	101	1			T777	4		T470	4		T797	1
values[90]	82	1			T777	1		T470	2		T797	3
values[91]	68	1			T777	6		T470	1		T797	3
values[92]	67	1			T777	9		T470	2		T797	1
values[93]	86	1			T777	15		T470	4		T797	1
values[94]	74	1			T777	10		T470	6		T797	3
values[95]	61	1			T777	5		T470	1		T797	2
values[96]	70	1			T777	2		T470	4		T797	8
values[97]	56	1			T777	3		T470	3		T797	2
values[98]	77	1			T777	3		T470	1		T797	1
values[99]	79	1			T777	5		T470	4		T797	4
values[100]	89	1			T777	14		T470	3		T797	7
values[101]	90	1			T777	9		T470	2		T797	2
values[102]	85	1			T777	3		T470	5		T797	2
values[103]	69	1			T777	2		T470	10		T797	2
values[104]	85	1			T777	10		T470	9		T797	2
values[105]	77	1			T777	6		T470	6		T797	4
values[106]	91	1			T777	4		T470	18		T797	1
values[107]	74	1			T777	6		T470	7		T797	1
values[108]	88	1			T777	8		T470	1		T797	2
values[109]	86	1			T777	7		T470	4		T797	1
values[110]	79	1			T777	6		T470	10		T797	1
values[111]	88	1			T777	4		T470	14		T797	1
values[112]	93	1			T777	5		T470	12		T797	1
values[113]	89	1			T777	12		T470	8		T797	3
values[114]	85	1			T777	9		T470	7		T797	2
values[115]	87	1			T777	5		T470	4		T797	2
values[116]	57	1			T777	3		T470	6		T797	3
values[117]	79	1			T777	8		T470	8		T797	3
values[118]	75	1			T777	3		T470	3		T797	2
values[119]	70	1			T777	7		T470	4		T797	2
values[120]	77	1			T777	4		T470	5		T797	3
values[121]	71	1			T777	7		T470	4		T797	1
values[122]	62	1			T777	3		T470	1		T797	1
values[123]	85	1			T777	5		T470	2		T797	3
values[124]	62	1			T777	1		T470	1		T797	1
values[125]	83	1			T470	8		T797	2		T784	3
values[126]	145	1			T470	8		T797	2		T784	3
values[127]	755	1			T470	2		T797	28		T784	42
values[128]	6454	1			T470	3		T797	316		T784	351