Unified Coverage Report :: Group Instance : sensor_ctrl

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T79	1	T529	1	T473	1
small_delay	672	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T529	1	T538	1	T469	1
small_delay	972	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T79	1	T529	1	T473	1
small_delay	672	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T529	1	T538	1	T469	1
small_delay	972	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T79	1	T529	1	T473	1
small_delay	672	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T529	1	T538	1	T469	1
small_delay	972	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T79	1	T529	1	T473	1
small_delay	672	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T529	1	T538	1	T469	1
small_delay	972	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T79	1	T529	1	T473	1
small_delay	672	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T529	1	T538	1	T469	1
small_delay	972	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T79	1	T529	1	T473	1
small_delay	672	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T529	1	T538	1	T469	1
small_delay	972	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T79	1	T529	1	T473	1
small_delay	672	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T529	1	T538	1	T469	1
small_delay	972	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T79	1	T529	1	T473	1
small_delay	672	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T529	1	T538	1	T469	1
small_delay	972	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T79	1	T529	1	T473	1
small_delay	672	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T529	1	T538	1	T469	1
small_delay	972	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T79	1	T529	1	T473	1
small_delay	672	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T529	1	T538	1	T469	1
small_delay	972	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T79	1	T529	1	T473	1
small_delay	672	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T529	1	T538	1	T469	1
small_delay	972	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T79	1	T529	1	T473	1
small_delay	672	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T529	1	T538	1	T469	1
small_delay	972	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T79	1	T529	1	T473	1
small_delay	672	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T529	1	T538	1	T469	1
small_delay	972	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T79	1	T529	1	T473	1
small_delay	672	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T529	1	T538	1	T469	1
small_delay	972	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T79	1	T529	1	T473	1
small_delay	672	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T529	1	T538	1	T469	1
small_delay	972	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T79	1	T529	1	T473	1
small_delay	672	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T529	1	T538	1	T469	1
small_delay	972	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T79	1	T529	1	T473	1
small_delay	672	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T529	1	T538	1	T469	1
small_delay	972	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T79	1	T529	1	T473	1
small_delay	672	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T529	1	T538	1	T469	1
small_delay	972	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T79	1	T529	1	T473	1
small_delay	672	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T529	1	T538	1	T469	1
small_delay	972	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T79	1	T529	1	T473	1
small_delay	672	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T529	1	T538	1	T469	1
small_delay	972	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T79	1	T529	1	T473	1
small_delay	672	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T529	1	T538	1	T469	1
small_delay	972	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T79	1	T529	1	T473	1
small_delay	672	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T529	1	T538	1	T469	1
small_delay	972	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T79	1	T529	1	T473	1
small_delay	672	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T529	1	T538	1	T469	1
small_delay	972	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T79	1	T529	1	T473	1
small_delay	672	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T529	1	T538	1	T469	1
small_delay	972	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T79	1	T529	1	T473	1
small_delay	672	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T529	1	T538	1	T469	1
small_delay	972	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T79	1	T529	1	T473	1
small_delay	672	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T529	1	T538	1	T469	1
small_delay	972	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T79	1	T529	1	T473	1
small_delay	672	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T529	1	T538	1	T469	1
small_delay	972	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T79	1	T529	1	T473	1
small_delay	672	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T529	1	T538	1	T469	1
small_delay	972	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T79	1	T529	1	T473	1
small_delay	672	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T529	1	T538	1	T469	1
small_delay	972	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T79	1	T529	1	T473	1
small_delay	672	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T529	1	T538	1	T469	1
small_delay	972	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T79	1	T529	1	T473	1
small_delay	672	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T529	1	T538	1	T469	1
small_delay	972	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T79	1	T529	1	T473	1
small_delay	672	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T529	1	T538	1	T469	1
small_delay	972	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T529	1	T538	1	T469	1
small_delay	972	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T79	1	T529	1	T473	1
small_delay	672	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T529	1	T538	1	T469	1
small_delay	972	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T79	1	T529	1	T473	1
small_delay	672	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T79	1	T529	1	T473	1
small_delay	672	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T529	1	T538	1	T469	1
small_delay	972	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T79	1	T529	1	T473	1
small_delay	672	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T529	1	T538	1	T469	1
small_delay	972	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T529	1	T538	1	T469	1
small_delay	972	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T79	1	T529	1	T473	1
small_delay	672	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T79	1	T529	1	T473	1
small_delay	672	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T529	1	T538	1	T469	1
small_delay	972	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T79	1	T529	1	T473	1
small_delay	672	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T529	1	T538	1	T469	1
small_delay	972	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	500	1		T79	1	T529	1	T473	1
small_delay	672	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
big_delay	200	1		T529	1	T538	1	T469	1
small_delay	972	1		T73	1	T75	1	T144	1
zero	628	1		T74	1	T255	1	T527	1