Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	492	1			T534	1		T449	1		T521	1
all_values[1]	498	1			T73	2		T449	4		T525	2
all_values[2]	519	1			T526	1		T780	3		T661	2
all_values[3]	502	1			T73	2		T525	1		T521	1
all_values[4]	457	1			T73	2		T449	1		T523	1
all_values[5]	473	1			T449	2		T523	2		T463	2
all_values[6]	493	1			T449	1		T523	3		T463	4
all_values[7]	456	1			T449	1		T525	1		T521	1
all_values[8]	486	1			T73	2		T534	1		T521	1
all_values[9]	483	1			T449	2		T521	1		T663	1
all_values[10]	505	1			T454	1		T449	2		T521	1
all_values[11]	459	1			T521	1		T526	1		T663	2
all_values[12]	458	1			T449	2		T521	1		T661	3
all_values[13]	506	1			T449	5		T523	1		T663	1
all_values[14]	480	1			T449	4		T523	1		T661	2
all_values[15]	481	1			T454	1		T449	1		T525	1
all_values[16]	465	1			T73	1		T534	1		T449	3
all_values[17]	452	1			T454	2		T449	1		T523	1
all_values[18]	434	1			T73	1		T449	3		T526	1
all_values[19]	472	1			T521	1		T661	1		T621	2
all_values[20]	474	1			T73	1		T454	1		T449	3
all_values[21]	468	1			T449	1		T526	1		T663	1
all_values[22]	467	1			T454	2		T449	1		T463	2
all_values[23]	492	1			T463	1		T610	2		T621	1
all_values[24]	527	1			T73	1		T449	2		T523	3
all_values[25]	479	1			T449	3		T663	2		T661	2
all_values[26]	507	1			T454	1		T449	5		T463	1
all_values[27]	485	1			T73	1		T454	2		T449	1
all_values[28]	485	1			T449	1		T463	5		T663	1
all_values[29]	467	1			T73	1		T454	1		T534	1
all_values[30]	505	1			T449	1		T523	3		T780	1
all_values[31]	513	1			T534	1		T521	1		T523	1
all_values[32]	476	1			T73	2		T454	2		T449	3
all_values[33]	499	1			T454	3		T521	1		T463	4
all_values[34]	472	1			T73	1		T534	1		T525	1
all_values[35]	458	1			T449	1		T463	1		T661	1
all_values[36]	445	1			T449	3		T526	1		T661	3
all_values[37]	436	1			T73	1		T534	1		T449	2
all_values[38]	487	1			T449	1		T463	1		T661	3
all_values[39]	480	1			T454	2		T449	1		T521	1
all_values[40]	476	1			T449	1		T521	1		T523	2
all_values[41]	505	1			T73	1		T449	1		T523	1
all_values[42]	450	1			T73	1		T463	1		T526	1
all_values[43]	460	1			T449	2		T523	3		T463	2
all_values[44]	496	1			T449	2		T463	2		T526	2
all_values[45]	476	1			T449	3		T523	2		T463	3
all_values[46]	509	1			T73	1		T454	2		T449	1
all_values[47]	481	1			T73	1		T521	1		T526	1
all_values[48]	467	1			T534	1		T449	1		T521	1
all_values[49]	465	1			T73	3		T449	1		T463	1