Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3557	1			T73	3		T255	6		T449	13
all_values[1]	3630	1			T73	1		T255	7		T449	11
all_values[2]	3546	1			T255	3		T449	11		T525	2
all_values[3]	3449	1			T73	1		T255	4		T449	8
all_values[4]	3640	1			T73	2		T255	7		T449	10
all_values[5]	3654	1			T454	2		T255	6		T449	16
all_values[6]	3520	1			T73	1		T255	4		T449	21
all_values[7]	3564	1			T73	2		T255	3		T449	6
all_values[8]	3552	1			T454	1		T255	4		T449	12
all_values[9]	3600	1			T73	1		T255	2		T449	9
all_values[10]	3600	1			T255	5		T449	11		T525	3
all_values[11]	3611	1			T73	2		T255	9		T449	11
all_values[12]	3560	1			T73	2		T454	1		T255	2
all_values[13]	3599	1			T255	5		T449	11		T523	5
all_values[14]	3546	1			T73	2		T255	5		T449	17
all_values[15]	3535	1			T73	1		T454	1		T255	7
all_values[16]	3623	1			T73	1		T255	8		T449	12
all_values[17]	3533	1			T73	1		T255	8		T449	12
all_values[18]	3626	1			T73	1		T255	5		T449	16
all_values[19]	3457	1			T454	2		T255	8		T449	12
all_values[20]	3551	1			T255	5		T449	12		T525	1
all_values[21]	3515	1			T255	7		T449	9		T525	3
all_values[22]	3580	1			T73	1		T255	5		T449	15
all_values[23]	3522	1			T255	5		T449	13		T525	1
all_values[24]	3508	1			T255	9		T449	10		T525	2
all_values[25]	3580	1			T255	4		T449	10		T525	2
all_values[26]	3508	1			T255	7		T449	8		T525	6
all_values[27]	3618	1			T255	6		T449	12		T525	6
all_values[28]	3633	1			T255	4		T449	14		T525	4
all_values[29]	3654	1			T255	8		T449	9		T525	1
all_values[30]	3632	1			T255	5		T449	8		T525	1
all_values[31]	3490	1			T255	4		T449	5		T525	1
all_values[32]	3616	1			T73	2		T255	9		T449	12
all_values[33]	3630	1			T454	1		T255	6		T449	12
all_values[34]	3626	1			T255	13		T449	10		T525	2
all_values[35]	3418	1			T255	6		T449	15		T525	2
all_values[36]	3625	1			T73	1		T255	2		T449	9
all_values[37]	3521	1			T255	5		T449	15		T525	3
all_values[38]	3594	1			T255	4		T449	12		T525	5
all_values[39]	3503	1			T73	2		T255	4		T449	10
all_values[40]	3505	1			T73	1		T255	5		T449	10
all_values[41]	3665	1			T73	1		T255	5		T449	11
all_values[42]	3551	1			T255	3		T449	13		T525	2
all_values[43]	3569	1			T255	8		T449	9		T525	3
all_values[44]	3573	1			T454	1		T255	8		T449	15
all_values[45]	3526	1			T255	8		T449	13		T525	4
all_values[46]	3551	1			T255	3		T449	9		T525	3
all_values[47]	3545	1			T73	1		T255	8		T449	8
all_values[48]	3472	1			T255	4		T449	15		T525	2
all_values[49]	3690	1			T255	5		T449	8		T522	1
all_values[50]	3682	1			T454	1		T255	5		T449	10
all_values[51]	3506	1			T255	4		T449	13		T525	3
all_values[52]	3553	1			T255	5		T449	20		T525	3
all_values[53]	3581	1			T73	1		T255	5		T449	17
all_values[54]	3650	1			T255	5		T449	9		T525	3
all_values[55]	3629	1			T454	1		T255	6		T449	10
all_values[56]	3517	1			T454	1		T255	10		T449	12
all_values[57]	3633	1			T73	1		T255	4		T449	7
all_values[58]	3510	1			T73	1		T255	7		T449	10
all_values[59]	3599	1			T255	8		T449	23		T525	2
all_values[60]	3592	1			T73	2		T255	4		T449	12
all_values[61]	3507	1			T73	1		T454	1		T255	3
all_values[62]	3509	1			T255	5		T449	16		T525	4
all_values[63]	3537	1			T73	2		T454	1		T255	7