Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.alert_handler_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	132408	1			T76	66		T77	322		T78	6
values[2]	8488	1			T76	5		T79	3		T473	2
values[3]	3280	1			T677	1		T459	12		T807	1
values[4]	1832	1			T677	1		T459	9		T807	1
values[5]	1099	1			T677	1		T459	1		T807	1
values[6]	835	1			T677	1		T807	1		T566	8
values[7]	575	1			T677	1		T807	1		T566	9
values[8]	496	1			T677	1		T807	1		T566	4
values[9]	417	1			T677	1		T807	1		T566	1
values[10]	380	1			T677	1		T807	1		T511	10
values[11]	355	1			T677	1		T807	1		T511	11
values[12]	402	1			T677	1		T807	1		T511	5
values[13]	374	1			T677	1		T807	1		T511	10
values[14]	322	1			T677	1		T807	1		T511	10
values[15]	360	1			T677	1		T807	1		T511	6
values[16]	289	1			T677	1		T807	1		T511	5
values[17]	306	1			T677	1		T807	1		T511	9
values[18]	305	1			T677	1		T807	1		T511	14
values[19]	293	1			T677	1		T807	1		T511	8
values[20]	267	1			T677	1		T807	1		T511	8
values[21]	282	1			T677	1		T807	1		T511	5
values[22]	279	1			T677	1		T807	1		T511	6
values[23]	284	1			T677	1		T807	1		T511	7
values[24]	238	1			T677	1		T807	1		T511	13
values[25]	274	1			T677	1		T807	1		T511	12
values[26]	265	1			T677	1		T807	1		T511	23
values[27]	253	1			T677	1		T807	1		T511	10
values[28]	326	1			T677	1		T807	1		T511	10
values[29]	271	1			T677	1		T807	1		T511	9
values[30]	304	1			T677	1		T807	1		T511	9
values[31]	288	1			T677	1		T807	1		T511	11
values[32]	276	1			T677	1		T807	1		T511	7
values[33]	244	1			T677	1		T807	1		T511	4
values[34]	261	1			T677	1		T807	1		T511	2
values[35]	256	1			T677	1		T807	1		T511	1
values[36]	261	1			T677	1		T807	1		T511	3
values[37]	300	1			T677	1		T807	1		T511	4
values[38]	267	1			T677	1		T807	2		T511	2
values[39]	264	1			T677	1		T807	1		T511	1
values[40]	226	1			T677	1		T807	1		T511	3
values[41]	222	1			T677	1		T807	1		T511	2
values[42]	223	1			T677	1		T807	1		T511	5
values[43]	205	1			T677	1		T807	1		T511	2
values[44]	244	1			T677	1		T807	1		T511	1
values[45]	231	1			T677	1		T807	1		T511	2
values[46]	233	1			T677	1		T807	1		T511	5
values[47]	266	1			T677	1		T807	1		T511	3
values[48]	221	1			T677	1		T807	1		T511	1
values[49]	238	1			T677	1		T807	1		T511	2
values[50]	221	1			T677	1		T807	1		T511	3
values[51]	207	1			T677	1		T807	1		T511	10
values[52]	216	1			T677	1		T807	1		T511	11
values[53]	235	1			T677	1		T807	1		T511	7
values[54]	181	1			T677	1		T807	1		T511	1
values[55]	203	1			T677	1		T807	1		T511	3
values[56]	213	1			T677	1		T807	1		T511	1
values[57]	179	1			T677	1		T807	1		T511	1
values[58]	138	1			T677	1		T807	1		T454	8
values[59]	196	1			T677	1		T807	1		T454	9
values[60]	152	1			T677	1		T807	1		T454	5
values[61]	166	1			T677	1		T807	1		T454	1
values[62]	141	1			T677	1		T807	1		T454	3
values[63]	150	1			T677	1		T807	1		T454	4
values[64]	136	1			T677	1		T807	1		T454	5
values[65]	145	1			T677	1		T807	1		T454	1
values[66]	136	1			T677	1		T807	1		T454	2
values[67]	161	1			T677	1		T807	1		T454	5
values[68]	121	1			T677	1		T807	1		T454	2
values[69]	108	1			T677	1		T807	1		T454	4
values[70]	117	1			T677	1		T807	1		T454	3
values[71]	112	1			T677	1		T807	1		T454	1
values[72]	101	1			T677	1		T807	1		T454	3
values[73]	79	1			T677	1		T807	1		T454	3
values[74]	92	1			T677	1		T807	1		T454	2
values[75]	81	1			T677	1		T807	1		T454	4
values[76]	105	1			T677	1		T807	1		T454	2
values[77]	94	1			T677	1		T807	1		T454	4
values[78]	99	1			T677	1		T807	1		T454	5
values[79]	104	1			T677	1		T807	1		T454	8
values[80]	107	1			T677	1		T807	1		T454	9
values[81]	85	1			T677	1		T807	1		T454	2
values[82]	94	1			T677	1		T807	1		T454	2
values[83]	99	1			T677	1		T807	1		T454	3
values[84]	91	1			T677	1		T807	1		T454	4
values[85]	95	1			T677	1		T807	1		T454	5
values[86]	120	1			T677	1		T807	1		T454	3
values[87]	96	1			T677	1		T807	1		T454	7
values[88]	102	1			T677	1		T807	5		T454	12
values[89]	61	1			T677	1		T807	2		T454	3
values[90]	78	1			T677	1		T807	2		T454	2
values[91]	85	1			T677	1		T807	1		T454	2
values[92]	90	1			T677	1		T807	3		T454	3
values[93]	96	1			T677	1		T807	5		T454	3
values[94]	85	1			T677	1		T807	1		T454	1
values[95]	87	1			T677	1		T807	4		T454	2
values[96]	91	1			T677	1		T807	3		T454	3
values[97]	87	1			T677	1		T807	3		T454	2
values[98]	97	1			T677	4		T807	8		T454	4
values[99]	110	1			T677	8		T807	6		T454	3
values[100]	119	1			T677	3		T807	2		T454	3
values[101]	107	1			T677	1		T807	2		T454	2
values[102]	109	1			T677	2		T807	2		T454	2
values[103]	118	1			T677	7		T807	3		T454	1
values[104]	105	1			T677	1		T807	4		T454	3
values[105]	81	1			T677	2		T807	1		T454	3
values[106]	88	1			T677	1		T807	1		T454	2
values[107]	101	1			T677	2		T807	1		T454	4
values[108]	95	1			T677	2		T807	1		T454	5
values[109]	80	1			T677	1		T807	1		T454	1
values[110]	86	1			T677	2		T807	1		T454	1
values[111]	77	1			T677	2		T807	1		T454	2
values[112]	95	1			T677	2		T807	3		T454	3
values[113]	94	1			T677	2		T807	2		T454	3
values[114]	91	1			T677	1		T807	4		T454	6
values[115]	93	1			T677	2		T807	2		T454	3
values[116]	77	1			T677	1		T807	2		T454	2
values[117]	84	1			T677	3		T807	2		T454	6
values[118]	79	1			T677	3		T807	1		T454	5
values[119]	85	1			T677	1		T807	1		T454	6
values[120]	96	1			T677	2		T807	4		T454	12
values[121]	87	1			T677	4		T807	3		T454	5
values[122]	92	1			T677	5		T807	6		T454	3
values[123]	79	1			T677	2		T807	3		T454	3
values[124]	78	1			T677	2		T807	1		T454	9
values[125]	98	1			T677	4		T807	1		T454	15
values[126]	160	1			T677	2		T807	2		T454	32
values[127]	814	1			T677	23		T807	38		T454	61
values[128]	6358	1			T677	304		T807	309		T454	35

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	149242	1			T76	61		T77	352		T78	5
values[2]	3967	1			T76	4		T78	1		T79	1
values[3]	1929	1			T677	1		T551	1		T808	1
values[4]	1458	1			T677	1		T551	1		T808	1
values[5]	1185	1			T677	1		T551	1		T808	1
values[6]	919	1			T677	1		T551	1		T808	1
values[7]	829	1			T677	1		T551	1		T808	1
values[8]	700	1			T677	1		T551	1		T808	1
values[9]	594	1			T677	1		T551	1		T808	1
values[10]	515	1			T677	1		T551	1		T808	1
values[11]	593	1			T677	1		T551	1		T808	1
values[12]	608	1			T677	1		T551	1		T808	1
values[13]	550	1			T677	1		T551	1		T808	1
values[14]	543	1			T677	1		T551	1		T808	1
values[15]	580	1			T677	1		T551	1		T808	1
values[16]	519	1			T677	1		T551	1		T808	1
values[17]	360	1			T677	1		T551	1		T808	1
values[18]	264	1			T677	1		T551	1		T808	1
values[19]	274	1			T677	1		T551	1		T808	1
values[20]	237	1			T677	1		T551	1		T808	1
values[21]	208	1			T677	1		T551	1		T808	1
values[22]	222	1			T677	2		T551	1		T808	1
values[23]	164	1			T677	1		T551	1		T808	1
values[24]	136	1			T677	1		T551	1		T808	1
values[25]	154	1			T677	1		T551	1		T808	1
values[26]	139	1			T677	1		T551	1		T808	1
values[27]	121	1			T677	1		T551	1		T808	1
values[28]	139	1			T677	1		T551	1		T808	1
values[29]	139	1			T677	1		T551	1		T808	1
values[30]	151	1			T677	1		T551	1		T808	1
values[31]	141	1			T677	1		T551	1		T808	1
values[32]	148	1			T677	1		T551	1		T808	1
values[33]	139	1			T677	1		T551	1		T808	1
values[34]	143	1			T677	1		T551	1		T808	1
values[35]	122	1			T677	1		T551	1		T808	1
values[36]	105	1			T677	1		T551	1		T808	1
values[37]	100	1			T677	1		T551	1		T808	1
values[38]	116	1			T677	1		T551	1		T808	1
values[39]	86	1			T677	1		T551	1		T808	1
values[40]	103	1			T677	1		T551	1		T808	1
values[41]	107	1			T677	1		T551	1		T808	1
values[42]	88	1			T677	1		T551	1		T808	1
values[43]	77	1			T677	1		T551	1		T808	1
values[44]	68	1			T677	1		T551	1		T808	1
values[45]	64	1			T677	1		T551	1		T808	1
values[46]	76	1			T677	1		T551	1		T808	1
values[47]	66	1			T677	1		T551	1		T808	1
values[48]	68	1			T677	1		T551	1		T808	1
values[49]	86	1			T677	1		T551	1		T808	1
values[50]	104	1			T677	1		T551	1		T808	1
values[51]	103	1			T677	1		T551	1		T808	1
values[52]	112	1			T677	1		T551	1		T808	1
values[53]	102	1			T677	1		T551	1		T808	1
values[54]	84	1			T677	1		T551	1		T808	1
values[55]	62	1			T677	1		T551	1		T808	1
values[56]	44	1			T677	1		T551	1		T808	1
values[57]	52	1			T677	1		T551	1		T808	1
values[58]	58	1			T677	1		T551	1		T808	1
values[59]	53	1			T677	1		T551	1		T808	1
values[60]	54	1			T677	1		T551	1		T808	1
values[61]	56	1			T677	1		T551	1		T808	1
values[62]	64	1			T677	1		T551	1		T808	1
values[63]	57	1			T677	1		T551	1		T808	1
values[64]	46	1			T677	1		T551	1		T808	1
values[65]	47	1			T677	1		T551	1		T808	2
values[66]	58	1			T677	1		T551	1		T808	1
values[67]	52	1			T677	1		T551	1		T808	1
values[68]	58	1			T677	1		T551	1		T808	1
values[69]	40	1			T677	1		T551	1		T808	1
values[70]	43	1			T677	1		T551	1		T808	1
values[71]	44	1			T677	1		T551	1		T808	1
values[72]	47	1			T677	1		T551	1		T808	1
values[73]	44	1			T677	1		T551	1		T808	1
values[74]	49	1			T677	1		T551	1		T808	1
values[75]	44	1			T677	1		T551	1		T808	1
values[76]	56	1			T677	1		T551	1		T808	1
values[77]	55	1			T677	1		T551	1		T808	1
values[78]	40	1			T677	1		T551	1		T808	1
values[79]	49	1			T677	1		T551	1		T808	1
values[80]	54	1			T677	1		T551	1		T808	1
values[81]	47	1			T677	1		T551	1		T808	1
values[82]	41	1			T677	1		T551	1		T808	1
values[83]	46	1			T677	1		T551	1		T808	1
values[84]	52	1			T677	1		T551	1		T808	2
values[85]	50	1			T677	2		T551	1		T808	1
values[86]	47	1			T677	2		T551	1		T808	1
values[87]	62	1			T677	6		T551	1		T808	1
values[88]	61	1			T677	6		T551	1		T808	1
values[89]	63	1			T677	7		T551	1		T808	4
values[90]	67	1			T677	4		T551	1		T808	1
values[91]	58	1			T677	5		T551	1		T808	1
values[92]	57	1			T677	2		T551	1		T808	4
values[93]	61	1			T677	5		T551	1		T808	2
values[94]	77	1			T677	1		T551	1		T808	1
values[95]	60	1			T677	1		T551	1		T808	2
values[96]	62	1			T677	4		T551	1		T808	4
values[97]	70	1			T677	3		T551	1		T808	3
values[98]	74	1			T677	7		T551	1		T808	7
values[99]	76	1			T677	4		T551	1		T808	4
values[100]	77	1			T677	2		T551	1		T808	4
values[101]	67	1			T677	1		T551	1		T808	1
values[102]	69	1			T677	1		T551	1		T808	1
values[103]	79	1			T677	4		T551	1		T808	3
values[104]	69	1			T677	2		T551	1		T808	2
values[105]	82	1			T677	3		T551	2		T808	2
values[106]	88	1			T677	3		T551	1		T808	2
values[107]	90	1			T677	3		T551	1		T808	1
values[108]	92	1			T677	1		T551	1		T808	7
values[109]	83	1			T677	3		T551	1		T808	2
values[110]	76	1			T677	3		T551	1		T808	1
values[111]	93	1			T677	3		T551	7		T808	1
values[112]	94	1			T677	2		T551	5		T808	1
values[113]	79	1			T677	2		T551	2		T808	2
values[114]	79	1			T677	3		T551	1		T808	4
values[115]	99	1			T677	1		T551	1		T808	3
values[116]	92	1			T677	1		T551	1		T808	2
values[117]	90	1			T677	1		T551	1		T808	1
values[118]	101	1			T677	1		T551	1		T808	2
values[119]	90	1			T677	1		T551	2		T808	1
values[120]	98	1			T677	3		T551	1		T808	1
values[121]	98	1			T677	3		T551	2		T808	1
values[122]	118	1			T677	5		T551	2		T808	1
values[123]	129	1			T677	3		T551	3		T808	2
values[124]	200	1			T677	1		T551	1		T808	2
values[125]	344	1			T677	1		T551	3		T808	1
values[126]	736	1			T677	14		T551	14		T808	25
values[127]	2828	1			T677	115		T551	115		T808	132
values[128]	4813	1			T677	187		T551	227		T808	175

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	139017	1			T76	74		T77	321		T79	70
values[2]	10564	1			T76	4		T77	5		T79	2
values[3]	3870	1			T76	1		T77	16		T551	1
values[4]	2462	1			T77	13		T551	1		T459	29
values[5]	1809	1			T77	4		T551	1		T459	20
values[6]	1228	1			T77	2		T551	1		T459	8
values[7]	883	1			T77	4		T551	1		T459	4
values[8]	733	1			T77	9		T551	1		T459	6
values[9]	683	1			T77	6		T551	1		T459	5
values[10]	630	1			T77	18		T551	1		T459	4
values[11]	562	1			T77	5		T551	1		T459	12
values[12]	453	1			T77	6		T551	1		T459	16
values[13]	427	1			T77	10		T551	1		T459	11
values[14]	479	1			T77	8		T551	1		T459	10
values[15]	401	1			T77	6		T551	1		T459	6
values[16]	417	1			T77	13		T551	1		T459	12
values[17]	431	1			T77	7		T551	1		T459	7
values[18]	453	1			T77	12		T551	1		T459	4
values[19]	371	1			T77	11		T551	1		T459	5
values[20]	422	1			T77	9		T551	1		T459	5
values[21]	406	1			T77	9		T551	1		T459	7
values[22]	365	1			T77	11		T551	1		T459	4
values[23]	411	1			T77	8		T551	1		T459	4
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