Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.84	95.42	93.64	95.49		94.45	96.47	99.58

Total tests in report: 2875

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
39.65	39.65	45.04	45.04	43.13	43.13	31.86	31.86			58.02	58.02	59.44	59.44	0.39	0.39	/workspace/coverage/default/8.chip_sw_all_escalation_resets.492676843
49.49	9.84	51.41	6.37	57.67	14.54	32.46	0.60			69.09	11.06	84.62	25.17	1.68	1.29	/workspace/coverage/cover_reg_top/6.chip_same_csr_outstanding.77353021
56.55	7.06	63.71	12.30	62.21	4.54	40.98	8.52			69.99	0.90	84.62	0.00	17.78	16.10	/workspace/coverage/cover_reg_top/19.xbar_stress_all_with_reset_error.2501599497
61.53	4.99	74.59	10.88	69.30	7.09	43.10	2.12			79.83	9.84	84.62	0.00	17.78	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_20.1078564635
65.47	3.93	74.59	0.00	69.61	0.31	43.10	0.00			79.91	0.08	84.62	0.00	40.97	23.19	/workspace/coverage/cover_reg_top/77.xbar_access_same_device_slow_rsp.4289553732
68.77	3.30	80.72	6.13	73.95	4.34	47.10	4.00			81.94	2.03	87.94	3.32	40.97	0.00	/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.1500639542
71.79	3.02	80.72	0.00	73.95	0.00	47.10	0.00			81.94	0.00	87.94	0.00	59.11	18.14	/workspace/coverage/cover_reg_top/82.xbar_access_same_device_slow_rsp.1103427728
74.46	2.67	80.72	0.00	73.95	0.00	63.11	16.01			81.94	0.00	87.94	0.00	59.11	0.00	/workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.3426167297
76.62	2.16	82.69	1.97	76.46	2.51	69.57	6.47			83.75	1.82	88.11	0.17	59.11	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.3699951732
78.57	1.95	82.69	0.00	76.99	0.52	69.57	0.00			83.97	0.21	88.11	0.00	70.09	10.97	/workspace/coverage/cover_reg_top/54.xbar_access_same_device_slow_rsp.166953874
80.11	1.54	82.96	0.27	77.13	0.15	77.87	8.30			84.15	0.18	88.46	0.35	70.09	0.00	/workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.3703054414
81.54	1.43	82.96	0.00	77.13	0.00	77.87	0.00			84.15	0.00	88.46	0.00	78.66	8.58	/workspace/coverage/cover_reg_top/95.xbar_access_same_device_slow_rsp.4019424491
82.92	1.38	83.66	0.70	78.04	0.90	81.86	3.99			84.69	0.55	88.64	0.17	80.61	1.95	/workspace/coverage/default/0.chip_sw_alert_test.3737330000
84.25	1.33	85.65	1.99	80.76	2.72	82.15	0.29			86.98	2.28	89.34	0.70	80.61	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.3357512337
85.52	1.27	87.80	2.15	82.78	2.02	83.17	1.02			89.40	2.43	89.34	0.00	80.61	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_0.4253415543
86.56	1.04	87.80	0.00	83.11	0.33	83.17	0.00			89.47	0.07	89.34	0.00	86.45	5.84	/workspace/coverage/cover_reg_top/78.xbar_access_same_device_slow_rsp.2501373357
87.48	0.92	89.10	1.30	84.12	1.01	83.61	0.44			90.69	1.22	90.91	1.57	86.45	0.00	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2334593133
88.29	0.81	89.81	0.71	84.28	0.16	83.63	0.01			90.84	0.16	94.76	3.85	86.45	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.1302651266
88.89	0.60	89.81	0.00	84.46	0.18	83.63	0.00			90.86	0.02	94.76	0.00	89.82	3.37	/workspace/coverage/cover_reg_top/50.xbar_access_same_device_slow_rsp.1631653927
89.41	0.52	89.81	0.00	84.62	0.15	83.79	0.16			90.86	0.00	94.76	0.00	92.64	2.82	/workspace/coverage/cover_reg_top/38.xbar_random_slow_rsp.144631188
89.92	0.51	90.89	1.08	85.50	0.88	84.16	0.38			91.55	0.69	94.76	0.00	92.64	0.00	/workspace/coverage/default/0.chip_sw_gpio.2499405506
90.39	0.47	90.90	0.01	85.50	0.01	86.96	2.80			91.55	0.00	94.76	0.00	92.64	0.00	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.3262129970
90.83	0.45	90.91	0.01	87.73	2.23	86.96	0.00			91.55	0.00	94.76	0.00	93.08	0.43	/workspace/coverage/cover_reg_top/23.chip_tl_errors.776655153
91.21	0.37	91.50	0.59	88.25	0.51	87.53	0.58			92.12	0.56	94.76	0.00	93.08	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_10.2581636583
91.53	0.33	91.50	0.00	88.28	0.04	87.53	0.00			92.12	0.00	94.76	0.00	95.01	1.93	/workspace/coverage/cover_reg_top/41.xbar_stress_all.2108544294
91.80	0.27	92.34	0.85	88.52	0.23	87.77	0.23			92.24	0.12	94.93	0.17	95.01	0.00	/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.2704591912
92.07	0.26	92.34	0.00	88.52	0.00	89.35	1.59			92.24	0.00	94.93	0.00	95.01	0.00	/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.3702843362
92.30	0.23	92.73	0.39	88.68	0.16	90.09	0.73			92.36	0.11	94.93	0.00	95.01	0.00	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.3296219449
92.51	0.21	92.99	0.25	88.73	0.05	91.00	0.91			92.39	0.03	94.93	0.00	95.01	0.00	/workspace/coverage/default/2.chip_jtag_csr_rw.2426479902
92.69	0.18	93.23	0.24	89.04	0.31	91.26	0.26			92.67	0.29	94.93	0.00	95.01	0.00	/workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.3700304479
92.84	0.15	93.54	0.31	89.30	0.26	91.29	0.03			92.99	0.32	94.93	0.00	95.01	0.00	/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.4278276912
92.99	0.15	93.73	0.19	89.43	0.13	91.38	0.09			93.12	0.13	95.28	0.35	95.01	0.00	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.4253853604
93.14	0.15	93.73	0.00	89.56	0.13	91.38	0.00			93.13	0.01	95.28	0.00	95.76	0.75	/workspace/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.3020133050
93.29	0.15	93.73	0.00	89.61	0.05	91.38	0.00			93.13	0.00	95.28	0.00	96.58	0.82	/workspace/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.3768008806
93.43	0.14	93.74	0.01	90.00	0.38	91.39	0.01			93.57	0.44	95.28	0.00	96.58	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.1914170374
93.57	0.14	93.76	0.02	90.08	0.08	91.91	0.52			93.61	0.04	95.45	0.17	96.58	0.00	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.1673400127
93.69	0.12	93.76	0.00	90.12	0.04	91.91	0.00			93.62	0.01	95.45	0.00	97.26	0.68	/workspace/coverage/cover_reg_top/81.xbar_random.2545505157
93.80	0.12	94.04	0.28	90.37	0.26	92.07	0.17			93.62	0.00	95.45	0.00	97.26	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.249310739
93.91	0.11	94.04	0.00	90.41	0.04	92.07	0.00			93.62	0.00	95.45	0.00	97.89	0.62	/workspace/coverage/cover_reg_top/33.xbar_random_large_delays.3594022426
94.02	0.10	94.04	0.00	90.69	0.28	92.09	0.02			93.94	0.32	95.45	0.00	97.89	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.4113616961
94.11	0.10	94.04	0.00	91.28	0.58	92.09	0.00			93.94	0.00	95.45	0.00	97.89	0.00	/workspace/coverage/cover_reg_top/9.chip_tl_errors.3694576464
94.20	0.08	94.06	0.02	91.29	0.01	92.55	0.46			93.95	0.01	95.45	0.00	97.89	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.1522125858
94.28	0.08	94.10	0.04	91.33	0.04	92.92	0.37			93.98	0.03	95.45	0.00	97.90	0.01	/workspace/coverage/default/0.rom_e2e_shutdown_output.1208434112
94.35	0.07	94.10	0.00	91.33	0.00	93.36	0.44			93.98	0.00	95.45	0.00	97.90	0.00	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.4064469503
94.41	0.06	94.10	0.00	91.33	0.00	93.73	0.37			93.98	0.00	95.45	0.00	97.90	0.00	/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.1865560162
94.47	0.06	94.10	0.00	91.33	0.00	94.09	0.37			93.98	0.00	95.45	0.00	97.90	0.00	/workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.713738533
94.53	0.05	94.14	0.04	91.35	0.03	94.12	0.03			94.02	0.04	95.63	0.17	97.91	0.01	/workspace/coverage/default/0.chip_sw_all_escalation_resets.4269138836
94.58	0.05	94.20	0.07	91.51	0.15	94.12	0.00			94.12	0.10	95.63	0.00	97.91	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_retention.3941573832
94.63	0.05	94.20	0.00	91.79	0.29	94.12	0.00			94.12	0.00	95.63	0.00	97.91	0.00	/workspace/coverage/cover_reg_top/12.chip_tl_errors.515998943
94.68	0.05	94.20	0.00	91.82	0.02	94.12	0.00			94.14	0.02	95.63	0.00	98.14	0.23	/workspace/coverage/cover_reg_top/19.xbar_stress_all_with_rand_reset.1868026778
94.72	0.04	94.20	0.00	91.85	0.04	94.12	0.00			94.15	0.02	95.63	0.00	98.34	0.20	/workspace/coverage/cover_reg_top/57.xbar_stress_all_with_rand_reset.3214078461
94.76	0.04	94.21	0.01	91.87	0.01	94.12	0.00			94.18	0.02	95.80	0.17	98.36	0.01	/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.2555379610
94.79	0.04	94.22	0.01	91.88	0.01	94.13	0.01			94.19	0.01	95.98	0.17	98.37	0.01	/workspace/coverage/default/93.chip_sw_all_escalation_resets.2083789278
94.83	0.04	94.22	0.01	91.90	0.02	94.13	0.00			94.20	0.01	96.15	0.17	98.38	0.01	/workspace/coverage/default/97.chip_sw_all_escalation_resets.2067918102
94.87	0.04	94.23	0.01	91.91	0.01	94.14	0.01			94.20	0.01	96.33	0.17	98.39	0.01	/workspace/coverage/default/65.chip_sw_all_escalation_resets.935696120
94.90	0.04	94.23	0.00	91.91	0.00	94.17	0.04			94.20	0.00	96.50	0.17	98.39	0.00	/workspace/coverage/default/0.chip_sw_data_integrity_escalation.1752602725
94.94	0.03	94.30	0.07	91.93	0.01	94.28	0.10			94.21	0.01	96.50	0.00	98.40	0.01	/workspace/coverage/default/18.chip_sw_all_escalation_resets.1616670584
94.96	0.03	94.37	0.07	91.93	0.00	94.36	0.08			94.22	0.01	96.50	0.00	98.40	0.00	/workspace/coverage/default/2.chip_tap_straps_testunlock0.4184930767
94.99	0.03	94.37	0.00	91.93	0.00	94.52	0.16			94.22	0.00	96.50	0.00	98.40	0.00	/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.3619379947
95.02	0.03	94.37	0.00	92.00	0.07	94.52	0.00			94.22	0.00	96.50	0.00	98.48	0.08	/workspace/coverage/cover_reg_top/53.xbar_stress_all_with_rand_reset.1621186818
95.04	0.03	94.38	0.01	92.15	0.15	94.52	0.00			94.22	0.00	96.50	0.00	98.48	0.00	/workspace/coverage/cover_reg_top/15.chip_csr_rw.2422709205
95.07	0.03	94.41	0.03	92.21	0.06	94.56	0.04			94.24	0.02	96.50	0.00	98.48	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.3372391028
95.09	0.03	94.41	0.00	92.21	0.00	94.71	0.15			94.24	0.00	96.50	0.00	98.48	0.00	/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.3110246795
95.12	0.02	94.41	0.00	92.36	0.15	94.71	0.00			94.24	0.00	96.50	0.00	98.48	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_0.1608488463
95.14	0.02	94.47	0.07	92.41	0.05	94.71	0.00			94.27	0.02	96.50	0.00	98.48	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.1289126215
95.16	0.02	94.50	0.03	92.46	0.05	94.73	0.02			94.30	0.03	96.50	0.00	98.48	0.00	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.726794242
95.19	0.02	94.57	0.07	92.51	0.05	94.73	0.00			94.32	0.02	96.50	0.00	98.48	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.1861744926
95.21	0.02	94.63	0.07	92.55	0.05	94.73	0.00			94.33	0.02	96.50	0.00	98.48	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_wake.87970571
95.23	0.02	94.63	0.00	92.64	0.09	94.73	0.00			94.33	0.00	96.50	0.00	98.52	0.04	/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.2645989797
95.25	0.02	94.66	0.03	92.70	0.06	94.74	0.01			94.36	0.02	96.50	0.00	98.52	0.00	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.1096861788
95.27	0.02	94.66	0.00	92.80	0.10	94.74	0.00			94.36	0.00	96.50	0.00	98.53	0.01	/workspace/coverage/cover_reg_top/4.chip_tl_errors.4192811346
95.28	0.02	94.66	0.00	92.80	0.00	94.84	0.10			94.36	0.00	96.50	0.00	98.53	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.3843433762
95.30	0.02	94.66	0.00	92.90	0.09	94.84	0.00			94.36	0.00	96.50	0.00	98.53	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_20.4197806836
95.31	0.01	94.66	0.00	92.98	0.08	94.84	0.00			94.36	0.00	96.50	0.00	98.53	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_0.3363420717
95.33	0.01	94.66	0.00	92.98	0.00	94.92	0.08			94.36	0.00	96.50	0.00	98.53	0.00	/workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.2181034676
95.34	0.01	94.68	0.02	93.01	0.04	94.94	0.02			94.36	0.00	96.50	0.00	98.53	0.00	/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.2484187047
95.35	0.01	94.68	0.00	93.01	0.00	95.01	0.07			94.36	0.00	96.50	0.00	98.53	0.00	/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.623590338
95.36	0.01	94.68	0.00	93.08	0.07	95.01	0.00			94.36	0.00	96.50	0.00	98.53	0.00	/workspace/coverage/cover_reg_top/16.chip_tl_errors.3894936363
95.37	0.01	94.68	0.00	93.08	0.00	95.01	0.00			94.36	0.00	96.50	0.00	98.60	0.07	/workspace/coverage/cover_reg_top/54.xbar_stress_all_with_rand_reset.2512050963
95.38	0.01	94.68	0.00	93.11	0.02	95.05	0.04			94.36	0.00	96.50	0.00	98.60	0.00	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.1701776899
95.39	0.01	94.71	0.02	93.11	0.01	95.06	0.01			94.37	0.02	96.50	0.00	98.60	0.00	/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.2433446859
95.40	0.01	94.71	0.00	93.12	0.01	95.06	0.00			94.37	0.00	96.50	0.00	98.65	0.05	/workspace/coverage/cover_reg_top/99.xbar_access_same_device_slow_rsp.1601233476
95.41	0.01	94.72	0.02	93.12	0.01	95.07	0.01			94.39	0.02	96.50	0.00	98.65	0.00	/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.4098777055
95.42	0.01	94.75	0.02	93.13	0.01	95.07	0.01			94.41	0.02	96.50	0.00	98.65	0.00	/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.826224826
95.43	0.01	94.75	0.00	93.18	0.05	95.07	0.00			94.41	0.00	96.50	0.00	98.65	0.00	/workspace/coverage/cover_reg_top/27.chip_tl_errors.2797734331
95.43	0.01	94.75	0.00	93.20	0.02	95.07	0.00			94.42	0.02	96.50	0.00	98.66	0.01	/workspace/coverage/cover_reg_top/21.xbar_stress_all_with_rand_reset.505396960
95.44	0.01	94.77	0.02	93.20	0.00	95.10	0.03			94.42	0.00	96.50	0.00	98.66	0.00	/workspace/coverage/default/2.chip_sw_power_idle_load.3122694461
95.45	0.01	94.77	0.00	93.25	0.05	95.10	0.00			94.42	0.00	96.50	0.00	98.66	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_20.1990083259
95.46	0.01	94.77	0.00	93.25	0.00	95.14	0.04			94.42	0.00	96.50	0.00	98.66	0.00	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.1323755401
95.46	0.01	94.77	0.00	93.25	0.00	95.18	0.04			94.42	0.00	96.50	0.00	98.66	0.00	/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.859874560
95.47	0.01	94.77	0.00	93.25	0.01	95.21	0.03			94.42	0.00	96.50	0.00	98.66	0.00	/workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.1655002521
95.48	0.01	94.77	0.00	93.29	0.04	95.21	0.00			94.42	0.00	96.50	0.00	98.66	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_10.1375551718
95.48	0.01	94.77	0.00	93.29	0.00	95.21	0.00			94.42	0.00	96.50	0.00	98.70	0.04	/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.856527861
95.49	0.01	94.77	0.00	93.29	0.00	95.21	0.00			94.42	0.00	96.50	0.00	98.73	0.04	/workspace/coverage/cover_reg_top/44.xbar_stress_all_with_reset_error.4023125981
95.49	0.01	94.77	0.01	93.31	0.03	95.21	0.00			94.42	0.00	96.50	0.00	98.73	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.3088996687
95.50	0.01	94.77	0.00	93.33	0.02	95.21	0.00			94.42	0.00	96.50	0.00	98.74	0.01	/workspace/coverage/cover_reg_top/45.xbar_stress_all_with_reset_error.2184175102
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95.51	0.01	94.77	0.00	93.39	0.03	95.21	0.00			94.42	0.00	96.50	0.00	98.74	0.00	/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.1876021761
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95.52	0.01	94.77	0.00	93.40	0.00	95.27	0.01			94.42	0.00	96.50	0.00	98.75	0.01	/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.3090898773
95.52	0.01	94.77	0.00	93.40	0.00	95.27	0.00			94.42	0.00	96.50	0.00	98.78	0.02	/workspace/coverage/cover_reg_top/98.xbar_stress_all_with_rand_reset.3499910894
95.53	0.01	94.77	0.00	93.40	0.00	95.30	0.02			94.42	0.00	96.50	0.00	98.78	0.00	/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.3180722724
95.53	0.01	94.77	0.00	93.42	0.02	95.30	0.00			94.42	0.00	96.50	0.00	98.78	0.00	/workspace/coverage/cover_reg_top/41.xbar_stress_all_with_rand_reset.626050827
95.54	0.01	94.77	0.00	93.43	0.01	95.30	0.01			94.42	0.00	96.50	0.00	98.78	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.3210773593
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95.54	0.01	94.77	0.00	93.45	0.01	95.30	0.00			94.42	0.00	96.50	0.00	98.80	0.01	/workspace/coverage/default/36.chip_sw_all_escalation_resets.523979604
95.55	0.01	94.77	0.00	93.45	0.00	95.31	0.01			94.42	0.00	96.50	0.00	98.81	0.01	/workspace/coverage/default/20.chip_sw_all_escalation_resets.3643864296
95.55	0.01	94.77	0.00	93.45	0.00	95.33	0.02			94.42	0.00	96.50	0.00	98.81	0.00	/workspace/coverage/default/0.chip_sw_usbdev_config_host.1778771691
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95.56	0.01	94.77	0.01	93.50	0.01	95.33	0.00			94.42	0.00	96.50	0.00	98.81	0.00	/workspace/coverage/cover_reg_top/18.chip_same_csr_outstanding.1214178401
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95.57	0.01	94.79	0.01	93.52	0.01	95.36	0.00			94.42	0.00	96.50	0.00	98.81	0.00	/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.4074293559
95.57	0.01	94.79	0.00	93.52	0.00	95.37	0.01			94.42	0.00	96.50	0.00	98.83	0.01	/workspace/coverage/default/92.chip_sw_all_escalation_resets.445554789
95.57	0.01	94.79	0.00	93.52	0.00	95.38	0.01			94.42	0.00	96.50	0.00	98.83	0.00	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.754525095
95.58	0.01	94.81	0.01	93.52	0.00	95.38	0.00			94.42	0.00	96.50	0.00	98.83	0.00	/workspace/coverage/default/0.chip_sw_pattgen_ios.3149441283
95.58	0.01	94.81	0.00	93.52	0.01	95.39	0.01			94.42	0.00	96.50	0.00	98.83	0.00	/workspace/coverage/default/0.chip_sw_sensor_ctrl_status.2300271935
95.58	0.01	94.81	0.00	93.52	0.00	95.39	0.01			94.43	0.01	96.50	0.00	98.83	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.703687564
95.58	0.01	94.81	0.00	93.52	0.00	95.39	0.00			94.43	0.00	96.50	0.00	98.84	0.01	/workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.3217331982
95.58	0.01	94.81	0.00	93.52	0.00	95.39	0.00			94.43	0.00	96.50	0.00	98.85	0.01	/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.2991548972
95.59	0.01	94.81	0.00	93.52	0.00	95.39	0.00			94.43	0.00	96.50	0.00	98.86	0.01	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.2053207371
95.59	0.01	94.81	0.00	93.52	0.00	95.39	0.00			94.43	0.00	96.50	0.00	98.87	0.01	/workspace/coverage/default/1.chip_sw_all_escalation_resets.1169126075
95.59	0.01	94.81	0.00	93.52	0.00	95.39	0.00			94.43	0.00	96.50	0.00	98.88	0.01	/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.4093599863
95.59	0.01	94.81	0.00	93.52	0.00	95.39	0.00			94.43	0.00	96.50	0.00	98.90	0.01	/workspace/coverage/default/10.chip_sw_all_escalation_resets.1333707838
95.59	0.01	94.81	0.00	93.52	0.00	95.39	0.00			94.43	0.00	96.50	0.00	98.91	0.01	/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.2104253004
95.60	0.01	94.81	0.00	93.52	0.00	95.39	0.00			94.43	0.00	96.50	0.00	98.92	0.01	/workspace/coverage/default/11.chip_sw_all_escalation_resets.3009364483
95.60	0.01	94.81	0.00	93.52	0.00	95.39	0.00			94.43	0.00	96.50	0.00	98.93	0.01	/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.3497270578
95.60	0.01	94.81	0.00	93.52	0.00	95.39	0.00			94.43	0.00	96.50	0.00	98.94	0.01	/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.2659579422
95.60	0.01	94.81	0.00	93.52	0.00	95.39	0.00			94.43	0.00	96.50	0.00	98.95	0.01	/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.801081931
95.60	0.01	94.81	0.00	93.52	0.00	95.39	0.00			94.43	0.00	96.50	0.00	98.97	0.01	/workspace/coverage/default/15.chip_sw_all_escalation_resets.1076969925
95.61	0.01	94.81	0.00	93.52	0.00	95.39	0.00			94.43	0.00	96.50	0.00	98.98	0.01	/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.1517507626
95.61	0.01	94.81	0.00	93.52	0.00	95.39	0.00			94.43	0.00	96.50	0.00	98.99	0.01	/workspace/coverage/default/16.chip_sw_all_escalation_resets.451181274
95.61	0.01	94.81	0.00	93.52	0.00	95.39	0.00			94.43	0.00	96.50	0.00	99.00	0.01	/workspace/coverage/default/17.chip_sw_all_escalation_resets.2675228507
95.61	0.01	94.81	0.00	93.52	0.00	95.39	0.00			94.43	0.00	96.50	0.00	99.01	0.01	/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.3214717858
95.61	0.01	94.81	0.00	93.52	0.00	95.39	0.00			94.43	0.00	96.50	0.00	99.02	0.01	/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.1924039220
95.62	0.01	94.81	0.00	93.52	0.00	95.39	0.00			94.43	0.00	96.50	0.00	99.04	0.01	/workspace/coverage/default/19.chip_sw_all_escalation_resets.4066335351
95.62	0.01	94.81	0.00	93.52	0.00	95.39	0.00			94.43	0.00	96.50	0.00	99.05	0.01	/workspace/coverage/default/2.chip_sw_all_escalation_resets.3007148634
95.62	0.01	94.81	0.00	93.52	0.00	95.39	0.00			94.43	0.00	96.50	0.00	99.06	0.01	/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.3831428648
95.62	0.01	94.81	0.00	93.52	0.00	95.39	0.00			94.43	0.00	96.50	0.00	99.07	0.01	/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.4076715894
95.62	0.01	94.81	0.00	93.52	0.00	95.39	0.00			94.43	0.00	96.50	0.00	99.08	0.01	/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.1112759892
95.63	0.01	94.81	0.00	93.52	0.00	95.39	0.00			94.43	0.00	96.50	0.00	99.10	0.01	/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.2784875043
95.63	0.01	94.81	0.00	93.52	0.00	95.39	0.00			94.43	0.00	96.50	0.00	99.11	0.01	/workspace/coverage/default/24.chip_sw_all_escalation_resets.2200597994
95.63	0.01	94.81	0.00	93.52	0.00	95.39	0.00			94.43	0.00	96.50	0.00	99.12	0.01	/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.4262084171
95.63	0.01	94.81	0.00	93.52	0.00	95.39	0.00			94.43	0.00	96.50	0.00	99.13	0.01	/workspace/coverage/default/25.chip_sw_all_escalation_resets.2187685239
95.63	0.01	94.81	0.00	93.52	0.00	95.39	0.00			94.43	0.00	96.50	0.00	99.14	0.01	/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.4248988881
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95.64	0.01	94.81	0.00	93.52	0.00	95.39	0.00			94.43	0.00	96.50	0.00	99.17	0.01	/workspace/coverage/default/27.chip_sw_all_escalation_resets.1789164990
95.64	0.01	94.81	0.00	93.52	0.00	95.39	0.00			94.43	0.00	96.50	0.00	99.18	0.01	/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.1450858103
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95.64	0.01	94.81	0.00	93.52	0.00	95.39	0.00			94.43	0.00	96.50	0.00	99.20	0.01	/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.4102012923
95.65	0.01	94.81	0.00	93.52	0.00	95.39	0.00			94.43	0.00	96.50	0.00	99.21	0.01	/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.282033135
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95.69	0.01	94.81	0.00	93.52	0.00	95.39	0.00			94.43	0.00	96.50	0.00	99.49	0.01	/workspace/coverage/default/69.chip_sw_all_escalation_resets.1355815657
95.69	0.01	94.81	0.00	93.52	0.00	95.39	0.00			94.43	0.00	96.50	0.00	99.51	0.01	/workspace/coverage/default/72.chip_sw_all_escalation_resets.554224293
95.70	0.01	94.81	0.00	93.52	0.00	95.39	0.00			94.43	0.00	96.50	0.00	99.52	0.01	/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.1540908108
95.70	0.01	94.81	0.00	93.52	0.00	95.39	0.00			94.43	0.00	96.50	0.00	99.53	0.01	/workspace/coverage/default/75.chip_sw_all_escalation_resets.3955784507
95.70	0.01	94.81	0.00	93.52	0.00	95.39	0.00			94.43	0.00	96.50	0.00	99.54	0.01	/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.2881568121
95.70	0.01	94.81	0.00	93.52	0.00	95.39	0.00			94.43	0.00	96.50	0.00	99.55	0.01	/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.2724003566
95.70	0.01	94.81	0.00	93.52	0.00	95.39	0.00			94.43	0.00	96.50	0.00	99.57	0.01	/workspace/coverage/default/86.chip_sw_all_escalation_resets.1298756101
95.71	0.01	94.81	0.00	93.52	0.00	95.39	0.00			94.43	0.00	96.50	0.00	99.58	0.01	/workspace/coverage/default/9.chip_sw_all_escalation_resets.3908901348
95.71	0.01	94.81	0.00	93.54	0.01	95.39	0.00			94.43	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/10.xbar_access_same_device.1854157709
95.71	0.01	94.81	0.00	93.55	0.01	95.39	0.00			94.43	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/77.xbar_stress_all.3036482362
95.71	0.01	94.81	0.00	93.56	0.01	95.39	0.00			94.43	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_entropy_src_csrng.2408830005
95.71	0.01	94.81	0.00	93.57	0.01	95.39	0.00			94.43	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.751330141
95.72	0.01	94.81	0.00	93.58	0.01	95.39	0.00			94.43	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_10.2499899609
95.72	0.01	94.81	0.01	93.58	0.00	95.40	0.01			94.43	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/default/23.chip_sw_all_escalation_resets.1283228793
95.72	0.01	94.82	0.01	93.58	0.00	95.40	0.00			94.43	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/default/0.chip_jtag_csr_rw.3686159517
95.72	0.01	94.82	0.00	93.58	0.00	95.41	0.01			94.43	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.3945946148
95.72	0.01	94.82	0.00	93.58	0.00	95.42	0.01			94.43	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2097469035
95.72	0.01	94.82	0.00	93.58	0.00	95.43	0.01			94.43	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.333100968
95.72	0.01	94.82	0.00	93.58	0.00	95.44	0.01			94.43	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.2655198039
95.73	0.01	94.82	0.00	93.58	0.00	95.44	0.00			94.44	0.01	96.50	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.516219829
95.73	0.01	94.82	0.00	93.58	0.00	95.44	0.00			94.45	0.01	96.50	0.00	99.58	0.00	/workspace/coverage/default/1.chip_tap_straps_dev.4071515239
95.73	0.01	94.82	0.01	93.58	0.00	95.44	0.01			94.45	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.1695388805
95.73	0.01	94.82	0.00	93.58	0.01	95.44	0.00			94.45	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.1741408603
95.73	0.01	94.82	0.00	93.59	0.01	95.44	0.00			94.45	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/13.chip_tl_errors.4124186106
95.73	0.01	94.82	0.00	93.60	0.01	95.44	0.00			94.45	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2192459983
95.73	0.01	94.82	0.00	93.60	0.00	95.45	0.01			94.45	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3933140904
95.73	0.01	94.82	0.00	93.60	0.00	95.46	0.01			94.45	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.70473614
95.74	0.01	94.82	0.00	93.60	0.00	95.46	0.01			94.45	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.3600988114
95.74	0.01	94.83	0.01	93.60	0.01	95.46	0.00			94.45	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.3960346663
95.74	0.01	94.83	0.00	93.60	0.00	95.47	0.01			94.45	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.1469012871
95.74	0.01	94.83	0.00	93.60	0.00	95.47	0.01			94.45	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_hmac_enc.2551461339
95.74	0.01	94.83	0.00	93.60	0.00	95.48	0.01			94.45	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2473978642
95.74	0.01	94.83	0.00	93.60	0.00	95.48	0.01			94.45	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/default/1.chip_sw_flash_init.1970709030
95.74	0.01	94.83	0.00	93.61	0.01	95.48	0.00			94.45	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/0.chip_csr_rw.3101941403
95.74	0.01	94.83	0.00	93.61	0.01	95.48	0.00			94.45	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/0.chip_tl_errors.179736807
95.74	0.01	94.83	0.00	93.61	0.01	95.48	0.00			94.45	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.3180958304
95.74	0.01	94.83	0.00	93.62	0.01	95.48	0.00			94.45	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/30.xbar_stress_all_with_reset_error.1174316480
95.74	0.01	94.83	0.00	93.62	0.01	95.48	0.00			94.45	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/35.xbar_error_and_unmapped_addr.1811317476
95.74	0.01	94.83	0.00	93.62	0.01	95.48	0.00			94.45	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/43.xbar_stress_all_with_reset_error.251508013
95.74	0.01	94.83	0.00	93.63	0.01	95.48	0.00			94.45	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/49.xbar_error_random.1799036575
95.75	0.01	94.83	0.00	93.63	0.01	95.48	0.00			94.45	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/64.xbar_stress_all_with_reset_error.3434330403
95.75	0.01	94.83	0.00	93.63	0.01	95.48	0.00			94.45	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.910701271
95.75	0.01	94.83	0.00	93.64	0.01	95.48	0.00			94.45	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.923294438
95.75	0.01	94.83	0.01	93.64	0.00	95.48	0.00			94.45	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.2043148561
95.75	0.01	94.83	0.01	93.64	0.00	95.48	0.00			94.45	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.1962679892
95.75	0.01	94.83	0.00	93.64	0.00	95.49	0.01			94.45	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_edn_boot_mode.1099100752
95.75	0.01	94.83	0.00	93.64	0.00	95.49	0.01			94.45	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.564970179
95.75	0.01	94.83	0.00	93.64	0.00	95.49	0.01			94.45	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3378609930
95.75	0.01	94.83	0.00	93.64	0.00	95.49	0.01			94.45	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.22677397
95.75	0.01	94.83	0.00	93.64	0.00	95.49	0.01			94.45	0.00	96.50	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.3267112447

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.589764283
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.2376271587
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.3478383901
/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.2651600787
/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.3052125737
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.4203316248
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.4279710329
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.3664271290
/workspace/coverage/cover_reg_top/0.xbar_error_random.2621682122
/workspace/coverage/cover_reg_top/0.xbar_random.1522663826
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.2789523397
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.3795944751
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.3212104472
/workspace/coverage/cover_reg_top/0.xbar_same_source.914715168
/workspace/coverage/cover_reg_top/0.xbar_smoke.1436497036
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.175094729
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.848490938
/workspace/coverage/cover_reg_top/0.xbar_stress_all.2139061003
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.217907100
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.1694591878
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.4064101823
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.1303429523
/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.3405865714
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.1299081456
/workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.1080821108
/workspace/coverage/cover_reg_top/1.chip_csr_rw.2545996701
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.4091316981
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.3227620983
/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.1269762908
/workspace/coverage/cover_reg_top/1.chip_tl_errors.1090157446
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.641197625
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.661266326
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.384956403
/workspace/coverage/cover_reg_top/1.xbar_error_random.1383395201
/workspace/coverage/cover_reg_top/1.xbar_random.4144819174
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.1005306893
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.3376251563
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.3574513056
/workspace/coverage/cover_reg_top/1.xbar_same_source.3722428837
/workspace/coverage/cover_reg_top/1.xbar_smoke.2225611720
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.885999591
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.189244287
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.2697545584
/workspace/coverage/cover_reg_top/1.xbar_stress_all.4282166618
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.4267336290
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.2137791443
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.1814087801
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.3570416841
/workspace/coverage/cover_reg_top/10.chip_csr_rw.597672205
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.28000282
/workspace/coverage/cover_reg_top/10.chip_tl_errors.1775036873
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.3035662062
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.1664750615
/workspace/coverage/cover_reg_top/10.xbar_error_random.1234065405
/workspace/coverage/cover_reg_top/10.xbar_random.1673978750
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.2861731384
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.1806634643
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.1158703424
/workspace/coverage/cover_reg_top/10.xbar_same_source.3217504373
/workspace/coverage/cover_reg_top/10.xbar_smoke.4130628424
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.491594741
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.3984597639
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.2199715842
/workspace/coverage/cover_reg_top/10.xbar_stress_all.4151873490
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.449889627
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.4004538562
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.1251380784
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.1624694722
/workspace/coverage/cover_reg_top/11.chip_csr_rw.2154359554
/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.812132510
/workspace/coverage/cover_reg_top/11.chip_tl_errors.3233136794
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.235280533
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.1922982400
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.3360575443
/workspace/coverage/cover_reg_top/11.xbar_error_random.2156402925
/workspace/coverage/cover_reg_top/11.xbar_random.2660373510
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.3654378737
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.1992790602
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.4161002150
/workspace/coverage/cover_reg_top/11.xbar_same_source.3678147874
/workspace/coverage/cover_reg_top/11.xbar_smoke.1365559919
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.1667488481
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.3062564795
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.3966166668
/workspace/coverage/cover_reg_top/11.xbar_stress_all.2071524580
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.3965360037
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.1642006178
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.4079375635
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.1066815903
/workspace/coverage/cover_reg_top/12.chip_csr_rw.108421783
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.1249802128
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.4018170283
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.875504402
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.1469579358
/workspace/coverage/cover_reg_top/12.xbar_error_random.359005935
/workspace/coverage/cover_reg_top/12.xbar_random.2424711953
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.169783261
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.1740660790
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.3177262572
/workspace/coverage/cover_reg_top/12.xbar_same_source.708228879
/workspace/coverage/cover_reg_top/12.xbar_smoke.210884003
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.12817371
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.1269123527
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.865626301
/workspace/coverage/cover_reg_top/12.xbar_stress_all.388304941
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.1159891070
/workspace/coverage/cover_reg_top/13.chip_csr_rw.3046476439
/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.2534137268
/workspace/coverage/cover_reg_top/13.xbar_access_same_device.1761881754
/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.822528548
/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.760286837
/workspace/coverage/cover_reg_top/13.xbar_error_random.1372017272
/workspace/coverage/cover_reg_top/13.xbar_random.1333262277
/workspace/coverage/cover_reg_top/13.xbar_random_large_delays.2186337426
/workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.2653162250
/workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.2542396987
/workspace/coverage/cover_reg_top/13.xbar_same_source.758777916
/workspace/coverage/cover_reg_top/13.xbar_smoke.3934694463
/workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.2941020934
/workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.33738476
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/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.3311908551
/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.2286557265
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/workspace/coverage/default/30.chip_sw_all_escalation_resets.3482133127
/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.3774721774
/workspace/coverage/default/32.chip_sw_all_escalation_resets.3125964957
/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.4028427642
/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.3801695693
/workspace/coverage/default/34.chip_sw_all_escalation_resets.4154273911
/workspace/coverage/default/35.chip_sw_all_escalation_resets.3498854795
/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.1935912925
/workspace/coverage/default/37.chip_sw_all_escalation_resets.3917873094
/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.147735382
/workspace/coverage/default/38.chip_sw_all_escalation_resets.3258585218
/workspace/coverage/default/39.chip_sw_all_escalation_resets.973032838
/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.678547827
/workspace/coverage/default/4.chip_sw_all_escalation_resets.3457073078
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.2060695769
/workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.4132843032
/workspace/coverage/default/4.chip_sw_data_integrity_escalation.2714587650
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.3419156168
/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.2223818426
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.1326475091
/workspace/coverage/default/4.chip_sw_uart_tx_rx.1050443929
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.492123914
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1915322655
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.804976900
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.621455279
/workspace/coverage/default/4.chip_tap_straps_dev.2281515543
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/workspace/coverage/default/4.chip_tap_straps_rma.4176438670
/workspace/coverage/default/4.chip_tap_straps_testunlock0.986436204
/workspace/coverage/default/40.chip_sw_all_escalation_resets.2015607371
/workspace/coverage/default/42.chip_sw_all_escalation_resets.3949161104
/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.3813461047
/workspace/coverage/default/43.chip_sw_all_escalation_resets.3132831980
/workspace/coverage/default/44.chip_sw_all_escalation_resets.2292578365
/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.1680190914
/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.741585592
/workspace/coverage/default/46.chip_sw_all_escalation_resets.3242776990
/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.1399822987
/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.2238373834
/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.78786779
/workspace/coverage/default/5.chip_sw_all_escalation_resets.3260455733
/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.826803030
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.163651390
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.3390374150
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.964976370
/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.2017235286
/workspace/coverage/default/50.chip_sw_all_escalation_resets.2272005459
/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.2986947521
/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.1547394327
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.2912614977
/workspace/coverage/default/53.chip_sw_all_escalation_resets.363272107
/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.2928880791
/workspace/coverage/default/54.chip_sw_all_escalation_resets.688906429
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.1194666612
/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.254021553
/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.2348462190
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.1134044128
/workspace/coverage/default/58.chip_sw_all_escalation_resets.3689480737
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.1449908731
/workspace/coverage/default/59.chip_sw_all_escalation_resets.1590314525
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.557381508
/workspace/coverage/default/6.chip_sw_all_escalation_resets.1083754578
/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.2602152225
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.2943007542
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.1514199604
/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.2038506418
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.2239261406
/workspace/coverage/default/61.chip_sw_all_escalation_resets.2218905201
/workspace/coverage/default/62.chip_sw_all_escalation_resets.3176104466
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.726740827
/workspace/coverage/default/63.chip_sw_all_escalation_resets.1908160936
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.886341697
/workspace/coverage/default/64.chip_sw_all_escalation_resets.3618167308
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.3948318402
/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.3130045014
/workspace/coverage/default/66.chip_sw_all_escalation_resets.1327890483
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.2885521991
/workspace/coverage/default/67.chip_sw_all_escalation_resets.2709118958
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.886793557
/workspace/coverage/default/68.chip_sw_all_escalation_resets.218493408
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.2549077102
/workspace/coverage/default/7.chip_sw_all_escalation_resets.1824658218
/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.3100536946
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.2896039624
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.4015596906
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.1068829623
/workspace/coverage/default/70.chip_sw_all_escalation_resets.1584681674
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.1023183922
/workspace/coverage/default/71.chip_sw_all_escalation_resets.2004898726
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.387196279
/workspace/coverage/default/73.chip_sw_all_escalation_resets.627336024
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.1316188955
/workspace/coverage/default/74.chip_sw_all_escalation_resets.3117294672
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.3400737153
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.4125966151
/workspace/coverage/default/76.chip_sw_all_escalation_resets.673784049
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.952384877
/workspace/coverage/default/77.chip_sw_all_escalation_resets.70501271
/workspace/coverage/default/78.chip_sw_all_escalation_resets.3323666522
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.1336840075
/workspace/coverage/default/79.chip_sw_all_escalation_resets.132907558
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.1655953858
/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.2412067749
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.963353204
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.981045897
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.3329409549
/workspace/coverage/default/80.chip_sw_all_escalation_resets.1657846773
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.3971957216
/workspace/coverage/default/81.chip_sw_all_escalation_resets.1672467001
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.4191389190
/workspace/coverage/default/83.chip_sw_all_escalation_resets.1473204814
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.3923876429
/workspace/coverage/default/84.chip_sw_all_escalation_resets.4192263661
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.688467049
/workspace/coverage/default/85.chip_sw_all_escalation_resets.3568371284
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.3321046131
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.3860103138
/workspace/coverage/default/87.chip_sw_all_escalation_resets.3357630389
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.3084366197
/workspace/coverage/default/88.chip_sw_all_escalation_resets.4219984026
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.2080784836
/workspace/coverage/default/89.chip_sw_all_escalation_resets.3696136273
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.128378108
/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.1803891702
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.4146640101
/workspace/coverage/default/90.chip_sw_all_escalation_resets.1501175365
/workspace/coverage/default/91.chip_sw_all_escalation_resets.3418490160
/workspace/coverage/default/94.chip_sw_all_escalation_resets.180862568
/workspace/coverage/default/95.chip_sw_all_escalation_resets.3746165677
/workspace/coverage/default/96.chip_sw_all_escalation_resets.2792572926
/workspace/coverage/default/98.chip_sw_all_escalation_resets.2773482232
/workspace/coverage/default/99.chip_sw_all_escalation_resets.1697776852
/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.68840577
/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.3564950322
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.1168997868
/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.3241670732
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.689482424
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.1630394483
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.3368590715
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.972921490

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Total test records in report: 2875

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T4	/workspace/coverage/default/0.chip_sw_kmac_mode_cshake.2261191651			Jun 02 03:43:50 PM PDT 24	Jun 02 03:48:03 PM PDT 24	2931181584 ps
T5	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.3699951732			Jun 02 03:51:07 PM PDT 24	Jun 02 05:11:53 PM PDT 24	13973993040 ps
T6	/workspace/coverage/default/0.chip_sw_clkmgr_jitter.2409444969			Jun 02 03:46:23 PM PDT 24	Jun 02 03:51:40 PM PDT 24	2558885143 ps
T18	/workspace/coverage/default/8.chip_sw_all_escalation_resets.492676843			Jun 02 04:04:34 PM PDT 24	Jun 02 04:19:44 PM PDT 24	5143968240 ps
T19	/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.4037857876			Jun 02 03:46:03 PM PDT 24	Jun 02 04:02:22 PM PDT 24	5602894528 ps
T20	/workspace/coverage/default/2.chip_sw_aon_timer_irq.1071639169			Jun 02 03:58:11 PM PDT 24	Jun 02 04:05:53 PM PDT 24	3908282118 ps
T84	/workspace/coverage/default/2.chip_sw_power_idle_load.3122694461			Jun 02 04:03:07 PM PDT 24	Jun 02 04:14:18 PM PDT 24	3513795538 ps
T46	/workspace/coverage/default/18.chip_sw_all_escalation_resets.1616670584			Jun 02 04:05:49 PM PDT 24	Jun 02 04:16:24 PM PDT 24	5513000384 ps
T47	/workspace/coverage/default/75.chip_sw_all_escalation_resets.3955784507			Jun 02 04:12:03 PM PDT 24	Jun 02 04:22:20 PM PDT 24	5052489720 ps
T63	/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.128378108			Jun 02 04:06:03 PM PDT 24	Jun 02 04:11:56 PM PDT 24	3861448298 ps
T115	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.3262129970			Jun 02 03:48:40 PM PDT 24	Jun 02 04:12:40 PM PDT 24	8133401350 ps
T21	/workspace/coverage/default/0.rom_e2e_shutdown_output.1208434112			Jun 02 03:47:46 PM PDT 24	Jun 02 04:40:49 PM PDT 24	22392934164 ps
T199	/workspace/coverage/default/2.chip_sw_kmac_smoketest.1368412069			Jun 02 04:04:51 PM PDT 24	Jun 02 04:10:05 PM PDT 24	2946847346 ps
T675	/workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.2861214916			Jun 02 03:50:33 PM PDT 24	Jun 02 03:54:52 PM PDT 24	2674024888 ps
T172	/workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.3518573439			Jun 02 04:01:28 PM PDT 24	Jun 02 04:08:58 PM PDT 24	4713592300 ps
T116	/workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.3731186717			Jun 02 03:44:13 PM PDT 24	Jun 02 03:48:20 PM PDT 24	3112235150 ps
T315	/workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.684307177			Jun 02 03:58:49 PM PDT 24	Jun 02 04:04:36 PM PDT 24	3282589000 ps
T22	/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.623590338			Jun 02 04:05:50 PM PDT 24	Jun 02 04:18:39 PM PDT 24	8657990983 ps
T176	/workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.3586505311			Jun 02 04:00:44 PM PDT 24	Jun 02 04:10:01 PM PDT 24	5108107160 ps
T58	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.2825877457			Jun 02 03:53:59 PM PDT 24	Jun 02 04:55:15 PM PDT 24	14494727904 ps
T316	/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.3090898773			Jun 02 04:07:27 PM PDT 24	Jun 02 04:14:56 PM PDT 24	3223559688 ps
T178	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.1673400127			Jun 02 03:48:02 PM PDT 24	Jun 02 03:58:32 PM PDT 24	4746264184 ps
T165	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.3539919809			Jun 02 03:46:57 PM PDT 24	Jun 02 04:58:58 PM PDT 24	14229174920 ps
T23	/workspace/coverage/default/12.chip_sw_lc_ctrl_transition.1559463777			Jun 02 04:06:03 PM PDT 24	Jun 02 04:25:40 PM PDT 24	10316783429 ps
T177	/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.345741981			Jun 02 03:58:34 PM PDT 24	Jun 02 04:07:55 PM PDT 24	7171743980 ps
T59	/workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.3703054414			Jun 02 03:57:58 PM PDT 24	Jun 02 04:28:48 PM PDT 24	25911314695 ps
T294	/workspace/coverage/default/20.chip_sw_all_escalation_resets.3643864296			Jun 02 04:10:02 PM PDT 24	Jun 02 04:21:23 PM PDT 24	4975791026 ps
T152	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.347993937			Jun 02 03:46:47 PM PDT 24	Jun 02 04:04:24 PM PDT 24	7083152760 ps
T118	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.1701776899			Jun 02 03:43:52 PM PDT 24	Jun 02 04:31:48 PM PDT 24	13321265578 ps
T295	/workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.1762871239			Jun 02 03:44:39 PM PDT 24	Jun 02 03:55:08 PM PDT 24	5455446540 ps
T296	/workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.508150936			Jun 02 03:58:01 PM PDT 24	Jun 02 04:09:42 PM PDT 24	4868089080 ps
T357	/workspace/coverage/default/51.chip_sw_all_escalation_resets.2817581926			Jun 02 04:10:44 PM PDT 24	Jun 02 04:20:17 PM PDT 24	4414539070 ps
T169	/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.3702843362			Jun 02 03:42:51 PM PDT 24	Jun 02 05:05:18 PM PDT 24	43278423430 ps
T60	/workspace/coverage/default/0.chip_sw_alert_test.3737330000			Jun 02 03:45:06 PM PDT 24	Jun 02 03:49:00 PM PDT 24	2608966996 ps
T351	/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.688467049			Jun 02 04:13:41 PM PDT 24	Jun 02 04:20:06 PM PDT 24	3773350044 ps
T187	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.754525095			Jun 02 03:42:53 PM PDT 24	Jun 02 03:54:47 PM PDT 24	9893669353 ps
T381	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.4265991002			Jun 02 03:51:07 PM PDT 24	Jun 02 05:00:08 PM PDT 24	13747837908 ps
T122	/workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.713738533			Jun 02 03:49:07 PM PDT 24	Jun 02 04:00:02 PM PDT 24	5877115226 ps
T382	/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.282033135			Jun 02 04:04:43 PM PDT 24	Jun 02 04:10:45 PM PDT 24	3383074792 ps
T383	/workspace/coverage/default/2.chip_sw_example_manufacturer.2762375162			Jun 02 03:53:03 PM PDT 24	Jun 02 03:55:15 PM PDT 24	1900118860 ps
T384	/workspace/coverage/default/1.chip_sw_kmac_entropy.1180884139			Jun 02 03:43:31 PM PDT 24	Jun 02 03:48:03 PM PDT 24	3060384092 ps
T121	/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.751330141			Jun 02 03:49:01 PM PDT 24	Jun 02 03:55:18 PM PDT 24	6180329064 ps
T356	/workspace/coverage/default/92.chip_sw_all_escalation_resets.445554789			Jun 02 04:12:49 PM PDT 24	Jun 02 04:24:20 PM PDT 24	5565041518 ps
T125	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation.2706562920			Jun 02 04:00:15 PM PDT 24	Jun 02 04:40:35 PM PDT 24	10695725964 ps
T117	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3544473255			Jun 02 03:48:08 PM PDT 24	Jun 02 03:56:19 PM PDT 24	4245449498 ps
T247	/workspace/coverage/default/2.chip_sw_clkmgr_off_peri.3805864968			Jun 02 04:00:40 PM PDT 24	Jun 02 04:25:28 PM PDT 24	11430218520 ps
T30	/workspace/coverage/default/13.chip_sw_uart_rand_baudrate.404563538			Jun 02 04:06:43 PM PDT 24	Jun 02 04:18:30 PM PDT 24	4052660910 ps
T358	/workspace/coverage/default/36.chip_sw_all_escalation_resets.523979604			Jun 02 04:08:17 PM PDT 24	Jun 02 04:18:45 PM PDT 24	4687854734 ps
T147	/workspace/coverage/default/0.chip_sw_otbn_smoketest.3447555879			Jun 02 03:44:50 PM PDT 24	Jun 02 04:29:22 PM PDT 24	10776781236 ps
T80	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.3296219449			Jun 02 03:44:07 PM PDT 24	Jun 02 04:07:18 PM PDT 24	10741864024 ps
T226	/workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.3426167297			Jun 02 03:44:36 PM PDT 24	Jun 02 03:58:53 PM PDT 24	5754260026 ps
T262	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.3502794931			Jun 02 03:45:37 PM PDT 24	Jun 02 04:08:26 PM PDT 24	6282692590 ps
T419	/workspace/coverage/default/0.rom_e2e_smoke.1470522367			Jun 02 03:48:44 PM PDT 24	Jun 02 04:44:16 PM PDT 24	14430398600 ps
T350	/workspace/coverage/default/1.chip_sw_flash_crash_alert.3936237876			Jun 02 03:51:43 PM PDT 24	Jun 02 04:04:45 PM PDT 24	5147501882 ps
T110	/workspace/coverage/default/2.chip_sw_power_sleep_load.1470540282			Jun 02 04:06:19 PM PDT 24	Jun 02 04:12:15 PM PDT 24	4496779270 ps
T699	/workspace/coverage/default/0.chip_sw_hmac_enc_idle.3147733487			Jun 02 03:41:27 PM PDT 24	Jun 02 03:45:22 PM PDT 24	3168271880 ps
T224	/workspace/coverage/default/0.chip_sw_all_escalation_resets.4269138836			Jun 02 03:44:45 PM PDT 24	Jun 02 03:54:27 PM PDT 24	5908956950 ps
T269	/workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.2277515651			Jun 02 03:44:20 PM PDT 24	Jun 02 04:01:51 PM PDT 24	5306554901 ps
T270	/workspace/coverage/default/58.chip_sw_all_escalation_resets.3689480737			Jun 02 04:11:27 PM PDT 24	Jun 02 04:22:20 PM PDT 24	5100526276 ps
T271	/workspace/coverage/default/12.chip_sw_all_escalation_resets.2753408857			Jun 02 04:05:57 PM PDT 24	Jun 02 04:13:39 PM PDT 24	5221396860 ps
T272	/workspace/coverage/default/2.rom_e2e_asm_init_dev.4018519210			Jun 02 04:08:18 PM PDT 24	Jun 02 04:58:44 PM PDT 24	13727694153 ps
T81	/workspace/coverage/default/65.chip_sw_all_escalation_resets.935696120			Jun 02 04:13:41 PM PDT 24	Jun 02 04:23:40 PM PDT 24	5545232000 ps
T92	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.1147168627			Jun 02 03:57:19 PM PDT 24	Jun 02 04:20:16 PM PDT 24	7450877400 ps
T93	/workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.491657113			Jun 02 03:43:12 PM PDT 24	Jun 02 03:51:51 PM PDT 24	7646926696 ps
T94	/workspace/coverage/default/0.chip_sw_clkmgr_smoketest.2420231435			Jun 02 03:46:28 PM PDT 24	Jun 02 03:49:27 PM PDT 24	2635002200 ps
T95	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.3117464141			Jun 02 03:43:16 PM PDT 24	Jun 02 03:50:17 PM PDT 24	3543156998 ps
T96	/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.3042008858			Jun 02 03:48:51 PM PDT 24	Jun 02 04:03:35 PM PDT 24	7714276860 ps
T97	/workspace/coverage/default/0.chip_sw_aes_idle.3697553013			Jun 02 03:44:22 PM PDT 24	Jun 02 03:49:52 PM PDT 24	2686749764 ps
T98	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.3317694140			Jun 02 03:46:39 PM PDT 24	Jun 02 05:29:31 PM PDT 24	22704075972 ps
T99	/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.3923876429			Jun 02 04:12:18 PM PDT 24	Jun 02 04:21:22 PM PDT 24	4148847120 ps
T100	/workspace/coverage/default/5.chip_sw_all_escalation_resets.3260455733			Jun 02 04:04:30 PM PDT 24	Jun 02 04:14:36 PM PDT 24	4448741400 ps
T211	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.1096861788			Jun 02 04:06:24 PM PDT 24	Jun 02 04:17:29 PM PDT 24	4515431400 ps
T674	/workspace/coverage/default/0.rom_e2e_asm_init_prod.3748496481			Jun 02 03:46:05 PM PDT 24	Jun 02 04:57:51 PM PDT 24	14458485925 ps
T368	/workspace/coverage/default/27.chip_sw_all_escalation_resets.1789164990			Jun 02 04:08:37 PM PDT 24	Jun 02 04:16:44 PM PDT 24	4503337168 ps
T170	/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.1469012871			Jun 02 03:42:44 PM PDT 24	Jun 02 05:13:24 PM PDT 24	43494565390 ps
T369	/workspace/coverage/default/55.chip_sw_all_escalation_resets.2263628271			Jun 02 04:11:24 PM PDT 24	Jun 02 04:23:27 PM PDT 24	5995253080 ps
T173	/workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.2112823617			Jun 02 03:43:36 PM PDT 24	Jun 02 03:46:15 PM PDT 24	2760687441 ps
T681	/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.2238373834			Jun 02 04:09:58 PM PDT 24	Jun 02 04:17:13 PM PDT 24	4152132008 ps
T1	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2334593133			Jun 02 03:53:12 PM PDT 24	Jun 02 03:59:45 PM PDT 24	7234752914 ps
T102	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.3154071155			Jun 02 03:57:11 PM PDT 24	Jun 02 04:08:59 PM PDT 24	3906940589 ps
T103	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2437567171			Jun 02 03:45:29 PM PDT 24	Jun 02 03:57:23 PM PDT 24	4237127800 ps
T104	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.3228413478			Jun 02 03:46:22 PM PDT 24	Jun 02 04:09:24 PM PDT 24	7273416252 ps
T50	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2004509561			Jun 02 03:44:10 PM PDT 24	Jun 02 03:50:51 PM PDT 24	4201341046 ps
T105	/workspace/coverage/default/2.chip_sw_aes_smoketest.34558682			Jun 02 04:03:19 PM PDT 24	Jun 02 04:09:09 PM PDT 24	2989192680 ps
T106	/workspace/coverage/default/0.chip_sival_flash_info_access.996879302			Jun 02 03:44:00 PM PDT 24	Jun 02 03:50:24 PM PDT 24	3638031780 ps
T107	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2706644431			Jun 02 03:43:42 PM PDT 24	Jun 02 03:53:47 PM PDT 24	5647204946 ps
T108	/workspace/coverage/default/98.chip_sw_all_escalation_resets.2773482232			Jun 02 04:13:09 PM PDT 24	Jun 02 04:23:56 PM PDT 24	4839051900 ps
T109	/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.4076715894			Jun 02 04:07:42 PM PDT 24	Jun 02 04:13:35 PM PDT 24	3455070394 ps
T186	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.2712818378			Jun 02 03:43:58 PM PDT 24	Jun 02 03:49:19 PM PDT 24	3122561391 ps
T223	/workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.721791558			Jun 02 04:00:26 PM PDT 24	Jun 02 04:46:06 PM PDT 24	30638512305 ps
T873	/workspace/coverage/default/2.chip_sw_rstmgr_smoketest.2572189889			Jun 02 04:03:52 PM PDT 24	Jun 02 04:08:00 PM PDT 24	3018057348 ps
T220	/workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.3142526885			Jun 02 03:46:55 PM PDT 24	Jun 02 04:09:35 PM PDT 24	8875654506 ps
T182	/workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.781887900			Jun 02 04:00:07 PM PDT 24	Jun 02 04:05:04 PM PDT 24	2885074376 ps
T874	/workspace/coverage/default/1.chip_sw_rstmgr_smoketest.2576234183			Jun 02 03:52:36 PM PDT 24	Jun 02 03:55:47 PM PDT 24	2422559060 ps
T796	/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.3971957216			Jun 02 04:13:00 PM PDT 24	Jun 02 04:20:07 PM PDT 24	3615671302 ps
T126	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.1896676201			Jun 02 03:47:24 PM PDT 24	Jun 02 03:56:09 PM PDT 24	5480612040 ps
T287	/workspace/coverage/default/1.chip_sw_otbn_mem_scramble.4273125429			Jun 02 03:45:05 PM PDT 24	Jun 02 03:51:30 PM PDT 24	3599063222 ps
T225	/workspace/coverage/default/81.chip_sw_all_escalation_resets.1672467001			Jun 02 04:12:01 PM PDT 24	Jun 02 04:20:54 PM PDT 24	4935835572 ps
T718	/workspace/coverage/default/35.chip_sw_all_escalation_resets.3498854795			Jun 02 04:09:45 PM PDT 24	Jun 02 04:22:57 PM PDT 24	4743148456 ps
T288	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.1189986643			Jun 02 04:00:07 PM PDT 24	Jun 02 04:12:03 PM PDT 24	4155424680 ps
T34	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.4253853604			Jun 02 03:42:52 PM PDT 24	Jun 02 04:11:41 PM PDT 24	21879221912 ps
T413	/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.3831428648			Jun 02 04:09:03 PM PDT 24	Jun 02 04:17:56 PM PDT 24	4474229054 ps
T875	/workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.1197222411			Jun 02 03:48:39 PM PDT 24	Jun 02 03:58:16 PM PDT 24	5695436968 ps
T67	/workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.1360792008			Jun 02 03:55:12 PM PDT 24	Jun 02 06:53:01 PM PDT 24	58151070873 ps
T684	/workspace/coverage/default/72.chip_sw_all_escalation_resets.554224293			Jun 02 04:11:50 PM PDT 24	Jun 02 04:22:51 PM PDT 24	5390525286 ps
T171	/workspace/coverage/default/1.chip_sw_flash_init.1970709030			Jun 02 03:42:28 PM PDT 24	Jun 02 04:14:39 PM PDT 24	17114994500 ps
T732	/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.3801695693			Jun 02 04:10:10 PM PDT 24	Jun 02 04:17:24 PM PDT 24	3010559872 ps
T335	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops.3438569108			Jun 02 03:42:15 PM PDT 24	Jun 02 03:51:00 PM PDT 24	4793941300 ps
T876	/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.770868653			Jun 02 03:57:11 PM PDT 24	Jun 02 05:00:28 PM PDT 24	14680839112 ps
T163	/workspace/coverage/default/7.chip_sw_all_escalation_resets.1824658218			Jun 02 04:05:17 PM PDT 24	Jun 02 04:13:09 PM PDT 24	5614587950 ps
T336	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.3088996687			Jun 02 03:46:58 PM PDT 24	Jun 02 03:58:26 PM PDT 24	4080397023 ps
T665	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.1695388805			Jun 02 03:45:05 PM PDT 24	Jun 02 03:56:24 PM PDT 24	8884646450 ps
T877	/workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.1860088258			Jun 02 03:48:07 PM PDT 24	Jun 02 03:56:26 PM PDT 24	3214145818 ps
T878	/workspace/coverage/default/1.chip_sw_entropy_src_kat_test.955613810			Jun 02 03:47:03 PM PDT 24	Jun 02 03:49:55 PM PDT 24	3005976880 ps
T111	/workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.779079917			Jun 02 03:48:07 PM PDT 24	Jun 02 03:56:29 PM PDT 24	17834940168 ps
T879	/workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.1247571570			Jun 02 03:44:01 PM PDT 24	Jun 02 05:10:00 PM PDT 24	27547400028 ps
T880	/workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.450723214			Jun 02 04:01:02 PM PDT 24	Jun 02 04:09:28 PM PDT 24	4235928470 ps
T685	/workspace/coverage/default/90.chip_sw_all_escalation_resets.1501175365			Jun 02 04:12:40 PM PDT 24	Jun 02 04:23:36 PM PDT 24	4498940256 ps
T2	/workspace/coverage/default/1.chip_sw_sleep_pin_retention.544318587			Jun 02 03:46:49 PM PDT 24	Jun 02 03:51:28 PM PDT 24	3394307390 ps
T228	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.1323755401			Jun 02 03:41:04 PM PDT 24	Jun 02 04:15:20 PM PDT 24	10818761094 ps
T425	/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.3321046131			Jun 02 04:12:20 PM PDT 24	Jun 02 04:19:01 PM PDT 24	3867623476 ps
T3	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.798603891			Jun 02 03:46:54 PM PDT 24	Jun 02 04:08:59 PM PDT 24	20239514942 ps
T142	/workspace/coverage/default/1.chip_sw_sensor_ctrl_status.4014078781			Jun 02 03:45:38 PM PDT 24	Jun 02 03:50:00 PM PDT 24	3248534797 ps
T159	/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.4102012923			Jun 02 04:09:38 PM PDT 24	Jun 02 04:16:00 PM PDT 24	3869579920 ps
T227	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.564970179			Jun 02 03:40:57 PM PDT 24	Jun 02 04:35:45 PM PDT 24	10602874060 ps
T426	/workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.2161448100			Jun 02 03:48:37 PM PDT 24	Jun 02 03:55:09 PM PDT 24	4291618600 ps
T213	/workspace/coverage/default/40.chip_sw_all_escalation_resets.2015607371			Jun 02 04:09:06 PM PDT 24	Jun 02 04:19:21 PM PDT 24	4994552190 ps
T273	/workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.3105383316			Jun 02 04:01:47 PM PDT 24	Jun 02 04:09:12 PM PDT 24	3254797515 ps
T881	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac.1470709985			Jun 02 04:00:29 PM PDT 24	Jun 02 04:05:51 PM PDT 24	3213625000 ps
T119	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1061222738			Jun 02 03:48:22 PM PDT 24	Jun 02 03:59:31 PM PDT 24	4452707644 ps
T154	/workspace/coverage/default/2.chip_plic_all_irqs_10.2581636583			Jun 02 04:00:30 PM PDT 24	Jun 02 04:11:02 PM PDT 24	4090379104 ps
T724	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.4147956315			Jun 02 03:59:09 PM PDT 24	Jun 02 04:05:01 PM PDT 24	3388405162 ps
T882	/workspace/coverage/default/2.chip_sw_aon_timer_smoketest.3009911955			Jun 02 04:02:57 PM PDT 24	Jun 02 04:08:11 PM PDT 24	3775326062 ps
T157	/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.1522125858			Jun 02 03:47:07 PM PDT 24	Jun 02 03:57:25 PM PDT 24	5203047896 ps
T260	/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.1400339927			Jun 02 03:59:59 PM PDT 24	Jun 02 04:46:00 PM PDT 24	11783827752 ps
T403	/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.1399822987			Jun 02 04:10:02 PM PDT 24	Jun 02 04:18:20 PM PDT 24	3631516816 ps
T229	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.2245574112			Jun 02 03:49:47 PM PDT 24	Jun 02 04:30:24 PM PDT 24	13134584740 ps
T255	/workspace/coverage/default/1.chip_sw_rv_timer_smoketest.3761884238			Jun 02 03:52:44 PM PDT 24	Jun 02 03:56:35 PM PDT 24	2659216200 ps
T32	/workspace/coverage/default/1.chip_jtag_csr_rw.1356768326			Jun 02 03:39:26 PM PDT 24	Jun 02 04:07:43 PM PDT 24	12397999950 ps
T248	/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.3358489833			Jun 02 03:50:32 PM PDT 24	Jun 02 04:20:12 PM PDT 24	14295175040 ps
T183	/workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.2700292996			Jun 02 03:46:36 PM PDT 24	Jun 02 03:54:00 PM PDT 24	3830833760 ps
T883	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.1275116837			Jun 02 03:51:01 PM PDT 24	Jun 02 04:59:14 PM PDT 24	14241067194 ps
T884	/workspace/coverage/default/0.chip_sw_example_rom.523175512			Jun 02 03:42:23 PM PDT 24	Jun 02 03:44:23 PM PDT 24	2106047914 ps
T725	/workspace/coverage/default/94.chip_sw_all_escalation_resets.180862568			Jun 02 04:12:44 PM PDT 24	Jun 02 04:25:18 PM PDT 24	4867389896 ps
T337	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.4153926532			Jun 02 03:45:15 PM PDT 24	Jun 02 03:57:19 PM PDT 24	4514795032 ps
T53	/workspace/coverage/default/0.chip_sw_spi_device_tpm.2548880538			Jun 02 03:43:02 PM PDT 24	Jun 02 03:48:52 PM PDT 24	3398252353 ps
T722	/workspace/coverage/default/0.chip_sw_ast_clk_outputs.3249622129			Jun 02 03:45:37 PM PDT 24	Jun 02 04:03:57 PM PDT 24	7611128378 ps
T123	/workspace/coverage/default/2.chip_sw_entropy_src_csrng.2697737203			Jun 02 04:00:06 PM PDT 24	Jun 02 04:29:17 PM PDT 24	6625836986 ps
T33	/workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.273916945			Jun 02 03:46:13 PM PDT 24	Jun 02 03:55:12 PM PDT 24	6020510820 ps
T68	/workspace/coverage/default/0.chip_jtag_mem_access.2541812172			Jun 02 03:33:47 PM PDT 24	Jun 02 03:57:08 PM PDT 24	13141915020 ps
T372	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2757541651			Jun 02 03:48:41 PM PDT 24	Jun 02 04:07:32 PM PDT 24	11497785749 ps
T885	/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.818282854			Jun 02 03:48:03 PM PDT 24	Jun 02 04:05:36 PM PDT 24	7235235234 ps
T886	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.3906303295			Jun 02 03:41:45 PM PDT 24	Jun 02 04:06:24 PM PDT 24	9390503712 ps
T887	/workspace/coverage/default/2.chip_sw_clkmgr_smoketest.4131589755			Jun 02 04:04:19 PM PDT 24	Jun 02 04:08:58 PM PDT 24	2451123280 ps
T56	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.2663938036			Jun 02 03:47:49 PM PDT 24	Jun 02 04:33:34 PM PDT 24	11027133435 ps
T888	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.3404883166			Jun 02 03:44:39 PM PDT 24	Jun 02 04:05:55 PM PDT 24	7970733033 ps
T217	/workspace/coverage/default/12.chip_sw_uart_rand_baudrate.526615111			Jun 02 04:05:51 PM PDT 24	Jun 02 04:18:09 PM PDT 24	4281973006 ps
T256	/workspace/coverage/default/1.chip_sw_rv_timer_irq.3110062260			Jun 02 03:46:28 PM PDT 24	Jun 02 03:50:39 PM PDT 24	3294233810 ps
T411	/workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.746501180			Jun 02 03:57:35 PM PDT 24	Jun 02 04:06:12 PM PDT 24	3965286104 ps
T57	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.3820947438			Jun 02 03:49:10 PM PDT 24	Jun 02 05:21:02 PM PDT 24	22045694712 ps
T112	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.4064469503			Jun 02 03:44:31 PM PDT 24	Jun 02 04:49:11 PM PDT 24	22694855089 ps
T215	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.2043148561			Jun 02 03:42:29 PM PDT 24	Jun 02 03:57:37 PM PDT 24	4703195050 ps
T212	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.687297547			Jun 02 03:45:07 PM PDT 24	Jun 02 03:56:12 PM PDT 24	4449854702 ps
T889	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.1621357281			Jun 02 03:45:23 PM PDT 24	Jun 02 03:56:11 PM PDT 24	7331487764 ps
T35	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.2544017174			Jun 02 03:57:50 PM PDT 24	Jun 02 04:28:00 PM PDT 24	23951458710 ps
T798	/workspace/coverage/default/78.chip_sw_all_escalation_resets.3323666522			Jun 02 04:11:32 PM PDT 24	Jun 02 04:21:41 PM PDT 24	5093098550 ps
T771	/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.254021553			Jun 02 04:09:35 PM PDT 24	Jun 02 04:15:15 PM PDT 24	3664060426 ps
T27	/workspace/coverage/default/0.chip_sw_spi_device_pass_through.3182095173			Jun 02 03:42:48 PM PDT 24	Jun 02 03:55:52 PM PDT 24	6250589707 ps
T120	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2047385339			Jun 02 03:47:16 PM PDT 24	Jun 02 03:56:40 PM PDT 24	4705010564 ps
T890	/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.1874800129			Jun 02 03:42:26 PM PDT 24	Jun 02 04:04:15 PM PDT 24	5259207200 ps
T682	/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.2881568121			Jun 02 04:13:00 PM PDT 24	Jun 02 04:19:27 PM PDT 24	3550311420 ps
T891	/workspace/coverage/default/0.chip_sw_entropy_src_smoketest.2110730308			Jun 02 03:46:08 PM PDT 24	Jun 02 03:55:07 PM PDT 24	3733384720 ps
T31	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2938115435			Jun 02 03:46:54 PM PDT 24	Jun 02 03:56:27 PM PDT 24	4128615142 ps
T179	/workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.1838847821			Jun 02 03:50:58 PM PDT 24	Jun 02 03:54:25 PM PDT 24	2399269784 ps
T306	/workspace/coverage/default/1.chip_sw_flash_ctrl_access.2078878040			Jun 02 03:43:12 PM PDT 24	Jun 02 04:02:26 PM PDT 24	5257131482 ps
T307	/workspace/coverage/default/25.chip_sw_all_escalation_resets.2187685239			Jun 02 04:09:11 PM PDT 24	Jun 02 04:18:18 PM PDT 24	5084487348 ps
T40	/workspace/coverage/default/0.chip_sw_gpio.2499405506			Jun 02 03:42:25 PM PDT 24	Jun 02 03:50:04 PM PDT 24	3887314067 ps
T308	/workspace/coverage/default/1.chip_sw_rstmgr_sw_req.2203536896			Jun 02 03:43:25 PM PDT 24	Jun 02 03:51:41 PM PDT 24	4846234352 ps
T309	/workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.1354326084			Jun 02 03:54:44 PM PDT 24	Jun 02 04:18:21 PM PDT 24	7498702912 ps
T71	/workspace/coverage/default/4.chip_tap_straps_prod.373174450			Jun 02 04:04:12 PM PDT 24	Jun 02 04:27:20 PM PDT 24	11134381334 ps
T261	/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.3100536946			Jun 02 04:05:27 PM PDT 24	Jun 02 05:36:37 PM PDT 24	26091016600 ps
T310	/workspace/coverage/default/0.rom_keymgr_functest.679530530			Jun 02 03:45:42 PM PDT 24	Jun 02 03:54:45 PM PDT 24	4241915612 ps
T54	/workspace/coverage/default/2.chip_sw_spi_device_tpm.2906376329			Jun 02 03:56:13 PM PDT 24	Jun 02 04:02:03 PM PDT 24	3121696627 ps
T543	/workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.2934576824			Jun 02 03:48:28 PM PDT 24	Jun 02 04:03:59 PM PDT 24	5151083414 ps
T720	/workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.3038527014			Jun 02 03:53:41 PM PDT 24	Jun 02 04:06:21 PM PDT 24	4549853640 ps
T124	/workspace/coverage/default/1.chip_sw_edn_boot_mode.3785185802			Jun 02 03:46:12 PM PDT 24	Jun 02 03:54:24 PM PDT 24	2751192740 ps
T113	/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.2791088603			Jun 02 03:49:09 PM PDT 24	Jun 02 04:23:50 PM PDT 24	10793364779 ps
T314	/workspace/coverage/default/0.chip_sw_uart_tx_rx.3451782688			Jun 02 03:44:32 PM PDT 24	Jun 02 03:56:00 PM PDT 24	4444210650 ps
T36	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.2429572490			Jun 02 03:44:48 PM PDT 24	Jun 02 04:50:44 PM PDT 24	20720543877 ps
T892	/workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.755157202			Jun 02 03:46:34 PM PDT 24	Jun 02 03:56:41 PM PDT 24	4213656092 ps
T893	/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.810204261			Jun 02 03:57:52 PM PDT 24	Jun 02 05:01:58 PM PDT 24	15558030136 ps
T894	/workspace/coverage/default/0.chip_sw_uart_smoketest.598467573			Jun 02 03:44:18 PM PDT 24	Jun 02 03:48:38 PM PDT 24	3091424632 ps
T289	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.2868575872			Jun 02 03:46:03 PM PDT 24	Jun 02 03:59:01 PM PDT 24	4185175508 ps
T143	/workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.3996449180			Jun 02 03:58:29 PM PDT 24	Jun 02 04:06:23 PM PDT 24	7142985284 ps
T69	/workspace/coverage/default/0.chip_tap_straps_testunlock0.2179914566			Jun 02 03:47:31 PM PDT 24	Jun 02 03:55:13 PM PDT 24	5472100746 ps
T330	/workspace/coverage/default/2.chip_plic_all_irqs_20.1078564635			Jun 02 04:00:40 PM PDT 24	Jun 02 04:15:45 PM PDT 24	4235066560 ps
T895	/workspace/coverage/default/39.chip_sw_all_escalation_resets.973032838			Jun 02 04:11:53 PM PDT 24	Jun 02 04:22:20 PM PDT 24	5013597688 ps
T13	/workspace/coverage/default/2.chip_sw_sleep_pin_retention.2348739906			Jun 02 03:54:02 PM PDT 24	Jun 02 03:58:59 PM PDT 24	3326725328 ps
T290	/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.809012188			Jun 02 04:00:53 PM PDT 24	Jun 02 04:11:52 PM PDT 24	7622201064 ps
T896	/workspace/coverage/default/1.chip_sw_uart_smoketest.2576264965			Jun 02 03:54:18 PM PDT 24	Jun 02 03:58:03 PM PDT 24	3243783314 ps
T545	/workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.395779138			Jun 02 03:48:48 PM PDT 24	Jun 02 04:17:46 PM PDT 24	13852132491 ps
T797	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.2053207371			Jun 02 03:44:38 PM PDT 24	Jun 02 03:50:54 PM PDT 24	3492459348 ps
T348	/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.2665846016			Jun 02 03:55:12 PM PDT 24	Jun 02 04:14:54 PM PDT 24	5463033916 ps
T897	/workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.1649791751			Jun 02 03:48:15 PM PDT 24	Jun 02 03:53:17 PM PDT 24	3372654220 ps
T898	/workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.2663965242			Jun 02 03:43:19 PM PDT 24	Jun 02 04:07:23 PM PDT 24	5611999540 ps
T899	/workspace/coverage/default/1.chip_sw_clkmgr_smoketest.3153169283			Jun 02 03:52:04 PM PDT 24	Jun 02 03:55:28 PM PDT 24	1945936290 ps
T900	/workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.3609107901			Jun 02 03:46:33 PM PDT 24	Jun 02 03:58:47 PM PDT 24	4765117544 ps
T901	/workspace/coverage/default/1.rom_e2e_smoke.2534393235			Jun 02 03:59:08 PM PDT 24	Jun 02 04:53:55 PM PDT 24	14330901692 ps
T362	/workspace/coverage/default/1.chip_sw_hmac_enc.2001055148			Jun 02 03:48:47 PM PDT 24	Jun 02 03:52:37 PM PDT 24	2788867354 ps
T902	/workspace/coverage/default/2.chip_sw_kmac_entropy.538941218			Jun 02 03:56:40 PM PDT 24	Jun 02 04:01:14 PM PDT 24	2476942984 ps
T903	/workspace/coverage/default/1.chip_sw_csrng_kat_test.3500492960			Jun 02 03:45:33 PM PDT 24	Jun 02 03:48:41 PM PDT 24	3009753848 ps
T276	/workspace/coverage/default/5.chip_sw_data_integrity_escalation.163651390			Jun 02 04:04:18 PM PDT 24	Jun 02 04:18:24 PM PDT 24	5490839448 ps
T279	/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.4125966151			Jun 02 04:11:55 PM PDT 24	Jun 02 04:18:41 PM PDT 24	3340607494 ps
T280	/workspace/coverage/default/1.chip_sw_all_escalation_resets.1169126075			Jun 02 03:49:07 PM PDT 24	Jun 02 04:00:17 PM PDT 24	5468672168 ps
T281	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.1448454666			Jun 02 03:58:20 PM PDT 24	Jun 02 04:24:49 PM PDT 24	9008908660 ps
T282	/workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.3200535620			Jun 02 03:56:44 PM PDT 24	Jun 02 04:05:18 PM PDT 24	3872662419 ps
T283	/workspace/coverage/default/69.chip_sw_all_escalation_resets.1355815657			Jun 02 04:12:56 PM PDT 24	Jun 02 04:25:49 PM PDT 24	5829900696 ps
T284	/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.2896039624			Jun 02 04:05:11 PM PDT 24	Jun 02 04:24:31 PM PDT 24	13298586948 ps
T114	/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.97867658			Jun 02 04:04:15 PM PDT 24	Jun 02 05:20:14 PM PDT 24	22751749023 ps
T285	/workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.511840968			Jun 02 03:47:47 PM PDT 24	Jun 02 04:30:39 PM PDT 24	19622242487 ps
T286	/workspace/coverage/default/0.chip_sw_kmac_entropy.3198113590			Jun 02 03:42:46 PM PDT 24	Jun 02 03:46:02 PM PDT 24	2774968648 ps
T904	/workspace/coverage/default/1.chip_sw_ast_clk_outputs.544085203			Jun 02 03:50:40 PM PDT 24	Jun 02 04:06:02 PM PDT 24	6406012352 ps
T344	/workspace/coverage/default/16.chip_sw_uart_rand_baudrate.3400877709			Jun 02 04:06:40 PM PDT 24	Jun 02 04:31:08 PM PDT 24	8488289984 ps
T905	/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1678748413			Jun 02 03:50:12 PM PDT 24	Jun 02 03:55:09 PM PDT 24	2924314342 ps
T729	/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.3948318402			Jun 02 04:14:03 PM PDT 24	Jun 02 04:19:26 PM PDT 24	3480975320 ps
T218	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.3210773593			Jun 02 03:46:07 PM PDT 24	Jun 02 03:57:34 PM PDT 24	4438877412 ps
T906	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2473978642			Jun 02 03:46:22 PM PDT 24	Jun 02 03:54:56 PM PDT 24	7328543288 ps
T907	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2581882211			Jun 02 03:44:46 PM PDT 24	Jun 02 04:39:55 PM PDT 24	37260091864 ps
T908	/workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.1668538135			Jun 02 04:03:48 PM PDT 24	Jun 02 04:08:51 PM PDT 24	3533227540 ps
T64	/workspace/coverage/default/2.chip_tap_straps_testunlock0.4184930767			Jun 02 04:01:51 PM PDT 24	Jun 02 04:12:55 PM PDT 24	6198423646 ps
T721	/workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.4217357194			Jun 02 03:43:21 PM PDT 24	Jun 02 03:52:19 PM PDT 24	5895674328 ps
T909	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.1846186423			Jun 02 04:03:50 PM PDT 24	Jun 02 04:23:49 PM PDT 24	13672940179 ps
T733	/workspace/coverage/default/44.chip_sw_all_escalation_resets.2292578365			Jun 02 04:09:31 PM PDT 24	Jun 02 04:17:02 PM PDT 24	4502108120 ps
T910	/workspace/coverage/default/2.chip_sw_example_concurrency.589530862			Jun 02 03:53:17 PM PDT 24	Jun 02 03:56:25 PM PDT 24	2530311040 ps
T911	/workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.3110588290			Jun 02 03:47:12 PM PDT 24	Jun 02 04:04:11 PM PDT 24	6003291938 ps
T700	/workspace/coverage/default/0.chip_sw_hmac_smoketest.2493842845			Jun 02 03:45:42 PM PDT 24	Jun 02 03:51:52 PM PDT 24	2996588486 ps
T127	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1245959284			Jun 02 04:03:00 PM PDT 24	Jun 02 04:09:59 PM PDT 24	4621814480 ps
T180	/workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.455325624			Jun 02 03:44:47 PM PDT 24	Jun 02 03:48:52 PM PDT 24	2872986259 ps
T770	/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.1134044128			Jun 02 04:10:18 PM PDT 24	Jun 02 04:17:33 PM PDT 24	3856296164 ps
T249	/workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.4029703754			Jun 02 04:01:34 PM PDT 24	Jun 02 04:12:06 PM PDT 24	5886697431 ps
T912	/workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.492838553			Jun 02 04:08:41 PM PDT 24	Jun 02 04:11:56 PM PDT 24	1923249044 ps
T913	/workspace/coverage/default/1.chip_tap_straps_prod.2001352504			Jun 02 03:47:10 PM PDT 24	Jun 02 04:01:04 PM PDT 24	7939983183 ps
T470	/workspace/coverage/default/2.chip_sw_edn_kat.3528459871			Jun 02 03:59:12 PM PDT 24	Jun 02 04:09:08 PM PDT 24	3685835028 ps
T683	/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.2659579422			Jun 02 04:07:25 PM PDT 24	Jun 02 04:14:31 PM PDT 24	3759442428 ps
T219	/workspace/coverage/default/2.chip_sw_pattgen_ios.3679715942			Jun 02 03:54:06 PM PDT 24	Jun 02 03:59:05 PM PDT 24	2912060840 ps
T250	/workspace/coverage/default/97.chip_sw_all_escalation_resets.2067918102			Jun 02 04:13:17 PM PDT 24	Jun 02 04:23:47 PM PDT 24	4923629936 ps
T72	/workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.3943326916			Jun 02 03:52:15 PM PDT 24	Jun 02 04:00:02 PM PDT 24	5216832712 ps
T297	/workspace/coverage/default/77.chip_sw_all_escalation_resets.70501271			Jun 02 04:11:41 PM PDT 24	Jun 02 04:18:34 PM PDT 24	3969905624 ps
T16	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2676355446			Jun 02 04:02:23 PM PDT 24	Jun 02 04:22:54 PM PDT 24	16406876076 ps
T298	/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.2395414768			Jun 02 04:07:54 PM PDT 24	Jun 02 04:13:33 PM PDT 24	3499215660 ps