Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.uart2_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	130230	1			T76	64		T77	290		T78	2
values[2]	8184	1			T76	6		T79	2		T252	1
values[3]	3276	1			T79	1		T551	1		T459	6
values[4]	1927	1			T551	1		T459	2		T482	4
values[5]	1258	1			T551	1		T482	3		T827	20
values[6]	952	1			T551	1		T482	17		T827	8
values[7]	701	1			T551	1		T482	4		T480	1
values[8]	571	1			T551	1		T482	12		T480	1
values[9]	515	1			T551	1		T482	12		T480	1
values[10]	411	1			T551	1		T482	3		T480	2
values[11]	387	1			T551	1		T482	11		T480	1
values[12]	400	1			T551	1		T482	8		T480	1
values[13]	329	1			T551	1		T482	8		T480	1
values[14]	321	1			T551	1		T482	8		T480	1
values[15]	381	1			T551	1		T482	3		T480	1
values[16]	325	1			T551	1		T482	8		T480	1
values[17]	383	1			T551	1		T482	12		T480	1
values[18]	354	1			T551	1		T482	9		T480	1
values[19]	342	1			T551	1		T482	7		T480	1
values[20]	323	1			T551	1		T482	12		T480	1
values[21]	328	1			T551	1		T482	8		T480	1
values[22]	304	1			T551	1		T482	8		T480	1
values[23]	322	1			T551	1		T482	7		T480	1
values[24]	357	1			T551	1		T482	29		T480	1
values[25]	308	1			T551	1		T482	8		T480	1
values[26]	285	1			T551	1		T482	5		T480	1
values[27]	365	1			T551	1		T482	2		T480	1
values[28]	332	1			T551	1		T482	3		T480	1
values[29]	313	1			T551	1		T482	4		T480	1
values[30]	279	1			T551	1		T482	2		T480	1
values[31]	307	1			T551	1		T482	3		T480	1
values[32]	354	1			T551	1		T482	31		T480	1
values[33]	318	1			T551	1		T482	6		T480	1
values[34]	273	1			T551	1		T482	4		T480	1
values[35]	300	1			T551	1		T482	5		T480	1
values[36]	318	1			T551	1		T482	6		T480	1
values[37]	331	1			T551	1		T482	4		T480	1
values[38]	332	1			T551	1		T482	4		T480	1
values[39]	303	1			T551	1		T482	8		T480	1
values[40]	301	1			T551	1		T482	10		T480	1
values[41]	307	1			T551	1		T482	14		T480	1
values[42]	310	1			T551	1		T482	15		T480	1
values[43]	272	1			T551	1		T482	10		T480	1
values[44]	264	1			T551	1		T482	9		T480	1
values[45]	295	1			T551	1		T482	8		T480	1
values[46]	323	1			T551	1		T482	8		T480	1
values[47]	319	1			T551	1		T482	7		T480	1
values[48]	252	1			T551	1		T482	5		T480	1
values[49]	298	1			T551	1		T482	4		T480	1
values[50]	261	1			T551	1		T482	5		T480	1
values[51]	290	1			T551	1		T482	4		T480	1
values[52]	277	1			T551	1		T482	8		T480	1
values[53]	291	1			T551	1		T482	4		T480	1
values[54]	260	1			T551	1		T482	4		T480	1
values[55]	290	1			T551	1		T482	5		T480	1
values[56]	218	1			T551	1		T482	3		T480	1
values[57]	250	1			T551	1		T482	2		T480	1
values[58]	293	1			T551	1		T482	10		T480	1
values[59]	223	1			T551	1		T482	7		T480	1
values[60]	221	1			T551	1		T482	4		T480	1
values[61]	179	1			T551	1		T482	6		T480	1
values[62]	192	1			T551	1		T482	14		T480	1
values[63]	202	1			T551	1		T482	2		T480	1
values[64]	166	1			T551	1		T482	4		T480	1
values[65]	171	1			T551	1		T482	9		T480	1
values[66]	181	1			T551	1		T482	4		T480	1
values[67]	167	1			T551	1		T482	7		T480	1
values[68]	134	1			T551	1		T480	1		T518	6
values[69]	154	1			T551	1		T480	1		T518	4
values[70]	142	1			T551	1		T480	1		T518	4
values[71]	114	1			T551	1		T480	1		T518	4
values[72]	108	1			T551	1		T480	1		T518	5
values[73]	119	1			T551	1		T480	1		T518	5
values[74]	106	1			T551	1		T480	1		T518	5
values[75]	107	1			T551	1		T480	1		T518	6
values[76]	83	1			T551	1		T480	1		T518	3
values[77]	96	1			T551	1		T480	1		T518	6
values[78]	86	1			T551	1		T480	1		T518	7
values[79]	81	1			T551	1		T480	1		T518	16
values[80]	80	1			T551	1		T480	1		T518	8
values[81]	72	1			T551	1		T480	1		T839	1
values[82]	73	1			T551	1		T480	1		T839	1
values[83]	72	1			T551	1		T480	1		T839	1
values[84]	83	1			T551	1		T480	1		T839	1
values[85]	72	1			T551	1		T480	1		T839	1
values[86]	61	1			T551	1		T480	1		T839	1
values[87]	65	1			T551	1		T480	1		T839	1
values[88]	74	1			T551	1		T480	1		T839	1
values[89]	105	1			T551	1		T480	1		T839	1
values[90]	111	1			T551	1		T480	1		T839	1
values[91]	88	1			T551	1		T480	1		T839	1
values[92]	91	1			T551	1		T480	1		T839	1
values[93]	102	1			T551	1		T480	1		T839	1
values[94]	105	1			T551	1		T480	1		T839	1
values[95]	103	1			T551	1		T480	1		T839	1
values[96]	112	1			T551	1		T480	1		T839	4
values[97]	112	1			T551	1		T480	1		T839	5
values[98]	96	1			T551	1		T480	1		T839	2
values[99]	89	1			T551	1		T480	1		T839	2
values[100]	109	1			T551	1		T480	1		T839	10
values[101]	95	1			T551	1		T480	1		T839	1
values[102]	86	1			T551	1		T480	1		T839	1
values[103]	97	1			T551	1		T480	7		T839	3
values[104]	116	1			T551	1		T480	1		T839	2
values[105]	78	1			T551	1		T480	1		T839	3
values[106]	93	1			T551	1		T480	2		T839	1
values[107]	102	1			T551	1		T480	3		T839	3
values[108]	95	1			T551	1		T480	2		T839	4
values[109]	101	1			T551	1		T480	3		T839	6
values[110]	81	1			T551	1		T480	1		T839	1
values[111]	99	1			T551	1		T480	1		T839	1
values[112]	121	1			T551	1		T480	1		T839	1
values[113]	95	1			T551	1		T480	2		T839	2
values[114]	94	1			T551	1		T480	1		T839	1
values[115]	96	1			T551	1		T480	3		T839	4
values[116]	82	1			T551	1		T480	1		T839	1
values[117]	87	1			T551	1		T480	5		T839	1
values[118]	74	1			T551	1		T480	2		T839	2
values[119]	96	1			T551	1		T480	2		T839	2
values[120]	78	1			T551	2		T480	2		T839	3
values[121]	84	1			T551	1		T480	1		T839	2
values[122]	75	1			T551	1		T480	1		T839	2
values[123]	67	1			T551	1		T480	1		T839	2
values[124]	78	1			T551	1		T480	7		T839	2
values[125]	95	1			T551	1		T480	2		T839	1
values[126]	199	1			T551	2		T480	3		T839	3
values[127]	1043	1			T551	22		T480	31		T839	25
values[128]	8139	1			T551	266		T480	297		T839	330