Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	473	1			T77	5		T677	1		T520	2
all_values[1]	490	1			T77	1		T435	1		T459	1
all_values[2]	431	1			T77	3		T807	1		T520	1
all_values[3]	466	1			T77	5		T677	1		T551	1
all_values[4]	461	1			T77	6		T435	1		T520	1
all_values[5]	468	1			T77	3		T459	1		T520	1
all_values[6]	510	1			T77	3		T444	1		T711	1
all_values[7]	433	1			T153	1		T77	3		T551	1
all_values[8]	459	1			T520	2		T428	1		T458	2
all_values[9]	480	1			T77	3		T459	1		T807	1
all_values[10]	482	1			T677	1		T520	3		T808	1
all_values[11]	471	1			T77	2		T520	1		T428	3
all_values[12]	470	1			T77	4		T677	1		T551	1
all_values[13]	468	1			T77	1		T677	1		T551	1
all_values[14]	433	1			T520	1		T816	1		T428	4
all_values[15]	443	1			T711	1		T520	1		T428	3
all_values[16]	486	1			T77	2		T551	4		T459	2
all_values[17]	511	1			T77	2		T520	4		T816	1
all_values[18]	479	1			T77	3		T711	3		T520	1
all_values[19]	517	1			T77	2		T520	4		T428	3
all_values[20]	476	1			T77	4		T677	1		T520	1
all_values[21]	496	1			T77	2		T520	2		T428	3
all_values[22]	455	1			T77	2		T677	1		T520	1
all_values[23]	504	1			T77	4		T711	1		T476	1
all_values[24]	464	1			T77	5		T807	1		T520	4
all_values[25]	449	1			T77	3		T551	1		T711	1
all_values[26]	485	1			T77	5		T435	1		T711	1
all_values[27]	455	1			T77	1		T444	1		T822	1
all_values[28]	484	1			T77	3		T459	1		T520	1
all_values[29]	486	1			T77	2		T459	1		T520	3
all_values[30]	465	1			T77	2		T677	1		T459	1
all_values[31]	485	1			T77	2		T459	1		T520	1
all_values[32]	483	1			T77	3		T444	1		T677	1
all_values[33]	469	1			T77	2		T459	1		T520	1
all_values[34]	450	1			T77	1		T428	3		T458	1
all_values[35]	471	1			T77	1		T677	1		T459	1
all_values[36]	459	1			T77	2		T551	1		T459	1
all_values[37]	454	1			T77	2		T677	1		T807	2
all_values[38]	462	1			T77	5		T444	1		T520	2
all_values[39]	459	1			T77	2		T711	1		T520	1
all_values[40]	464	1			T77	4		T435	1		T459	2
all_values[41]	498	1			T77	1		T444	1		T807	1
all_values[42]	471	1			T77	1		T551	1		T520	2
all_values[43]	506	1			T77	1		T551	1		T711	1
all_values[44]	474	1			T77	2		T520	3		T428	3
all_values[45]	465	1			T77	4		T435	1		T711	1
all_values[46]	449	1			T77	4		T520	3		T428	2
all_values[47]	474	1			T77	2		T711	1		T520	2
all_values[48]	467	1			T77	2		T677	1		T459	1
all_values[49]	503	1			T77	2		T711	1		T807	1