Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3384	1			T77	8		T435	1		T501	5
all_values[1]	3486	1			T77	8		T501	3		T711	5
all_values[2]	3469	1			T77	9		T445	2		T435	3
all_values[3]	3578	1			T77	11		T445	2		T435	1
all_values[4]	3578	1			T77	10		T445	1		T446	3
all_values[5]	3586	1			T77	6		T445	3		T446	1
all_values[6]	3536	1			T77	5		T445	1		T446	1
all_values[7]	3530	1			T77	13		T445	3		T446	1
all_values[8]	3620	1			T77	15		T435	2		T501	2
all_values[9]	3495	1			T77	11		T445	1		T501	5
all_values[10]	3564	1			T77	15		T445	4		T435	1
all_values[11]	3637	1			T77	8		T445	1		T435	3
all_values[12]	3452	1			T77	9		T445	1		T435	1
all_values[13]	3630	1			T77	16		T445	2		T435	1
all_values[14]	3536	1			T77	11		T435	4		T446	1
all_values[15]	3541	1			T77	7		T445	1		T435	2
all_values[16]	3429	1			T77	11		T445	1		T435	1
all_values[17]	3625	1			T77	7		T445	1		T435	1
all_values[18]	3521	1			T77	11		T445	3		T435	1
all_values[19]	3629	1			T77	21		T445	2		T501	1
all_values[20]	3577	1			T77	9		T445	5		T446	1
all_values[21]	3519	1			T77	12		T445	3		T435	1
all_values[22]	3607	1			T77	7		T446	1		T501	3
all_values[23]	3520	1			T77	12		T445	1		T446	1
all_values[24]	3549	1			T77	6		T435	2		T501	4
all_values[25]	3423	1			T77	11		T445	1		T435	3
all_values[26]	3510	1			T77	16		T445	2		T501	3
all_values[27]	3453	1			T77	10		T445	1		T446	2
all_values[28]	3526	1			T77	8		T445	2		T435	1
all_values[29]	3507	1			T77	8		T435	3		T501	2
all_values[30]	3480	1			T77	8		T445	2		T435	1
all_values[31]	3494	1			T77	15		T445	4		T435	1
all_values[32]	3502	1			T77	17		T445	1		T435	2
all_values[33]	3584	1			T77	3		T445	2		T435	3
all_values[34]	3525	1			T77	16		T445	3		T435	1
all_values[35]	3570	1			T77	7		T445	3		T446	1
all_values[36]	3553	1			T77	17		T445	1		T446	1
all_values[37]	3516	1			T77	7		T445	3		T446	1
all_values[38]	3432	1			T77	8		T445	2		T435	1
all_values[39]	3539	1			T77	12		T445	2		T501	1
all_values[40]	3557	1			T77	12		T445	1		T435	5
all_values[41]	3594	1			T77	10		T445	1		T435	2
all_values[42]	3625	1			T77	7		T445	2		T435	1
all_values[43]	3520	1			T77	15		T445	2		T446	1
all_values[44]	3580	1			T77	8		T445	2		T435	2
all_values[45]	3562	1			T77	14		T445	1		T435	2
all_values[46]	3629	1			T77	12		T445	4		T435	2
all_values[47]	3391	1			T77	12		T445	2		T501	3
all_values[48]	3615	1			T77	11		T445	1		T435	2
all_values[49]	3497	1			T77	16		T445	3		T435	1
all_values[50]	3462	1			T77	15		T445	1		T501	5
all_values[51]	3495	1			T77	11		T435	3		T446	1
all_values[52]	3575	1			T77	18		T445	1		T435	1
all_values[53]	3540	1			T77	10		T445	2		T435	2
all_values[54]	3572	1			T77	7		T445	2		T435	2
all_values[55]	3492	1			T77	9		T501	4		T711	8
all_values[56]	3562	1			T77	13		T435	1		T446	1
all_values[57]	3490	1			T77	10		T445	2		T435	1
all_values[58]	3516	1			T77	13		T501	1		T711	3
all_values[59]	3505	1			T77	10		T445	2		T446	1
all_values[60]	3555	1			T77	13		T435	2		T501	3
all_values[61]	3491	1			T77	12		T445	1		T446	1
all_values[62]	3581	1			T77	10		T435	2		T446	2
all_values[63]	3514	1			T77	11		T445	1		T501	2