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LINE 30472
EXPRESSION (dio_pad_sleep_mode_12_we & dio_pad_sleep_regwen_12_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T392,T393,T395 |
1 | 1 | Covered | T24,T25,T26 |
LINE 30504
EXPRESSION (dio_pad_sleep_mode_13_we & dio_pad_sleep_regwen_13_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T392,T393,T395 |
1 | 1 | Covered | T24,T25,T26 |
LINE 30536
EXPRESSION (dio_pad_sleep_mode_14_we & dio_pad_sleep_regwen_14_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T392,T393,T395 |
1 | 1 | Covered | T24,T25,T26 |
LINE 30568
EXPRESSION (dio_pad_sleep_mode_15_we & dio_pad_sleep_regwen_15_qs)
------------1----------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T392,T131,T415 |
1 | 1 | Covered | T24,T25,T26 |
LINE 30832
EXPRESSION (aon_wkup_detector_en_0_we & aon_wkup_detector_en_0_regwen)
------------1------------ --------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T392,T393,T395 |
1 | 1 | Covered | T2,T13,T14 |
LINE 30865
EXPRESSION (aon_wkup_detector_en_1_we & aon_wkup_detector_en_1_regwen)
------------1------------ --------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T393,T395,T396 |
1 | 1 | Covered | T392,T393,T395 |
LINE 30898
EXPRESSION (aon_wkup_detector_en_2_we & aon_wkup_detector_en_2_regwen)
------------1------------ --------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T393,T397,T415 |
1 | 1 | Covered | T392,T393,T395 |
LINE 30931
EXPRESSION (aon_wkup_detector_en_3_we & aon_wkup_detector_en_3_regwen)
------------1------------ --------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T392,T393,T395 |
1 | 1 | Covered | T11,T396,T397 |
LINE 30964
EXPRESSION (aon_wkup_detector_en_4_we & aon_wkup_detector_en_4_regwen)
------------1------------ --------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T393,T396,T423 |
1 | 1 | Covered | T392,T393,T395 |
LINE 30997
EXPRESSION (aon_wkup_detector_en_5_we & aon_wkup_detector_en_5_regwen)
------------1------------ --------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T393,T397,T415 |
1 | 1 | Covered | T1,T3,T16 |
LINE 31030
EXPRESSION (aon_wkup_detector_en_6_we & aon_wkup_detector_en_6_regwen)
------------1------------ --------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T392,T393,T423 |
1 | 1 | Covered | T15,T392,T393 |
LINE 31063
EXPRESSION (aon_wkup_detector_en_7_we & aon_wkup_detector_en_7_regwen)
------------1------------ --------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T392,T395,T131 |
1 | 1 | Covered | T12,T392,T393 |
LINE 31096
EXPRESSION (aon_wkup_detector_0_we & aon_wkup_detector_0_regwen)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T393,T395,T131 |
1 | 1 | Covered | T2,T13,T14 |
LINE 31183
EXPRESSION (aon_wkup_detector_1_we & aon_wkup_detector_1_regwen)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T392,T395,T396 |
1 | 1 | Covered | T392,T393,T395 |
LINE 31270
EXPRESSION (aon_wkup_detector_2_we & aon_wkup_detector_2_regwen)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T393,T397,T394 |
1 | 1 | Covered | T392,T393,T395 |
LINE 31357
EXPRESSION (aon_wkup_detector_3_we & aon_wkup_detector_3_regwen)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T392,T393,T395 |
1 | 1 | Covered | T11,T392,T396 |
LINE 31444
EXPRESSION (aon_wkup_detector_4_we & aon_wkup_detector_4_regwen)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T392,T393,T396 |
1 | 1 | Covered | T395,T397,T394 |
LINE 31531
EXPRESSION (aon_wkup_detector_5_we & aon_wkup_detector_5_regwen)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T393,T397,T394 |
1 | 1 | Covered | T1,T3,T16 |
LINE 31618
EXPRESSION (aon_wkup_detector_6_we & aon_wkup_detector_6_regwen)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T392,T393,T423 |
1 | 1 | Covered | T15,T392,T393 |
LINE 31705
EXPRESSION (aon_wkup_detector_7_we & aon_wkup_detector_7_regwen)
-----------1---------- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T392,T393,T395 |
1 | 1 | Covered | T12,T393,T395 |
LINE 31792
EXPRESSION (aon_wkup_detector_cnt_th_0_we & aon_wkup_detector_cnt_th_0_regwen)
--------------1-------------- ----------------2----------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T392,T395,T423 |
1 | 1 | Covered | T392,T393,T395 |
LINE 31825
EXPRESSION (aon_wkup_detector_cnt_th_1_we & aon_wkup_detector_cnt_th_1_regwen)
--------------1-------------- ----------------2----------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T392,T395,T396 |
1 | 1 | Covered | T7,T421,T8 |
LINE 31858
EXPRESSION (aon_wkup_detector_cnt_th_2_we & aon_wkup_detector_cnt_th_2_regwen)
--------------1-------------- ----------------2----------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T397,T394,T417 |
1 | 1 | Covered | T392,T393,T395 |
LINE 31891
EXPRESSION (aon_wkup_detector_cnt_th_3_we & aon_wkup_detector_cnt_th_3_regwen)
--------------1-------------- ----------------2----------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T392,T393,T395 |
1 | 1 | Covered | T392,T396,T397 |
LINE 31924
EXPRESSION (aon_wkup_detector_cnt_th_4_we & aon_wkup_detector_cnt_th_4_regwen)
--------------1-------------- ----------------2----------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T392,T393,T423 |
1 | 1 | Covered | T392,T393,T395 |
LINE 31957
EXPRESSION (aon_wkup_detector_cnt_th_5_we & aon_wkup_detector_cnt_th_5_regwen)
--------------1-------------- ----------------2----------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T392,T393,T397 |
1 | 1 | Covered | T392,T393,T395 |
LINE 31990
EXPRESSION (aon_wkup_detector_cnt_th_6_we & aon_wkup_detector_cnt_th_6_regwen)
--------------1-------------- ----------------2----------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T392,T393,T423 |
1 | 1 | Covered | T392,T395,T396 |
LINE 32023
EXPRESSION (aon_wkup_detector_cnt_th_7_we & aon_wkup_detector_cnt_th_7_regwen)
--------------1-------------- ----------------2----------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T392,T393,T395 |
1 | 1 | Covered | T393,T395,T396 |
LINE 32056
EXPRESSION (wkup_detector_padsel_0_we & wkup_detector_regwen_0_qs)
------------1------------ ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T392,T395,T131 |
1 | 1 | Covered | T2,T13,T14 |
LINE 32088
EXPRESSION (wkup_detector_padsel_1_we & wkup_detector_regwen_1_qs)
------------1------------ ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T392,T395,T396 |
1 | 1 | Covered | T392,T459,T476 |
LINE 32120
EXPRESSION (wkup_detector_padsel_2_we & wkup_detector_regwen_2_qs)
------------1------------ ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T393,T397,T394 |
1 | 1 | Covered | T392,T393,T480 |
LINE 32152
EXPRESSION (wkup_detector_padsel_3_we & wkup_detector_regwen_3_qs)
------------1------------ ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T392,T393,T395 |
1 | 1 | Covered | T11,T447,T427 |
LINE 32184
EXPRESSION (wkup_detector_padsel_4_we & wkup_detector_regwen_4_qs)
------------1------------ ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T393,T396,T423 |
1 | 1 | Covered | T435,T501,T392 |
LINE 32216
EXPRESSION (wkup_detector_padsel_5_we & wkup_detector_regwen_5_qs)
------------1------------ ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T392,T393,T131 |
1 | 1 | Covered | T1,T3,T16 |
LINE 32248
EXPRESSION (wkup_detector_padsel_6_we & wkup_detector_regwen_6_qs)
------------1------------ ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T392,T393,T423 |
1 | 1 | Covered | T15,T542,T393 |
LINE 32280
EXPRESSION (wkup_detector_padsel_7_we & wkup_detector_regwen_7_qs)
------------1------------ ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T392,T393,T395 |
1 | 1 | Covered | T12,T392,T520 |
LINE 32533
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_ALERT_TEST_OFFSET)
---------------------------1--------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T5,T6 |
LINE 32534
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_0_OFFSET)
----------------------------------1----------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T5,T6 |
LINE 32535
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_1_OFFSET)
----------------------------------1----------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T5,T6 |
LINE 32536
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_2_OFFSET)
----------------------------------1----------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T5,T6 |
LINE 32537
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_3_OFFSET)
----------------------------------1----------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T5,T6 |
LINE 32538
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_4_OFFSET)
----------------------------------1----------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T5,T6 |
LINE 32539
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_5_OFFSET)
----------------------------------1----------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T5,T6 |
LINE 32540
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_6_OFFSET)
----------------------------------1----------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T5,T6 |
LINE 32541
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_7_OFFSET)
----------------------------------1----------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T5,T6 |
LINE 32542
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_8_OFFSET)
----------------------------------1----------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T5,T6 |
LINE 32543
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_9_OFFSET)
----------------------------------1----------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T5,T6 |
LINE 32544
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_10_OFFSET)
-----------------------------------1----------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T5,T6 |
LINE 32545
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_11_OFFSET)
-----------------------------------1----------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T5,T6 |
LINE 32546
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_12_OFFSET)
-----------------------------------1----------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T5,T6 |
LINE 32547
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_13_OFFSET)
-----------------------------------1----------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T5,T6 |
LINE 32548
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_14_OFFSET)
-----------------------------------1----------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T5,T6 |
LINE 32549
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_15_OFFSET)
-----------------------------------1----------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T5,T6 |
LINE 32550
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_16_OFFSET)
-----------------------------------1----------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T5,T6 |
LINE 32551
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_17_OFFSET)
-----------------------------------1----------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T5,T6 |
LINE 32552
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_18_OFFSET)
-----------------------------------1----------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T5,T6 |
LINE 32553
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_19_OFFSET)
-----------------------------------1----------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T5,T6 |
LINE 32554
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_20_OFFSET)
-----------------------------------1----------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T5,T6 |
LINE 32555
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_21_OFFSET)
-----------------------------------1----------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T5,T6 |
LINE 32556
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_22_OFFSET)
-----------------------------------1----------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T5,T6 |
LINE 32557
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_23_OFFSET)
-----------------------------------1----------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T5,T6 |
LINE 32558
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_24_OFFSET)
-----------------------------------1----------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T5,T6 |
LINE 32559
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_25_OFFSET)
-----------------------------------1----------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T5,T6 |
LINE 32560
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_26_OFFSET)
-----------------------------------1----------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T5,T6 |
LINE 32561
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_27_OFFSET)
-----------------------------------1----------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T5,T6 |
LINE 32562
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_28_OFFSET)
-----------------------------------1----------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T5,T6 |
LINE 32563
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_29_OFFSET)
-----------------------------------1----------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T5,T6 |
LINE 32564
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_30_OFFSET)
-----------------------------------1----------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T5,T6 |
LINE 32565
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_31_OFFSET)
-----------------------------------1----------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T5,T6 |
LINE 32566
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_32_OFFSET)
-----------------------------------1----------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T5,T6 |
LINE 32567
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_33_OFFSET)
-----------------------------------1----------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T5,T6 |
LINE 32568
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_34_OFFSET)
-----------------------------------1----------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T5,T6 |
LINE 32569
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_35_OFFSET)
-----------------------------------1----------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T5,T6 |
LINE 32570
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_36_OFFSET)
-----------------------------------1----------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T5,T6 |
LINE 32571
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_37_OFFSET)
-----------------------------------1----------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T5,T6 |
LINE 32572
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_38_OFFSET)
-----------------------------------1----------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32573
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_39_OFFSET)
-----------------------------------1----------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32574
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_40_OFFSET)
-----------------------------------1----------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32575
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_41_OFFSET)
-----------------------------------1----------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32576
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_42_OFFSET)
-----------------------------------1----------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T5,T6 |
LINE 32577
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_43_OFFSET)
-----------------------------------1----------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T5,T6 |
LINE 32578
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_44_OFFSET)
-----------------------------------1----------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32579
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_45_OFFSET)
-----------------------------------1----------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32580
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_46_OFFSET)
-----------------------------------1----------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32581
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_47_OFFSET)
-----------------------------------1----------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32582
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_48_OFFSET)
-----------------------------------1----------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32583
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_49_OFFSET)
-----------------------------------1----------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32584
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_50_OFFSET)
-----------------------------------1----------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32585
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_51_OFFSET)
-----------------------------------1----------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32586
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_52_OFFSET)
-----------------------------------1----------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32587
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_53_OFFSET)
-----------------------------------1----------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32588
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_54_OFFSET)
-----------------------------------1----------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32589
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_55_OFFSET)
-----------------------------------1----------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32590
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_REGWEN_56_OFFSET)
-----------------------------------1----------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32591
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_0_OFFSET)
-------------------------------1------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T46 |
LINE 32592
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_1_OFFSET)
-------------------------------1------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32593
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_2_OFFSET)
-------------------------------1------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32594
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_3_OFFSET)
-------------------------------1------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32595
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_4_OFFSET)
-------------------------------1------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32596
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_5_OFFSET)
-------------------------------1------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32597
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_6_OFFSET)
-------------------------------1------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T20,T84 |
LINE 32598
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_7_OFFSET)
-------------------------------1------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T20,T84 |
LINE 32599
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_8_OFFSET)
-------------------------------1------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32600
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_9_OFFSET)
-------------------------------1------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T20,T84 |
LINE 32601
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_10_OFFSET)
-------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T20,T84 |
LINE 32602
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_11_OFFSET)
-------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T20,T84 |
LINE 32603
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_12_OFFSET)
-------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T20,T84 |
LINE 32604
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_13_OFFSET)
-------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T20,T84 |
LINE 32605
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_14_OFFSET)
-------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32606
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_15_OFFSET)
-------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32607
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_16_OFFSET)
-------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32608
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_17_OFFSET)
-------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32609
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_18_OFFSET)
-------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32610
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_19_OFFSET)
-------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32611
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_20_OFFSET)
-------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32612
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_21_OFFSET)
-------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T47 |
LINE 32613
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_22_OFFSET)
-------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T5,T6 |
LINE 32614
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_23_OFFSET)
-------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T5,T6 |
LINE 32615
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_24_OFFSET)
-------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T5,T6 |
LINE 32616
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_25_OFFSET)
-------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32617
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_26_OFFSET)
-------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32618
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_27_OFFSET)
-------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32619
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_28_OFFSET)
-------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32620
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_29_OFFSET)
-------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32621
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_30_OFFSET)
-------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32622
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_31_OFFSET)
-------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32623
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_32_OFFSET)
-------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32624
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_33_OFFSET)
-------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32625
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_34_OFFSET)
-------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32626
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_35_OFFSET)
-------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32627
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_36_OFFSET)
-------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T19,T84 |
LINE 32628
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_37_OFFSET)
-------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T19,T84 |
LINE 32629
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_38_OFFSET)
-------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32630
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_39_OFFSET)
-------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32631
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_40_OFFSET)
-------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32632
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_41_OFFSET)
-------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32633
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_42_OFFSET)
-------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T5,T6 |
LINE 32634
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_43_OFFSET)
-------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T5,T6 |
LINE 32635
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_44_OFFSET)
-------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T18,T84 |
LINE 32636
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_45_OFFSET)
-------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32637
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_46_OFFSET)
-------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32638
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_47_OFFSET)
-------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32639
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_48_OFFSET)
-------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32640
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_49_OFFSET)
-------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32641
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_50_OFFSET)
-------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32642
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_51_OFFSET)
-------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32643
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_52_OFFSET)
-------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32644
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_53_OFFSET)
-------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32645
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_54_OFFSET)
-------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32646
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_55_OFFSET)
-------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32647
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PERIPH_INSEL_56_OFFSET)
-------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32648
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_0_OFFSET)
-------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32649
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_1_OFFSET)
-------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32650
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_2_OFFSET)
-------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32651
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_3_OFFSET)
-------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32652
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_4_OFFSET)
-------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32653
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_5_OFFSET)
-------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32654
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_6_OFFSET)
-------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32655
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_7_OFFSET)
-------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32656
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_8_OFFSET)
-------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T46 |
LINE 32657
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_9_OFFSET)
-------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32658
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_10_OFFSET)
--------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32659
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_11_OFFSET)
--------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32660
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_12_OFFSET)
--------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32661
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_13_OFFSET)
--------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T5,T6 |
LINE 32662
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_14_OFFSET)
--------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T5,T6 |
LINE 32663
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_15_OFFSET)
--------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32664
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_16_OFFSET)
--------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32665
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_17_OFFSET)
--------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32666
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_18_OFFSET)
--------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32667
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_19_OFFSET)
--------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |
LINE 32668
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_20_OFFSET)
--------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T19,T84 |
LINE 32669
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_21_OFFSET)
--------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T19,T84 |
LINE 32670
EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_22_OFFSET)
--------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T5,T84,T63 |