Unified Coverage Report :: Cond split page

Go back

 LINE       33107
 SUB-EXPRESSION (addr_hit[134] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T84,T63
1	1	Covered	T77,T473,T546

 LINE       33107
 SUB-EXPRESSION (addr_hit[135] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T19,T84
1	1	Covered	T77,T79,T444

 LINE       33107
 SUB-EXPRESSION (addr_hit[136] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T19,T84
1	1	Covered	T77,T252,T456

 LINE       33107
 SUB-EXPRESSION (addr_hit[137] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T84,T63
1	1	Covered	T77,T473,T444

 LINE       33107
 SUB-EXPRESSION (addr_hit[138] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T84,T63
1	1	Covered	T76,T77,T456

 LINE       33107
 SUB-EXPRESSION (addr_hit[139] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T84,T63
1	1	Covered	T77,T79,T435

 LINE       33107
 SUB-EXPRESSION (addr_hit[140] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T77,T473,T444

 LINE       33107
 SUB-EXPRESSION (addr_hit[141] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T76,T252,T550

 LINE       33107
 SUB-EXPRESSION (addr_hit[142] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T84,T63
1	1	Covered	T76,T445,T435

 LINE       33107
 SUB-EXPRESSION (addr_hit[143] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T84,T63
1	1	Covered	T76,T77,T79

 LINE       33107
 SUB-EXPRESSION (addr_hit[144] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T77,T435,T549

 LINE       33107
 SUB-EXPRESSION (addr_hit[145] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T84,T63
1	1	Covered	T77,T444,T546

 LINE       33107
 SUB-EXPRESSION (addr_hit[146] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T84,T63
1	1	Covered	T77,T546,T501

 LINE       33107
 SUB-EXPRESSION (addr_hit[147] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T84,T63
1	1	Covered	T76,T77,T473

 LINE       33107
 SUB-EXPRESSION (addr_hit[148] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T84,T63
1	1	Covered	T76,T77,T79

 LINE       33107
 SUB-EXPRESSION (addr_hit[149] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T84,T63
1	1	Covered	T76,T77,T445

 LINE       33107
 SUB-EXPRESSION (addr_hit[150] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T84,T63
1	1	Covered	T77,T79,T473

 LINE       33107
 SUB-EXPRESSION (addr_hit[151] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T84,T63
1	1	Covered	T77,T550,T435

 LINE       33107
 SUB-EXPRESSION (addr_hit[152] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T84,T63
1	1	Covered	T77,T79,T550

 LINE       33107
 SUB-EXPRESSION (addr_hit[153] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T84,T63
1	1	Covered	T76,T77,T79

 LINE       33107
 SUB-EXPRESSION (addr_hit[154] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T84,T63
1	1	Covered	T77,T435,T546

 LINE       33107
 SUB-EXPRESSION (addr_hit[155] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T84,T63
1	1	Covered	T77,T435,T546

 LINE       33107
 SUB-EXPRESSION (addr_hit[156] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T84,T63
1	1	Covered	T76,T77,T435

 LINE       33107
 SUB-EXPRESSION (addr_hit[157] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T84,T63
1	1	Covered	T76,T77,T445

 LINE       33107
 SUB-EXPRESSION (addr_hit[158] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T84,T63
1	1	Covered	T77,T444,T550

 LINE       33107
 SUB-EXPRESSION (addr_hit[159] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T84,T63
1	1	Covered	T76,T77,T445

 LINE       33107
 SUB-EXPRESSION (addr_hit[160] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T84,T63
1	1	Covered	T77,T79,T444

 LINE       33107
 SUB-EXPRESSION (addr_hit[161] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T84,T63
1	1	Covered	T77,T473,T252

 LINE       33107
 SUB-EXPRESSION (addr_hit[162] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T84,T63
1	1	Covered	T77,T550,T456

 LINE       33107
 SUB-EXPRESSION (addr_hit[163] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T84,T63
1	1	Covered	T76,T77,T79

 LINE       33107
 SUB-EXPRESSION (addr_hit[164] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T84,T63
1	1	Covered	T77,T79,T473

 LINE       33107
 SUB-EXPRESSION (addr_hit[165] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T84,T63
1	1	Covered	T77,T79,T473

 LINE       33107
 SUB-EXPRESSION (addr_hit[166] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T84,T63
1	1	Covered	T77,T79,T252

 LINE       33107
 SUB-EXPRESSION (addr_hit[167] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T18,T84
1	1	Covered	T77,T444,T456

 LINE       33107
 SUB-EXPRESSION (addr_hit[168] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T84,T63
1	1	Covered	T77,T474,T435

 LINE       33107
 SUB-EXPRESSION (addr_hit[169] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T84,T63
1	1	Covered	T77,T444,T456

 LINE       33107
 SUB-EXPRESSION (addr_hit[170] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T84,T63
1	1	Covered	T77,T79,T445

 LINE       33107
 SUB-EXPRESSION (addr_hit[171] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T84,T63
1	1	Covered	T77,T78,T79

 LINE       33107
 SUB-EXPRESSION (addr_hit[172] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T84,T63
1	1	Covered	T79,T252,T445

 LINE       33107
 SUB-EXPRESSION (addr_hit[173] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T84,T63
1	1	Covered	T77,T473,T435

 LINE       33107
 SUB-EXPRESSION (addr_hit[174] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T84,T63
1	1	Covered	T77,T473,T445

 LINE       33107
 SUB-EXPRESSION (addr_hit[175] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T77,T444,T435

 LINE       33107
 SUB-EXPRESSION (addr_hit[176] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T76,T456,T435

 LINE       33107
 SUB-EXPRESSION (addr_hit[177] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T84,T63
1	1	Covered	T77,T435,T546

 LINE       33107
 SUB-EXPRESSION (addr_hit[178] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T84,T63
1	1	Covered	T77,T79,T473

 LINE       33107
 SUB-EXPRESSION (addr_hit[179] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T84,T63
1	1	Covered	T77,T79,T435

 LINE       33107
 SUB-EXPRESSION (addr_hit[180] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T84,T63
1	1	Covered	T77,T435,T546

 LINE       33107
 SUB-EXPRESSION (addr_hit[181] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T84,T63
1	1	Covered	T76,T77,T79

 LINE       33107
 SUB-EXPRESSION (addr_hit[182] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T19,T84
1	1	Covered	T77,T435,T546

 LINE       33107
 SUB-EXPRESSION (addr_hit[183] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T19,T84
1	1	Covered	T76,T77,T79

 LINE       33107
 SUB-EXPRESSION (addr_hit[184] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T84,T63
1	1	Covered	T77,T445,T435

 LINE       33107
 SUB-EXPRESSION (addr_hit[185] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T84,T63
1	1	Covered	T77,T79,T474

 LINE       33107
 SUB-EXPRESSION (addr_hit[186] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T84,T63
1	1	Covered	T77,T79,T473

 LINE       33107
 SUB-EXPRESSION (addr_hit[187] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T77,T473,T474

 LINE       33107
 SUB-EXPRESSION (addr_hit[188] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T77,T473,T435

 LINE       33107
 SUB-EXPRESSION (addr_hit[189] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T84,T63
1	1	Covered	T77,T473,T444

 LINE       33107
 SUB-EXPRESSION (addr_hit[190] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T84,T63
1	1	Covered	T77,T473,T456

 LINE       33107
 SUB-EXPRESSION (addr_hit[191] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T76,T77,T79

 LINE       33107
 SUB-EXPRESSION (addr_hit[192] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T84,T63
1	1	Covered	T77,T550,T435

 LINE       33107
 SUB-EXPRESSION (addr_hit[193] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T84,T63
1	1	Covered	T77,T79,T473

 LINE       33107
 SUB-EXPRESSION (addr_hit[194] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T84,T63
1	1	Covered	T77,T444,T435

 LINE       33107
 SUB-EXPRESSION (addr_hit[195] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T84,T63
1	1	Covered	T76,T77,T79

 LINE       33107
 SUB-EXPRESSION (addr_hit[196] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T84,T63
1	1	Covered	T77,T456,T435

 LINE       33107
 SUB-EXPRESSION (addr_hit[197] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T84,T63
1	1	Covered	T77,T79,T444

 LINE       33107
 SUB-EXPRESSION (addr_hit[198] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T84,T63
1	1	Covered	T76,T77,T79

 LINE       33107
 SUB-EXPRESSION (addr_hit[199] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T84,T63
1	1	Covered	T77,T473,T549

 LINE       33107
 SUB-EXPRESSION (addr_hit[200] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T84,T63
1	1	Covered	T76,T77,T474

 LINE       33107
 SUB-EXPRESSION (addr_hit[201] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T63,T315,T316
1	1	Covered	T76,T77,T435

 LINE       33107
 SUB-EXPRESSION (addr_hit[202] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T63,T315,T316
1	1	Covered	T77,T79,T546

 LINE       33107
 SUB-EXPRESSION (addr_hit[203] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T63,T315,T316
1	1	Covered	T76,T77,T473

 LINE       33107
 SUB-EXPRESSION (addr_hit[204] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T63,T315,T316
1	1	Covered	T77,T79,T473

 LINE       33107
 SUB-EXPRESSION (addr_hit[205] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T63,T315,T316
1	1	Covered	T76,T77,T79

 LINE       33107
 SUB-EXPRESSION (addr_hit[206] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T63,T315,T316
1	1	Covered	T77,T252,T445

 LINE       33107
 SUB-EXPRESSION (addr_hit[207] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T63,T315,T316
1	1	Covered	T76,T77,T456

 LINE       33107
 SUB-EXPRESSION (addr_hit[208] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T63,T315,T316
1	1	Covered	T77,T79,T435

 LINE       33107
 SUB-EXPRESSION (addr_hit[209] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T47,T63,T315
1	1	Covered	T76,T77,T79

 LINE       33107
 SUB-EXPRESSION (addr_hit[210] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T63,T315,T316
1	1	Covered	T76,T77,T79

 LINE       33107
 SUB-EXPRESSION (addr_hit[211] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T63,T315,T316
1	1	Covered	T77,T79,T435

 LINE       33107
 SUB-EXPRESSION (addr_hit[212] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T63,T315,T316
1	1	Covered	T76,T77,T252

 LINE       33107
 SUB-EXPRESSION (addr_hit[213] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T63,T315,T316
1	1	Covered	T76,T77,T550

 LINE       33107
 SUB-EXPRESSION (addr_hit[214] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T63,T315,T316
1	1	Covered	T77,T79,T445

 LINE       33107
 SUB-EXPRESSION (addr_hit[215] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T63,T315,T316
1	1	Covered	T77,T79,T435

 LINE       33107
 SUB-EXPRESSION (addr_hit[216] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T63,T315,T316
1	1	Covered	T76,T77,T474

 LINE       33107
 SUB-EXPRESSION (addr_hit[217] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T63,T315,T316
1	1	Covered	T76,T77,T473

 LINE       33107
 SUB-EXPRESSION (addr_hit[218] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T63,T315,T316
1	1	Covered	T76,T77,T79

 LINE       33107
 SUB-EXPRESSION (addr_hit[219] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T63,T315,T316
1	1	Covered	T76,T77,T444

 LINE       33107
 SUB-EXPRESSION (addr_hit[220] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T63,T315,T316
1	1	Covered	T77,T473,T445

 LINE       33107
 SUB-EXPRESSION (addr_hit[221] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T63,T315,T316
1	1	Covered	T76,T77,T79

 LINE       33107
 SUB-EXPRESSION (addr_hit[222] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T63,T315,T316
1	1	Covered	T435,T549,T546

 LINE       33107
 SUB-EXPRESSION (addr_hit[223] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T63,T315,T316
1	1	Covered	T77,T79,T474

 LINE       33107
 SUB-EXPRESSION (addr_hit[224] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T63,T315,T316
1	1	Covered	T77,T444,T445

 LINE       33107
 SUB-EXPRESSION (addr_hit[225] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T63,T315,T316
1	1	Covered	T76,T77,T435

 LINE       33107
 SUB-EXPRESSION (addr_hit[226] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T63,T315,T316
1	1	Covered	T77,T473,T456

 LINE       33107
 SUB-EXPRESSION (addr_hit[227] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T63,T315,T316
1	1	Covered	T77,T444,T445

 LINE       33107
 SUB-EXPRESSION (addr_hit[228] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T63,T315,T316
1	1	Covered	T76,T77,T79

 LINE       33107
 SUB-EXPRESSION (addr_hit[229] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T63,T315,T316
1	1	Covered	T77,T445,T435

 LINE       33107
 SUB-EXPRESSION (addr_hit[230] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T63,T315,T316
1	1	Covered	T76,T77,T550

 LINE       33107
 SUB-EXPRESSION (addr_hit[231] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T63,T315,T316
1	1	Covered	T77,T79,T550

 LINE       33107
 SUB-EXPRESSION (addr_hit[232] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T18,T63,T315
1	1	Covered	T77,T252,T456

 LINE       33107
 SUB-EXPRESSION (addr_hit[233] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T63,T315,T316
1	1	Covered	T76,T77,T79

 LINE       33107
 SUB-EXPRESSION (addr_hit[234] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T6,T18
1	1	Covered	T76,T77,T79

 LINE       33107
 SUB-EXPRESSION (addr_hit[235] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T63,T315,T316
1	1	Covered	T76,T77,T456

 LINE       33107
 SUB-EXPRESSION (addr_hit[236] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T63,T315,T316
1	1	Covered	T77,T79,T444

 LINE       33107
 SUB-EXPRESSION (addr_hit[237] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T63,T315,T316
1	1	Covered	T77,T456,T435

 LINE       33107
 SUB-EXPRESSION (addr_hit[238] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T63,T315,T316
1	1	Covered	T77,T456,T435

 LINE       33107
 SUB-EXPRESSION (addr_hit[239] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T63,T315,T316
1	1	Covered	T77,T79,T456

 LINE       33107
 SUB-EXPRESSION (addr_hit[240] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T63,T315,T316
1	1	Covered	T76,T77,T435

 LINE       33107
 SUB-EXPRESSION (addr_hit[241] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T63,T315,T316
1	1	Covered	T77,T79,T252

 LINE       33107
 SUB-EXPRESSION (addr_hit[242] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T63,T315,T316
1	1	Covered	T76,T77,T252

 LINE       33107
 SUB-EXPRESSION (addr_hit[243] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T63,T315,T316
1	1	Covered	T77,T252,T444

 LINE       33107
 SUB-EXPRESSION (addr_hit[244] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T63,T315,T316
1	1	Covered	T76,T77,T473

 LINE       33107
 SUB-EXPRESSION (addr_hit[245] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T63,T315,T316
1	1	Covered	T77,T79,T546

 LINE       33107
 SUB-EXPRESSION (addr_hit[246] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T63,T315,T316
1	1	Covered	T77,T78,T435

 LINE       33107
 SUB-EXPRESSION (addr_hit[247] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T63,T315,T316
1	1	Covered	T76,T77,T79

 LINE       33107
 SUB-EXPRESSION (addr_hit[248] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T63,T315,T316
1	1	Covered	T76,T77,T445

 LINE       33107
 SUB-EXPRESSION (addr_hit[249] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T63,T315,T316
1	1	Covered	T76,T77,T445

 LINE       33107
 SUB-EXPRESSION (addr_hit[250] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T63,T315,T316
1	1	Covered	T77,T79,T456

 LINE       33107
 SUB-EXPRESSION (addr_hit[251] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T63,T315,T316
1	1	Covered	T76,T77,T435

 LINE       33107
 SUB-EXPRESSION (addr_hit[252] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T63,T315,T316
1	1	Covered	T77,T79,T444

 LINE       33107
 SUB-EXPRESSION (addr_hit[253] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T46,T63,T315
1	1	Covered	T77,T79,T550

 LINE       33107
 SUB-EXPRESSION (addr_hit[254] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T63,T315,T316
1	1	Covered	T77,T252,T474

 LINE       33107
 SUB-EXPRESSION (addr_hit[255] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T63,T315,T316
1	1	Covered	T77,T79,T252

 LINE       33107
 SUB-EXPRESSION (addr_hit[256] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T63,T315,T316
1	1	Covered	T77,T435,T546

 LINE       33107
 SUB-EXPRESSION (addr_hit[257] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T63,T315,T316
1	1	Covered	T76,T77,T79

 LINE       33107
 SUB-EXPRESSION (addr_hit[258] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T63,T315,T316
1	1	Covered	T76,T77,T252

 LINE       33107
 SUB-EXPRESSION (addr_hit[259] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T63,T315,T316
1	1	Covered	T77,T435,T546

 LINE       33107
 SUB-EXPRESSION (addr_hit[260] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T63,T315,T316
1	1	Covered	T76,T77,T473

 LINE       33107
 SUB-EXPRESSION (addr_hit[261] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T63,T315,T316
1	1	Covered	T77,T444,T456

 LINE       33107
 SUB-EXPRESSION (addr_hit[262] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T63,T315,T316
1	1	Covered	T77,T550,T456

 LINE       33107
 SUB-EXPRESSION (addr_hit[263] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T63,T315,T316
1	1	Covered	T77,T435,T546

 LINE       33107
 SUB-EXPRESSION (addr_hit[264] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T63,T315,T316
1	1	Covered	T77,T444,T435

 LINE       33107
 SUB-EXPRESSION (addr_hit[265] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T63,T315,T316
1	1	Covered	T77,T546,T553