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LINE 36611
EXPRESSION (addr_hit[540] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T4,T5,T6 |
1 | 0 | 1 | Covered | T4,T5,T6 |
1 | 1 | 0 | Covered | T546,T627,T532 |
1 | 1 | 1 | Covered | T1,T3,T16 |
LINE 36613
EXPRESSION (addr_hit[541] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T4,T5,T6 |
1 | 0 | 1 | Covered | T4,T5,T6 |
1 | 1 | 0 | Covered | T476,T561,T428 |
1 | 1 | 1 | Covered | T15,T392,T436 |
LINE 36615
EXPRESSION (addr_hit[542] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T4,T5,T6 |
1 | 0 | 1 | Covered | T4,T5,T6 |
1 | 1 | 0 | Covered | T444,T561,T447 |
1 | 1 | 1 | Covered | T12,T392,T438 |
LINE 36617
EXPRESSION (addr_hit[543] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T4,T5,T6 |
1 | 0 | 1 | Covered | T4,T5,T6 |
1 | 1 | 0 | Covered | T546,T561,T482 |
1 | 1 | 1 | Covered | T2,T13,T14 |
LINE 36621
EXPRESSION (addr_hit[544] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T4,T5,T6 |
1 | 0 | 1 | Covered | T4,T5,T6 |
1 | 1 | 0 | Covered | T579,T530,T556 |
1 | 1 | 1 | Covered | T443,T392,T436 |
LINE 36625
EXPRESSION (addr_hit[545] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T4,T5,T6 |
1 | 0 | 1 | Covered | T4,T5,T6 |
1 | 1 | 0 | Covered | T459,T479,T519 |
1 | 1 | 1 | Covered | T444,T445,T392 |
LINE 36629
EXPRESSION (addr_hit[546] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T4,T5,T6 |
1 | 0 | 1 | Covered | T4,T5,T6 |
1 | 1 | 0 | Covered | T546,T438,T655 |
1 | 1 | 1 | Covered | T11,T392,T428 |
LINE 36633
EXPRESSION (addr_hit[547] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T4,T5,T6 |
1 | 0 | 1 | Covered | T4,T5,T6 |
1 | 1 | 0 | Covered | T443,T561,T656 |
1 | 1 | 1 | Covered | T446,T392,T438 |
LINE 36637
EXPRESSION (addr_hit[548] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T4,T5,T6 |
1 | 0 | 1 | Covered | T4,T5,T6 |
1 | 1 | 0 | Covered | T79,T554,T555 |
1 | 1 | 1 | Covered | T1,T3,T16 |
LINE 36641
EXPRESSION (addr_hit[549] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T4,T5,T6 |
1 | 0 | 1 | Covered | T4,T5,T6 |
1 | 1 | 0 | Covered | T556,T564,T581 |
1 | 1 | 1 | Covered | T15,T392,T447 |
LINE 36645
EXPRESSION (addr_hit[550] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T4,T5,T6 |
1 | 0 | 1 | Covered | T4,T5,T6 |
1 | 1 | 0 | Covered | T561,T458,T455 |
1 | 1 | 1 | Covered | T12,T392,T428 |
LINE 36649
EXPRESSION (addr_hit[551] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T4,T5,T6 |
1 | 0 | 1 | Covered | T4,T5,T6 |
1 | 1 | 0 | Covered | T564,T581,T509 |
1 | 1 | 1 | Covered | T444,T392,T438 |
LINE 36651
EXPRESSION (addr_hit[552] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T4,T5,T6 |
1 | 0 | 1 | Covered | T4,T5,T6 |
1 | 1 | 0 | Covered | T477,T455,T479 |
1 | 1 | 1 | Covered | T7,T421,T8 |
LINE 36653
EXPRESSION (addr_hit[553] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T4,T5,T6 |
1 | 0 | 1 | Covered | T4,T5,T6 |
1 | 1 | 0 | Covered | T546,T561,T477 |
1 | 1 | 1 | Covered | T392,T393,T454 |
LINE 36655
EXPRESSION (addr_hit[554] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T4,T5,T6 |
1 | 0 | 1 | Covered | T4,T5,T6 |
1 | 1 | 0 | Covered | T444,T554,T560 |
1 | 1 | 1 | Covered | T392,T455,T393 |
LINE 36657
EXPRESSION (addr_hit[555] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T4,T5,T6 |
1 | 0 | 1 | Covered | T4,T5,T6 |
1 | 1 | 0 | Covered | T561,T458,T480 |
1 | 1 | 1 | Covered | T456,T392,T457 |
LINE 36659
EXPRESSION (addr_hit[556] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T4,T5,T6 |
1 | 0 | 1 | Covered | T4,T5,T6 |
1 | 1 | 0 | Covered | T546,T561,T477 |
1 | 1 | 1 | Covered | T444,T392,T458 |
LINE 36661
EXPRESSION (addr_hit[557] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T4,T5,T6 |
1 | 0 | 1 | Covered | T4,T5,T6 |
1 | 1 | 0 | Covered | T560,T567,T657 |
1 | 1 | 1 | Covered | T392,T458,T393 |
LINE 36663
EXPRESSION (addr_hit[558] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T4,T5,T6 |
1 | 0 | 1 | Covered | T4,T5,T6 |
1 | 1 | 0 | Covered | T444,T561,T478 |
1 | 1 | 1 | Covered | T392,T459,T438 |
LINE 36665
EXPRESSION (addr_hit[559] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T4,T5,T6 |
1 | 0 | 1 | Covered | T4,T5,T6 |
1 | 1 | 0 | Covered | T546,T548,T584 |
1 | 1 | 1 | Covered | T2,T13,T14 |
LINE 36668
EXPRESSION (addr_hit[560] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T4,T5,T6 |
1 | 0 | 1 | Covered | T4,T5,T6 |
1 | 1 | 0 | Covered | T444,T476,T438 |
1 | 1 | 1 | Covered | T392,T459,T476 |
LINE 36671
EXPRESSION (addr_hit[561] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T4,T5,T6 |
1 | 0 | 1 | Covered | T4,T5,T6 |
1 | 1 | 0 | Covered | T546,T499,T555 |
1 | 1 | 1 | Covered | T392,T393,T480 |
LINE 36674
EXPRESSION (addr_hit[562] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T4,T5,T6 |
1 | 0 | 1 | Covered | T4,T5,T6 |
1 | 1 | 0 | Covered | T438,T554,T518 |
1 | 1 | 1 | Covered | T11,T392,T447 |
LINE 36677
EXPRESSION (addr_hit[563] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T4,T5,T6 |
1 | 0 | 1 | Covered | T4,T5,T6 |
1 | 1 | 0 | Covered | T501,T459,T485 |
1 | 1 | 1 | Covered | T435,T501,T392 |
LINE 36680
EXPRESSION (addr_hit[564] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T4,T5,T6 |
1 | 0 | 1 | Covered | T4,T5,T6 |
1 | 1 | 0 | Covered | T546,T458,T447 |
1 | 1 | 1 | Covered | T1,T3,T16 |
LINE 36683
EXPRESSION (addr_hit[565] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T4,T5,T6 |
1 | 0 | 1 | Covered | T4,T5,T6 |
1 | 1 | 0 | Covered | T645,T560,T492 |
1 | 1 | 1 | Covered | T15,T392,T542 |
LINE 36686
EXPRESSION (addr_hit[566] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T4,T5,T6 |
1 | 0 | 1 | Covered | T4,T5,T6 |
1 | 1 | 0 | Covered | T546,T561,T438 |
1 | 1 | 1 | Covered | T12,T392,T520 |
LINE 36689
EXPRESSION (addr_hit[567] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T4,T5,T6 |
1 | 0 | 1 | Covered | T4,T5,T6 |
1 | 1 | 0 | Covered | T428,T447,T603 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 40162
EXPRESSION (reg_busy_sel | shadow_busy)
------1----- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |