Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.alert_handler_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	126562	1			T73	7		T74	78		T75	13
values[2]	7940	1			T73	1		T74	8		T128	60
values[3]	2951	1			T128	58		T543	40		T581	1
values[4]	1826	1			T128	51		T543	9		T418	57
values[5]	1305	1			T128	35		T418	22		T855	1
values[6]	1044	1			T128	11		T418	15		T855	1
values[7]	718	1			T418	34		T855	1		T856	6
values[8]	518	1			T418	38		T855	1		T856	5
values[9]	517	1			T418	31		T855	1		T856	11
values[10]	468	1			T418	23		T855	1		T856	5
values[11]	402	1			T418	28		T855	1		T856	16
values[12]	350	1			T418	6		T855	1		T856	7
values[13]	358	1			T418	1		T855	1		T856	9
values[14]	363	1			T855	1		T856	17		T857	1
values[15]	371	1			T855	1		T856	3		T857	1
values[16]	319	1			T855	1		T856	4		T857	1
values[17]	296	1			T855	1		T856	3		T857	1
values[18]	320	1			T855	1		T856	6		T857	1
values[19]	345	1			T855	1		T856	9		T857	1
values[20]	340	1			T855	1		T856	6		T857	1
values[21]	327	1			T855	1		T856	3		T857	1
values[22]	357	1			T855	1		T856	5		T857	1
values[23]	373	1			T855	1		T856	23		T857	1
values[24]	322	1			T855	1		T856	7		T857	1
values[25]	292	1			T855	1		T856	4		T857	1
values[26]	303	1			T855	1		T856	6		T857	1
values[27]	331	1			T855	1		T856	6		T857	2
values[28]	337	1			T855	1		T856	3		T857	1
values[29]	344	1			T855	1		T856	7		T857	1
values[30]	338	1			T855	1		T856	6		T857	1
values[31]	380	1			T855	1		T856	7		T857	1
values[32]	315	1			T855	1		T856	6		T857	1
values[33]	360	1			T855	1		T856	11		T857	1
values[34]	315	1			T855	1		T856	8		T857	1
values[35]	284	1			T855	1		T856	4		T857	1
values[36]	362	1			T855	1		T856	5		T857	1
values[37]	376	1			T855	1		T856	6		T857	1
values[38]	329	1			T855	1		T856	5		T857	1
values[39]	306	1			T855	1		T856	3		T857	1
values[40]	301	1			T855	1		T856	7		T857	1
values[41]	337	1			T855	1		T856	7		T857	1
values[42]	316	1			T855	1		T856	3		T857	1
values[43]	291	1			T855	1		T856	7		T857	1
values[44]	324	1			T855	1		T856	3		T857	1
values[45]	329	1			T855	1		T856	11		T857	1
values[46]	327	1			T855	1		T856	47		T857	1
values[47]	313	1			T855	1		T856	9		T857	1
values[48]	286	1			T855	1		T856	5		T857	1
values[49]	288	1			T855	1		T856	5		T857	1
values[50]	264	1			T855	1		T856	2		T857	1
values[51]	336	1			T855	1		T856	9		T857	1
values[52]	352	1			T855	1		T856	8		T857	1
values[53]	295	1			T855	1		T856	4		T857	1
values[54]	327	1			T855	1		T856	3		T857	1
values[55]	272	1			T855	1		T856	6		T857	1
values[56]	292	1			T855	1		T856	9		T857	1
values[57]	259	1			T855	1		T856	5		T857	1
values[58]	248	1			T855	1		T856	10		T857	1
values[59]	233	1			T855	1		T856	5		T857	1
values[60]	223	1			T855	1		T856	14		T857	1
values[61]	210	1			T855	1		T856	6		T857	1
values[62]	230	1			T855	1		T856	12		T857	1
values[63]	278	1			T855	1		T856	11		T857	1
values[64]	209	1			T855	1		T856	6		T857	1
values[65]	213	1			T855	1		T856	3		T857	1
values[66]	206	1			T855	1		T856	11		T857	1
values[67]	186	1			T855	1		T856	5		T857	1
values[68]	139	1			T855	1		T856	4		T857	1
values[69]	136	1			T855	1		T856	9		T857	1
values[70]	151	1			T855	1		T856	9		T857	1
values[71]	142	1			T855	1		T856	4		T857	1
values[72]	117	1			T855	1		T856	12		T857	2
values[73]	119	1			T855	1		T857	1		T858	6
values[74]	96	1			T855	1		T857	1		T858	1
values[75]	100	1			T855	1		T857	1		T858	8
values[76]	94	1			T855	1		T857	1		T858	2
values[77]	89	1			T855	1		T857	1		T858	2
values[78]	60	1			T855	1		T857	1		T858	2
values[79]	72	1			T855	1		T857	1		T858	1
values[80]	77	1			T855	1		T857	1		T858	1
values[81]	70	1			T855	1		T857	1		T858	9
values[82]	66	1			T855	7		T857	1		T858	5
values[83]	73	1			T855	2		T857	1		T858	3
values[84]	46	1			T855	2		T857	1		T858	1
values[85]	63	1			T855	4		T857	1		T858	4
values[86]	65	1			T855	1		T857	1		T858	1
values[87]	51	1			T855	3		T857	1		T858	3
values[88]	66	1			T855	6		T857	2		T858	1
values[89]	68	1			T855	3		T857	1		T858	1
values[90]	80	1			T855	5		T857	1		T858	4
values[91]	79	1			T855	9		T857	1		T858	1
values[92]	100	1			T855	11		T857	1		T858	11
values[93]	85	1			T855	2		T857	1		T858	2
values[94]	73	1			T855	2		T857	1		T858	6
values[95]	62	1			T855	1		T857	1		T858	4
values[96]	73	1			T855	5		T857	1		T858	6
values[97]	73	1			T855	1		T857	1		T858	4
values[98]	79	1			T855	3		T857	1		T858	4
values[99]	62	1			T855	5		T857	1		T858	6
values[100]	61	1			T855	1		T857	1		T858	9
values[101]	60	1			T855	1		T857	1		T858	2
values[102]	66	1			T855	1		T857	1		T858	6
values[103]	84	1			T855	1		T857	3		T858	2
values[104]	87	1			T855	2		T857	3		T858	5
values[105]	78	1			T855	3		T857	1		T858	3
values[106]	81	1			T855	1		T857	1		T858	1
values[107]	72	1			T855	2		T857	1		T858	2
values[108]	78	1			T855	1		T857	1		T858	3
values[109]	63	1			T855	2		T857	1		T858	2
values[110]	83	1			T855	2		T857	1		T858	5
values[111]	64	1			T855	3		T857	1		T858	2
values[112]	68	1			T855	1		T857	1		T858	4
values[113]	72	1			T855	2		T857	10		T858	2
values[114]	76	1			T855	2		T857	2		T858	4
values[115]	64	1			T855	1		T857	1		T858	1
values[116]	78	1			T855	6		T857	4		T858	5
values[117]	64	1			T855	1		T857	2		T858	4
values[118]	57	1			T855	4		T857	1		T858	2
values[119]	56	1			T855	1		T857	2		T858	1
values[120]	58	1			T855	1		T857	2		T858	7
values[121]	50	1			T855	1		T857	1		T858	4
values[122]	62	1			T855	2		T857	2		T858	1
values[123]	78	1			T855	2		T857	3		T858	19
values[124]	81	1			T855	3		T857	1		T858	13
values[125]	98	1			T855	2		T857	1		T858	11
values[126]	142	1			T855	8		T857	3		T858	31
values[127]	870	1			T855	23		T857	35		T858	46
values[128]	7857	1			T855	299		T857	391		T858	13

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	150232	1			T73	4		T74	92		T75	23
values[2]	4079	1			T74	2		T128	74		T536	2
values[3]	1870	1			T128	59		T536	2		T430	6
values[4]	1466	1			T128	45		T536	2		T430	20
values[5]	1236	1			T128	40		T536	2		T430	24
values[6]	1031	1			T128	23		T536	2		T430	18
values[7]	993	1			T128	29		T536	2		T430	15
values[8]	841	1			T128	37		T536	2		T430	14
values[9]	765	1			T128	40		T536	2		T430	7
values[10]	742	1			T128	31		T536	2		T430	5
values[11]	702	1			T128	22		T536	2		T541	1
values[12]	771	1			T128	20		T536	2		T541	1
values[13]	632	1			T128	27		T536	2		T541	1
values[14]	616	1			T128	36		T536	2		T541	1
values[15]	535	1			T128	24		T536	2		T541	1
values[16]	471	1			T128	10		T536	2		T541	1
values[17]	335	1			T536	2		T541	1		T859	2
values[18]	293	1			T536	2		T541	1		T859	2
values[19]	264	1			T536	2		T541	1		T859	2
values[20]	258	1			T536	2		T541	1		T859	4
values[21]	248	1			T536	2		T541	1		T859	8
values[22]	209	1			T536	2		T541	1		T859	5
values[23]	230	1			T536	2		T541	1		T859	3
values[24]	204	1			T536	2		T541	1		T859	1
values[25]	233	1			T536	2		T541	1		T859	4
values[26]	213	1			T536	2		T541	1		T859	10
values[27]	188	1			T536	2		T541	1		T859	7
values[28]	191	1			T536	2		T541	1		T859	1
values[29]	155	1			T536	2		T541	1		T859	2
values[30]	168	1			T536	2		T541	1		T859	6
values[31]	193	1			T536	2		T541	1		T859	13
values[32]	169	1			T536	2		T541	1		T859	7
values[33]	206	1			T536	2		T541	1		T859	10
values[34]	207	1			T536	2		T541	1		T859	3
values[35]	141	1			T536	2		T541	1		T859	2
values[36]	135	1			T536	2		T541	1		T859	1
values[37]	149	1			T536	2		T541	1		T859	2
values[38]	111	1			T536	2		T541	1		T859	2
values[39]	99	1			T536	2		T541	1		T859	3
values[40]	97	1			T536	2		T541	1		T859	1
values[41]	100	1			T536	2		T541	1		T859	5
values[42]	123	1			T536	2		T541	1		T859	3
values[43]	113	1			T536	2		T541	1		T859	3
values[44]	94	1			T536	2		T541	1		T859	2
values[45]	88	1			T536	2		T541	1		T859	8
values[46]	90	1			T536	2		T541	1		T859	7
values[47]	96	1			T536	2		T541	1		T859	5
values[48]	99	1			T536	2		T541	1		T859	5
values[49]	80	1			T536	2		T541	1		T859	4
values[50]	89	1			T536	2		T541	1		T859	6
values[51]	83	1			T536	2		T541	1		T859	3
values[52]	79	1			T536	2		T541	1		T859	3
values[53]	85	1			T536	2		T541	1		T859	7
values[54]	128	1			T536	2		T541	1		T859	40
values[55]	121	1			T536	2		T541	1		T859	27
values[56]	126	1			T536	2		T541	1		T859	40
values[57]	101	1			T536	2		T541	1		T859	19
values[58]	94	1			T536	2		T541	1		T859	7
values[59]	96	1			T536	2		T541	1		T859	2
values[60]	109	1			T536	2		T541	1		T859	1
values[61]	102	1			T536	2		T541	1		T859	2
values[62]	93	1			T536	2		T541	1		T859	4
values[63]	118	1			T536	2		T541	1		T859	5
values[64]	115	1			T536	2		T541	1		T859	2
values[65]	96	1			T536	2		T541	1		T859	5
values[66]	89	1			T536	2		T541	1		T859	17
values[67]	89	1			T536	2		T541	1		T859	23
values[68]	94	1			T536	2		T541	1		T859	13
values[69]	86	1			T536	2		T541	1		T859	4
values[70]	92	1			T536	2		T541	1		T859	3
values[71]	95	1			T536	2		T541	1		T859	5
values[72]	87	1			T536	2		T541	1		T859	4
values[73]	94	1			T536	2		T541	1		T859	3
values[74]	95	1			T536	2		T541	1		T859	3
values[75]	86	1			T536	2		T541	1		T859	4
values[76]	107	1			T536	2		T541	1		T859	2
values[77]	87	1			T536	2		T541	1		T860	8
values[78]	75	1			T536	2		T541	1		T860	3
values[79]	80	1			T536	2		T541	1		T860	3
values[80]	87	1			T536	2		T541	1		T860	2
values[81]	76	1			T536	2		T541	1		T860	2
values[82]	86	1			T536	2		T541	1		T860	5
values[83]	104	1			T536	2		T541	1		T860	5
values[84]	99	1			T536	2		T541	1		T860	6
values[85]	102	1			T536	2		T541	1		T860	10
values[86]	95	1			T536	2		T541	1		T860	7
values[87]	96	1			T536	2		T541	1		T860	10
values[88]	97	1			T536	2		T541	1		T860	14
values[89]	84	1			T536	2		T541	1		T860	9
values[90]	110	1			T536	2		T541	1		T860	12
values[91]	100	1			T536	2		T541	1		T860	7
values[92]	94	1			T536	2		T541	1		T860	3
values[93]	106	1			T536	2		T541	1		T860	4
values[94]	111	1			T536	2		T541	1		T860	10
values[95]	94	1			T536	2		T541	1		T860	3
values[96]	99	1			T536	2		T541	1		T860	9
values[97]	78	1			T536	2		T541	1		T860	7
values[98]	84	1			T536	3		T541	1		T860	5
values[99]	100	1			T536	3		T541	1		T860	3
values[100]	110	1			T536	3		T541	1		T860	8
values[101]	105	1			T536	2		T541	1		T860	6
values[102]	113	1			T536	3		T541	1		T860	5
values[103]	116	1			T536	5		T541	1		T860	4
values[104]	104	1			T536	2		T541	1		T860	4
values[105]	119	1			T536	2		T541	1		T860	7
values[106]	103	1			T536	4		T541	1		T860	5
values[107]	128	1			T536	3		T541	1		T860	8
values[108]	109	1			T536	5		T541	1		T860	6
values[109]	119	1			T536	2		T541	1		T860	7
values[110]	133	1			T536	4		T541	3		T860	12
values[111]	119	1			T536	2		T541	3		T860	7
values[112]	128	1			T536	2		T541	4		T860	8
values[113]	151	1			T536	4		T541	2		T860	10
values[114]	119	1			T536	2		T541	1		T860	14
values[115]	124	1			T536	2		T541	1		T860	7
values[116]	116	1			T536	6		T541	1		T860	10
values[117]	115	1			T536	8		T541	1		T860	4
values[118]	132	1			T536	6		T541	5		T860	4
values[119]	134	1			T536	12		T541	2		T860	10
values[120]	139	1			T536	5		T541	1		T860	14
values[121]	129	1			T536	5		T541	3		T860	7
values[122]	162	1			T536	3		T541	2		T860	18
values[123]	197	1			T536	4		T541	1		T860	20
values[124]	287	1			T536	3		T541	4		T860	36
values[125]	630	1			T536	6		T541	1		T860	68
values[126]	1244	1			T536	30		T541	25		T860	105
values[127]	4157	1			T536	242		T541	154		T860	71
values[128]	7242	1			T536	472		T541	209		T860	7

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	127604	1			T73	3		T74	77		T75	11
values[2]	7342	1			T74	4		T128	111		T440	1
values[3]	2657	1			T128	83		T536	1		T537	39
values[4]	1586	1			T128	31		T536	1		T537	30
values[5]	1108	1			T128	26		T536	1		T537	18
values[6]	780	1			T128	6		T536	1		T537	19
values[7]	647	1			T128	3		T536	1		T537	14
values[8]	584	1			T536	1		T537	5		T750	7
values[9]	446	1			T536	1		T537	2		T750	13
values[10]	412	1			T536	1		T750	4		T860	8
values[11]	321	1			T536	1		T750	8		T860	6
values[12]	315	1			T536	1		T750	8		T860	4
values[13]	322	1			T536	1		T750	4		T860	2
values[14]	329	1			T536	1		T750	7		T860	5
values[15]	275	1			T536	1		T750	10		T860	4
values[16]	281	1			T536	1		T750	4		T860	1
values[17]	313	1			T536	1		T750	9		T860	1
values[18]	282	1			T536	1		T750	10		T860	4
values[19]	314	1			T536	1		T750	3		T860	1
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