Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.95	95.45	93.92	95.53		94.77	96.47	99.59

Total tests in report: 2885

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
39.61	39.61	45.05	45.05	43.14	43.14	31.67	31.67			58.03	58.03	59.44	59.44	0.34	0.34	/workspace/coverage/default/85.chip_sw_all_escalation_resets.2426148469
48.57	8.96	52.60	7.55	52.16	9.02	34.27	2.60			66.23	8.19	85.66	26.22	0.51	0.16	/workspace/coverage/default/1.chip_jtag_csr_rw.3586513323
55.38	6.81	61.28	8.68	56.13	3.98	40.83	6.56			66.51	0.29	85.66	0.00	21.84	21.34	/workspace/coverage/cover_reg_top/78.xbar_stress_all_with_reset_error.1005254776
61.24	5.87	73.60	12.32	64.35	8.22	44.29	3.47			77.72	11.21	85.66	0.00	21.84	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_0.970777534
64.91	3.67	73.60	0.00	64.35	0.00	44.29	0.00			77.72	0.00	85.66	0.00	43.85	22.01	/workspace/coverage/cover_reg_top/62.xbar_access_same_device_slow_rsp.4122362913
68.21	3.30	79.63	6.04	68.62	4.27	48.25	3.96			79.76	2.04	89.16	3.50	43.85	0.00	/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.2108161258
71.07	2.86	79.64	0.01	68.65	0.02	65.34	17.09			79.78	0.02	89.16	0.00	43.85	0.00	/workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.2405019984
73.74	2.67	82.21	2.57	76.04	7.39	65.70	0.36			84.59	4.81	89.16	0.00	44.72	0.87	/workspace/coverage/cover_reg_top/15.chip_csr_rw.2794910868
76.34	2.60	82.21	0.00	76.04	0.00	65.70	0.00			84.59	0.00	89.16	0.00	60.33	15.62	/workspace/coverage/cover_reg_top/94.xbar_access_same_device_slow_rsp.415340175
78.42	2.08	84.17	1.96	78.51	2.47	71.80	6.09			86.38	1.79	89.34	0.17	60.33	0.00	/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.2910331771
80.26	1.84	84.17	0.00	78.87	0.36	71.80	0.00			86.38	0.00	89.34	0.00	71.00	10.67	/workspace/coverage/cover_reg_top/56.xbar_access_same_device_slow_rsp.1647919011
81.81	1.55	84.17	0.00	79.04	0.17	71.80	0.00			86.41	0.03	89.34	0.00	80.10	9.09	/workspace/coverage/cover_reg_top/87.xbar_access_same_device_slow_rsp.2948796324
83.34	1.53	84.44	0.27	79.20	0.16	80.01	8.22			86.59	0.18	89.69	0.35	80.10	0.00	/workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.1051447257
84.46	1.12	86.48	2.04	81.13	1.94	80.33	0.32			88.31	1.72	90.38	0.70	80.10	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.2023933672
85.45	0.99	87.73	1.24	82.18	1.04	82.12	1.79			89.44	1.13	91.08	0.70	80.14	0.05	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2657935751
86.30	0.85	88.93	1.21	83.15	0.97	83.90	1.78			90.61	1.18	91.08	0.00	80.14	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_20.432215136
87.10	0.79	89.37	0.43	83.37	0.23	83.91	0.01			90.85	0.24	94.93	3.85	80.14	0.00	/workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.3806138278
87.83	0.73	89.37	0.00	83.37	0.00	83.91	0.00			90.85	0.00	94.93	0.00	84.53	4.38	/workspace/coverage/cover_reg_top/74.xbar_access_same_device_slow_rsp.1934320170
88.55	0.73	90.83	1.46	84.66	1.29	84.37	0.46			92.00	1.14	94.93	0.00	84.53	0.00	/workspace/coverage/default/1.chip_sw_gpio.1724838583
89.25	0.69	90.88	0.05	84.71	0.05	86.27	1.90			92.00	0.00	94.93	0.00	86.69	2.16	/workspace/coverage/default/0.chip_sw_alert_test.860932891
89.82	0.57	90.88	0.00	84.71	0.00	86.27	0.00			92.00	0.00	94.93	0.00	90.12	3.43	/workspace/coverage/cover_reg_top/45.xbar_access_same_device_slow_rsp.1496299042
90.27	0.45	90.89	0.01	87.02	2.31	86.27	0.00			92.00	0.00	94.93	0.00	90.52	0.40	/workspace/coverage/cover_reg_top/29.chip_tl_errors.3338352892
90.69	0.42	90.89	0.00	87.29	0.28	86.27	0.00			92.00	0.00	94.93	0.00	92.77	2.26	/workspace/coverage/cover_reg_top/56.xbar_stress_all_with_error.2810991095
91.10	0.40	91.41	0.52	87.78	0.49	87.19	0.92			92.49	0.49	94.93	0.00	92.77	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_10.3145888519
91.47	0.37	92.16	0.76	88.54	0.76	87.20	0.01			93.02	0.53	95.10	0.17	92.79	0.01	/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.2885216925
91.82	0.35	92.16	0.00	88.58	0.04	87.20	0.00			93.02	0.00	95.10	0.00	94.83	2.04	/workspace/coverage/cover_reg_top/84.xbar_stress_all_with_reset_error.3381286329
92.11	0.29	92.16	0.00	88.73	0.14	87.20	0.00			93.02	0.00	95.10	0.00	96.43	1.60	/workspace/coverage/cover_reg_top/53.xbar_access_same_device_slow_rsp.1647003041
92.39	0.28	92.17	0.01	88.73	0.01	88.89	1.69			93.02	0.00	95.10	0.00	96.43	0.00	/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.283776349
92.67	0.28	92.99	0.82	89.05	0.32	88.94	0.05			93.16	0.15	95.45	0.35	96.43	0.00	/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.2263740606
92.92	0.24	92.99	0.00	89.05	0.00	90.40	1.46			93.16	0.00	95.45	0.00	96.43	0.00	/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.4289014157
93.11	0.19	93.30	0.31	89.70	0.65	90.43	0.03			93.33	0.16	95.45	0.00	96.44	0.01	/workspace/coverage/cover_reg_top/6.chip_same_csr_outstanding.1554958782
93.28	0.17	93.67	0.36	90.02	0.32	90.78	0.36			93.33	0.00	95.45	0.00	96.44	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.157629784
93.44	0.16	93.67	0.00	90.17	0.15	90.78	0.00			93.34	0.02	95.45	0.00	97.23	0.79	/workspace/coverage/cover_reg_top/89.xbar_stress_all.463673405
93.57	0.13	93.89	0.23	90.36	0.19	90.80	0.01			93.66	0.32	95.45	0.00	97.23	0.00	/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.686925478
93.69	0.12	93.91	0.02	90.69	0.33	90.82	0.02			94.03	0.37	95.45	0.00	97.23	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.1984193707
93.80	0.11	93.91	0.00	90.71	0.02	90.82	0.00			94.03	0.00	95.45	0.00	97.89	0.66	/workspace/coverage/cover_reg_top/26.xbar_random_large_delays.2700342069
93.91	0.11	93.91	0.00	90.71	0.00	91.49	0.67			94.03	0.00	95.45	0.00	97.89	0.00	/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.3091405759
94.02	0.11	93.91	0.00	90.71	0.00	92.14	0.66			94.03	0.00	95.45	0.00	97.89	0.00	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.3441569143
94.11	0.09	93.92	0.01	90.77	0.06	92.44	0.30			94.04	0.01	95.63	0.17	97.89	0.00	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.1701563245
94.19	0.08	94.07	0.15	90.88	0.11	92.53	0.08			94.16	0.12	95.63	0.00	97.89	0.00	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.2175093066
94.27	0.08	94.07	0.00	90.88	0.01	92.98	0.46			94.16	0.00	95.63	0.00	97.89	0.00	/workspace/coverage/default/69.chip_sw_all_escalation_resets.1355476345
94.35	0.08	94.07	0.00	91.33	0.45	92.98	0.00			94.16	0.00	95.63	0.00	97.90	0.01	/workspace/coverage/cover_reg_top/4.chip_tl_errors.3800767019
94.42	0.07	94.24	0.17	91.49	0.16	92.98	0.00			94.27	0.11	95.63	0.00	97.90	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_retention.125611064
94.49	0.07	94.29	0.06	91.51	0.02	93.27	0.28			94.30	0.03	95.63	0.00	97.91	0.01	/workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.372893080
94.55	0.07	94.29	0.00	91.63	0.12	93.27	0.00			94.33	0.02	95.63	0.00	98.17	0.26	/workspace/coverage/cover_reg_top/24.xbar_stress_all_with_rand_reset.3337076046
94.62	0.06	94.35	0.06	91.67	0.04	93.54	0.27			94.34	0.02	95.63	0.00	98.17	0.00	/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.244586357
94.67	0.05	94.41	0.06	91.70	0.03	93.56	0.02			94.36	0.02	95.80	0.17	98.18	0.01	/workspace/coverage/default/70.chip_sw_all_escalation_resets.2248604787
94.72	0.05	94.41	0.00	91.70	0.00	93.87	0.31			94.36	0.00	95.80	0.00	98.18	0.00	/workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.1525151043
94.76	0.04	94.41	0.00	91.83	0.13	93.87	0.00			94.37	0.02	95.80	0.00	98.28	0.11	/workspace/coverage/cover_reg_top/32.xbar_stress_all.859277617
94.80	0.04	94.41	0.00	91.94	0.11	93.87	0.00			94.51	0.13	95.80	0.00	98.28	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.3016429307
94.84	0.04	94.41	0.00	91.94	0.00	94.12	0.24			94.51	0.00	95.80	0.00	98.28	0.00	/workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.3228678041
94.88	0.04	94.42	0.01	91.96	0.01	94.12	0.01			94.51	0.01	95.98	0.17	98.30	0.01	/workspace/coverage/default/33.chip_sw_all_escalation_resets.550508358
94.92	0.04	94.42	0.00	91.96	0.00	94.29	0.17			94.51	0.00	95.98	0.00	98.34	0.05	/workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.470771892
94.95	0.04	94.42	0.01	91.97	0.01	94.30	0.01			94.52	0.01	96.15	0.17	98.36	0.01	/workspace/coverage/default/51.chip_sw_all_escalation_resets.2308702348
94.99	0.04	94.43	0.01	91.98	0.01	94.30	0.00			94.53	0.01	96.33	0.17	98.37	0.01	/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.1291986823
95.02	0.04	94.43	0.00	91.98	0.00	94.34	0.04			94.53	0.00	96.50	0.17	98.37	0.00	/workspace/coverage/default/4.chip_sw_data_integrity_escalation.1853841746
95.06	0.03	94.43	0.00	92.16	0.17	94.34	0.00			94.53	0.00	96.50	0.00	98.39	0.02	/workspace/coverage/cover_reg_top/14.chip_tl_errors.2939747118
95.09	0.03	94.46	0.03	92.20	0.05	94.42	0.08			94.55	0.02	96.50	0.00	98.39	0.00	/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1248431850
95.12	0.03	94.46	0.00	92.37	0.17	94.42	0.00			94.55	0.00	96.50	0.00	98.39	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_0.3983510091
95.14	0.03	94.49	0.03	92.49	0.12	94.42	0.01			94.55	0.00	96.50	0.00	98.39	0.00	/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.2879581751
95.17	0.02	94.56	0.07	92.49	0.00	94.49	0.07			94.56	0.01	96.50	0.00	98.39	0.00	/workspace/coverage/default/4.chip_tap_straps_rma.1055130864
95.19	0.02	94.59	0.02	92.54	0.05	94.53	0.04			94.60	0.03	96.50	0.00	98.39	0.00	/workspace/coverage/default/0.chip_sw_usbdev_pincfg.4285503264
95.21	0.02	94.59	0.01	92.56	0.02	94.63	0.10			94.60	0.01	96.50	0.00	98.39	0.00	/workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.8067158
95.24	0.02	94.59	0.00	92.70	0.13	94.63	0.00			94.60	0.00	96.50	0.00	98.39	0.00	/workspace/coverage/cover_reg_top/24.chip_tl_errors.2298052599
95.26	0.02	94.65	0.06	92.75	0.05	94.63	0.00			94.63	0.02	96.50	0.00	98.39	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_wake.699665518
95.28	0.02	94.68	0.03	92.81	0.06	94.65	0.01			94.65	0.02	96.50	0.00	98.39	0.00	/workspace/coverage/default/1.chip_sw_uart_rand_baudrate.3989637017
95.30	0.02	94.68	0.00	92.81	0.00	94.77	0.12			94.65	0.00	96.50	0.00	98.39	0.00	/workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.1564921323
95.32	0.02	94.74	0.06	92.85	0.05	94.77	0.00			94.67	0.02	96.50	0.00	98.39	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.1359028840
95.34	0.02	94.74	0.00	92.96	0.11	94.77	0.00			94.67	0.00	96.50	0.00	98.39	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_20.572334019
95.36	0.02	94.74	0.00	92.96	0.00	94.77	0.00			94.67	0.00	96.50	0.00	98.50	0.11	/workspace/coverage/cover_reg_top/28.xbar_stress_all_with_rand_reset.1938855268
95.37	0.02	94.74	0.01	92.98	0.02	94.83	0.06			94.68	0.01	96.50	0.00	98.50	0.00	/workspace/coverage/default/1.rom_e2e_shutdown_output.3451252808
95.39	0.02	94.74	0.00	92.98	0.00	94.92	0.09			94.68	0.00	96.50	0.00	98.50	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.2780785239
95.40	0.02	94.74	0.00	93.05	0.07	94.92	0.00			94.68	0.00	96.50	0.00	98.52	0.02	/workspace/coverage/cover_reg_top/54.xbar_stress_all_with_rand_reset.269841715
95.42	0.01	94.74	0.00	93.05	0.00	95.00	0.08			94.68	0.00	96.50	0.00	98.52	0.00	/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.322488555
95.43	0.01	94.74	0.00	93.08	0.03	95.00	0.00			94.69	0.02	96.50	0.00	98.55	0.04	/workspace/coverage/cover_reg_top/18.xbar_stress_all_with_rand_reset.1476692888
95.44	0.01	94.74	0.00	93.16	0.08	95.00	0.00			94.69	0.00	96.50	0.00	98.55	0.00	/workspace/coverage/cover_reg_top/9.chip_tl_errors.1390028562
95.46	0.01	94.74	0.01	93.18	0.01	95.05	0.04			94.70	0.01	96.50	0.00	98.57	0.01	/workspace/coverage/default/58.chip_sw_all_escalation_resets.1794858998
95.47	0.01	94.74	0.00	93.25	0.08	95.05	0.00			94.70	0.00	96.50	0.00	98.57	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_0.792575096
95.48	0.01	94.74	0.00	93.26	0.01	95.10	0.06			94.70	0.00	96.50	0.00	98.57	0.00	/workspace/coverage/cover_reg_top/26.xbar_smoke.1690801504
95.49	0.01	94.74	0.00	93.31	0.05	95.10	0.00			94.71	0.01	96.50	0.00	98.57	0.00	/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.3560311651
95.50	0.01	94.74	0.00	93.38	0.06	95.10	0.00			94.71	0.00	96.50	0.00	98.57	0.00	/workspace/coverage/cover_reg_top/25.chip_tl_errors.1882844758
95.51	0.01	94.74	0.00	93.38	0.00	95.10	0.00			94.71	0.00	96.50	0.00	98.63	0.06	/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.2537595751
95.52	0.01	94.77	0.02	93.38	0.01	95.11	0.01			94.73	0.02	96.50	0.00	98.63	0.00	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.3201163835
95.53	0.01	94.77	0.01	93.41	0.03	95.13	0.02			94.73	0.00	96.50	0.00	98.63	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.61549520
95.54	0.01	94.77	0.00	93.42	0.01	95.13	0.00			94.73	0.00	96.50	0.00	98.67	0.05	/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.1784647440
95.55	0.01	94.80	0.02	93.42	0.01	95.13	0.01			94.74	0.02	96.50	0.00	98.67	0.00	/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.677308365
95.55	0.01	94.80	0.00	93.47	0.05	95.13	0.00			94.74	0.00	96.50	0.00	98.67	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_10.3491884424
95.56	0.01	94.80	0.00	93.51	0.04	95.14	0.01			94.74	0.00	96.50	0.00	98.67	0.00	/workspace/coverage/default/1.chip_sw_uart_tx_rx.220602040
95.57	0.01	94.80	0.00	93.51	0.00	95.18	0.04			94.74	0.00	96.50	0.00	98.67	0.00	/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.1426466234
95.57	0.01	94.80	0.00	93.51	0.00	95.22	0.04			94.74	0.00	96.50	0.00	98.67	0.00	/workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.333868919
95.58	0.01	94.80	0.00	93.55	0.04	95.22	0.00			94.74	0.00	96.50	0.00	98.67	0.00	/workspace/coverage/cover_reg_top/26.xbar_stress_all_with_rand_reset.1306624584
95.59	0.01	94.80	0.00	93.55	0.00	95.22	0.00			94.74	0.00	96.50	0.00	98.71	0.04	/workspace/coverage/cover_reg_top/30.xbar_stress_all_with_reset_error.2035735351
95.59	0.01	94.80	0.00	93.57	0.02	95.22	0.00			94.74	0.00	96.50	0.00	98.72	0.01	/workspace/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.560029152
95.60	0.01	94.80	0.00	93.57	0.00	95.25	0.03			94.74	0.00	96.50	0.00	98.72	0.00	/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.3327414851
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95.61	0.01	94.80	0.00	93.60	0.00	95.28	0.03			94.74	0.00	96.50	0.00	98.72	0.00	/workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.3420472149
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95.62	0.01	94.80	0.00	93.63	0.00	95.31	0.03			94.74	0.00	96.50	0.00	98.72	0.00	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.618771594
95.62	0.01	94.80	0.00	93.64	0.01	95.33	0.01			94.74	0.00	96.50	0.00	98.72	0.00	/workspace/coverage/default/1.chip_sw_entropy_src_csrng.504348241
95.63	0.01	94.80	0.00	93.67	0.02	95.33	0.00			94.74	0.00	96.50	0.00	98.72	0.00	/workspace/coverage/cover_reg_top/53.xbar_stress_all.1644536699
95.63	0.01	94.80	0.00	93.67	0.00	95.33	0.00			94.74	0.00	96.50	0.00	98.74	0.02	/workspace/coverage/cover_reg_top/44.xbar_stress_all_with_rand_reset.1463881055
95.63	0.01	94.80	0.00	93.67	0.00	95.33	0.00			94.74	0.00	96.50	0.00	98.77	0.02	/workspace/coverage/cover_reg_top/52.xbar_stress_all_with_reset_error.2686466087
95.64	0.01	94.80	0.00	93.68	0.01	95.33	0.00			94.74	0.00	96.50	0.00	98.78	0.01	/workspace/coverage/cover_reg_top/6.xbar_random_slow_rsp.3119760152
95.64	0.01	94.80	0.01	93.69	0.01	95.33	0.01			94.74	0.00	96.50	0.00	98.78	0.00	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.620741498
95.64	0.01	94.80	0.00	93.69	0.00	95.34	0.01			94.74	0.00	96.50	0.00	98.79	0.01	/workspace/coverage/default/14.chip_sw_all_escalation_resets.1906865132
95.65	0.01	94.80	0.00	93.69	0.01	95.34	0.00			94.76	0.02	96.50	0.00	98.79	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.1616126476
95.65	0.01	94.80	0.00	93.69	0.00	95.36	0.02			94.76	0.00	96.50	0.00	98.79	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3783353985
95.65	0.01	94.81	0.01	93.70	0.01	95.36	0.00			94.76	0.00	96.50	0.00	98.79	0.00	/workspace/coverage/default/2.chip_sw_pattgen_ios.847957288
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95.66	0.01	94.81	0.00	93.70	0.00	95.37	0.01			94.76	0.00	96.50	0.00	98.81	0.01	/workspace/coverage/default/83.chip_sw_all_escalation_resets.4209258893
95.66	0.01	94.82	0.01	93.71	0.01	95.37	0.01			94.76	0.00	96.50	0.00	98.81	0.00	/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.2029367172
95.66	0.01	94.83	0.01	93.71	0.00	95.37	0.01			94.76	0.00	96.50	0.00	98.81	0.00	/workspace/coverage/default/0.chip_sw_plic_sw_irq.4205065976
95.67	0.01	94.84	0.01	93.71	0.00	95.38	0.01			94.76	0.00	96.50	0.00	98.81	0.00	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.897512660
95.67	0.01	94.84	0.00	93.72	0.01	95.38	0.00			94.76	0.00	96.50	0.00	98.81	0.00	/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.4041901677
95.67	0.01	94.84	0.00	93.73	0.01	95.38	0.00			94.76	0.00	96.50	0.00	98.81	0.00	/workspace/coverage/cover_reg_top/14.xbar_stress_all.2667381674
95.67	0.01	94.84	0.00	93.75	0.01	95.38	0.00			94.76	0.00	96.50	0.00	98.81	0.00	/workspace/coverage/cover_reg_top/27.chip_tl_errors.3534577155
95.68	0.01	94.84	0.00	93.76	0.01	95.38	0.00			94.76	0.00	96.50	0.00	98.81	0.00	/workspace/coverage/cover_reg_top/76.xbar_stress_all_with_rand_reset.2232326069
95.68	0.01	94.84	0.00	93.78	0.01	95.38	0.00			94.76	0.00	96.50	0.00	98.81	0.00	/workspace/coverage/cover_reg_top/84.xbar_access_same_device.3467552913
95.68	0.01	94.84	0.00	93.79	0.01	95.38	0.00			94.76	0.00	96.50	0.00	98.81	0.00	/workspace/coverage/default/0.chip_sw_gpio.1485800722
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95.69	0.01	94.84	0.00	93.79	0.00	95.40	0.01			94.76	0.00	96.50	0.00	98.83	0.00	/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.3433150689
95.69	0.01	94.84	0.01	93.80	0.01	95.40	0.00			94.76	0.00	96.50	0.00	98.83	0.00	/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.896195446
95.69	0.01	94.84	0.00	93.81	0.01	95.40	0.01			94.76	0.00	96.50	0.00	98.83	0.00	/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.1412605752
95.69	0.01	94.84	0.00	93.81	0.00	95.40	0.01			94.76	0.00	96.50	0.00	98.84	0.01	/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.2636644832
95.69	0.01	94.85	0.01	93.81	0.00	95.41	0.01			94.76	0.00	96.50	0.00	98.84	0.00	/workspace/coverage/default/0.chip_sw_power_idle_load.3833196871
95.70	0.01	94.85	0.00	93.81	0.00	95.41	0.00			94.76	0.00	96.50	0.00	98.85	0.01	/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.2574485801
95.70	0.01	94.85	0.00	93.81	0.00	95.41	0.00			94.76	0.00	96.50	0.00	98.86	0.01	/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.754163590
95.70	0.01	94.85	0.00	93.81	0.00	95.41	0.00			94.76	0.00	96.50	0.00	98.87	0.01	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.3602189462
95.70	0.01	94.85	0.00	93.81	0.00	95.41	0.00			94.76	0.00	96.50	0.00	98.88	0.01	/workspace/coverage/default/0.chip_sw_all_escalation_resets.1680381329
95.70	0.01	94.85	0.00	93.81	0.00	95.41	0.00			94.76	0.00	96.50	0.00	98.90	0.01	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.3318390726
95.71	0.01	94.85	0.00	93.81	0.00	95.41	0.00			94.76	0.00	96.50	0.00	98.91	0.01	/workspace/coverage/default/1.chip_sw_all_escalation_resets.1932499853
95.71	0.01	94.85	0.00	93.81	0.00	95.41	0.00			94.76	0.00	96.50	0.00	98.92	0.01	/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.1756484430
95.71	0.01	94.85	0.00	93.81	0.00	95.41	0.00			94.76	0.00	96.50	0.00	98.93	0.01	/workspace/coverage/default/10.chip_sw_all_escalation_resets.2892418632
95.71	0.01	94.85	0.00	93.81	0.00	95.41	0.00			94.76	0.00	96.50	0.00	98.94	0.01	/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.65941339
95.71	0.01	94.85	0.00	93.81	0.00	95.41	0.00			94.76	0.00	96.50	0.00	98.95	0.01	/workspace/coverage/default/11.chip_sw_all_escalation_resets.1117469421
95.72	0.01	94.85	0.00	93.81	0.00	95.41	0.00			94.76	0.00	96.50	0.00	98.97	0.01	/workspace/coverage/default/12.chip_sw_all_escalation_resets.309525572
95.72	0.01	94.85	0.00	93.81	0.00	95.41	0.00			94.76	0.00	96.50	0.00	98.98	0.01	/workspace/coverage/default/13.chip_sw_all_escalation_resets.547149350
95.72	0.01	94.85	0.00	93.81	0.00	95.41	0.00			94.76	0.00	96.50	0.00	98.99	0.01	/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.1575560269
95.72	0.01	94.85	0.00	93.81	0.00	95.41	0.00			94.76	0.00	96.50	0.00	99.00	0.01	/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.2373134908
95.72	0.01	94.85	0.00	93.81	0.00	95.41	0.00			94.76	0.00	96.50	0.00	99.01	0.01	/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.2251246210
95.73	0.01	94.85	0.00	93.81	0.00	95.41	0.00			94.76	0.00	96.50	0.00	99.02	0.01	/workspace/coverage/default/17.chip_sw_all_escalation_resets.422263170
95.73	0.01	94.85	0.00	93.81	0.00	95.41	0.00			94.76	0.00	96.50	0.00	99.04	0.01	/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.465183294
95.73	0.01	94.85	0.00	93.81	0.00	95.41	0.00			94.76	0.00	96.50	0.00	99.05	0.01	/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.3818982382
95.73	0.01	94.85	0.00	93.81	0.00	95.41	0.00			94.76	0.00	96.50	0.00	99.06	0.01	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.2289677708
95.73	0.01	94.85	0.00	93.81	0.00	95.41	0.00			94.76	0.00	96.50	0.00	99.07	0.01	/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.2295185161
95.74	0.01	94.85	0.00	93.81	0.00	95.41	0.00			94.76	0.00	96.50	0.00	99.08	0.01	/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.3565891145
95.74	0.01	94.85	0.00	93.81	0.00	95.41	0.00			94.76	0.00	96.50	0.00	99.10	0.01	/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.2135468019
95.74	0.01	94.85	0.00	93.81	0.00	95.41	0.00			94.76	0.00	96.50	0.00	99.11	0.01	/workspace/coverage/default/22.chip_sw_all_escalation_resets.3926219105
95.74	0.01	94.85	0.00	93.81	0.00	95.41	0.00			94.76	0.00	96.50	0.00	99.12	0.01	/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.1559957863
95.74	0.01	94.85	0.00	93.81	0.00	95.41	0.00			94.76	0.00	96.50	0.00	99.13	0.01	/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.2739197868
95.75	0.01	94.85	0.00	93.81	0.00	95.41	0.00			94.76	0.00	96.50	0.00	99.14	0.01	/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.4081342678
95.75	0.01	94.85	0.00	93.81	0.00	95.41	0.00			94.76	0.00	96.50	0.00	99.15	0.01	/workspace/coverage/default/26.chip_sw_all_escalation_resets.2387755127
95.75	0.01	94.85	0.00	93.81	0.00	95.41	0.00			94.76	0.00	96.50	0.00	99.17	0.01	/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.1683649118
95.75	0.01	94.85	0.00	93.81	0.00	95.41	0.00			94.76	0.00	96.50	0.00	99.18	0.01	/workspace/coverage/default/27.chip_sw_all_escalation_resets.4158876813
95.75	0.01	94.85	0.00	93.81	0.00	95.41	0.00			94.76	0.00	96.50	0.00	99.19	0.01	/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.4111120981
95.76	0.01	94.85	0.00	93.81	0.00	95.41	0.00			94.76	0.00	96.50	0.00	99.20	0.01	/workspace/coverage/default/28.chip_sw_all_escalation_resets.3274715810
95.76	0.01	94.85	0.00	93.81	0.00	95.41	0.00			94.76	0.00	96.50	0.00	99.21	0.01	/workspace/coverage/default/30.chip_sw_all_escalation_resets.1914143595
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95.77	0.01	94.85	0.00	93.81	0.00	95.41	0.00			94.76	0.00	96.50	0.00	99.26	0.01	/workspace/coverage/default/37.chip_sw_all_escalation_resets.726684681
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95.78	0.01	94.85	0.00	93.81	0.00	95.41	0.00			94.76	0.00	96.50	0.00	99.32	0.01	/workspace/coverage/default/42.chip_sw_all_escalation_resets.3655460066
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95.80	0.01	94.85	0.00	93.81	0.00	95.41	0.00			94.76	0.00	96.50	0.00	99.47	0.01	/workspace/coverage/default/67.chip_sw_all_escalation_resets.1364382259
95.80	0.01	94.85	0.00	93.81	0.00	95.41	0.00			94.76	0.00	96.50	0.00	99.48	0.01	/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.1591071368
95.80	0.01	94.85	0.00	93.81	0.00	95.41	0.00			94.76	0.00	96.50	0.00	99.49	0.01	/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.2905910233
95.81	0.01	94.85	0.00	93.81	0.00	95.41	0.00			94.76	0.00	96.50	0.00	99.51	0.01	/workspace/coverage/default/82.chip_sw_all_escalation_resets.2459004843
95.81	0.01	94.85	0.00	93.81	0.00	95.41	0.00			94.76	0.00	96.50	0.00	99.52	0.01	/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.2514749868
95.81	0.01	94.85	0.00	93.81	0.00	95.41	0.00			94.76	0.00	96.50	0.00	99.53	0.01	/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.1623063266
95.81	0.01	94.85	0.00	93.81	0.00	95.41	0.00			94.76	0.00	96.50	0.00	99.54	0.01	/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.2151434656
95.81	0.01	94.85	0.00	93.81	0.00	95.41	0.00			94.76	0.00	96.50	0.00	99.55	0.01	/workspace/coverage/default/89.chip_sw_all_escalation_resets.2280673903
95.82	0.01	94.85	0.00	93.81	0.00	95.41	0.00			94.76	0.00	96.50	0.00	99.57	0.01	/workspace/coverage/default/91.chip_sw_all_escalation_resets.2321949103
95.82	0.01	94.85	0.00	93.81	0.00	95.41	0.00			94.76	0.00	96.50	0.00	99.58	0.01	/workspace/coverage/default/95.chip_sw_all_escalation_resets.1475883407
95.82	0.01	94.85	0.00	93.81	0.00	95.41	0.00			94.76	0.00	96.50	0.00	99.59	0.01	/workspace/coverage/default/99.chip_sw_all_escalation_resets.146890957
95.82	0.01	94.85	0.00	93.81	0.00	95.42	0.01			94.76	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.895181777
95.82	0.01	94.85	0.00	93.81	0.00	95.43	0.01			94.76	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.3578812920
95.83	0.01	94.85	0.00	93.81	0.00	95.44	0.01			94.76	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.3630250224
95.83	0.01	94.85	0.00	93.82	0.01	95.44	0.00			94.76	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/cover_reg_top/69.xbar_stress_all_with_rand_reset.2475219823
95.83	0.01	94.85	0.00	93.83	0.01	95.44	0.00			94.76	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_10.983138447
95.83	0.01	94.85	0.00	93.84	0.01	95.44	0.00			94.76	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3414873258
95.83	0.01	94.85	0.00	93.85	0.01	95.44	0.00			94.76	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.2098829116
95.83	0.01	94.85	0.00	93.86	0.01	95.44	0.00			94.76	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_20.251274128
95.84	0.01	94.86	0.01	93.86	0.00	95.45	0.01			94.76	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.2982540843
95.84	0.01	94.86	0.01	93.86	0.00	95.46	0.01			94.76	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/default/15.chip_sw_all_escalation_resets.2083808184
95.84	0.01	94.86	0.00	93.86	0.00	95.46	0.01			94.76	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.488931808
95.84	0.01	94.86	0.00	93.86	0.00	95.47	0.01			94.76	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.3339258771
95.84	0.01	94.86	0.00	93.87	0.01	95.48	0.01			94.76	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3113758484
95.84	0.01	94.86	0.00	93.87	0.00	95.48	0.00			94.77	0.01	96.50	0.00	99.59	0.00	/workspace/coverage/default/0.chip_tap_straps_dev.2145812524
95.85	0.01	94.86	0.00	93.87	0.01	95.48	0.00			94.77	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/cover_reg_top/10.chip_tl_errors.588825789
95.85	0.01	94.86	0.00	93.88	0.01	95.48	0.00			94.77	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_retention.2973374242
95.85	0.01	94.86	0.00	93.89	0.01	95.48	0.00			94.77	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/default/2.chip_sw_gpio.278689113
95.85	0.01	94.86	0.00	93.89	0.00	95.49	0.01			94.77	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2891102126
95.85	0.01	94.86	0.00	93.89	0.00	95.49	0.01			94.77	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_kmac_entropy.288420621
95.85	0.01	94.87	0.01	93.89	0.00	95.49	0.00			94.77	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.2822235389
95.85	0.01	94.87	0.00	93.89	0.00	95.50	0.01			94.77	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2039442715
95.85	0.01	94.87	0.00	93.89	0.00	95.50	0.01			94.77	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.561272566
95.85	0.01	94.87	0.00	93.89	0.00	95.51	0.01			94.77	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.3573458281
95.85	0.01	94.87	0.00	93.89	0.00	95.51	0.01			94.77	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.3393776110
95.86	0.01	94.87	0.00	93.89	0.00	95.52	0.01			94.77	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.2208713861
95.86	0.01	94.87	0.00	93.89	0.01	95.52	0.00			94.77	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.824721371
95.86	0.01	94.87	0.00	93.89	0.01	95.52	0.00			94.77	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/cover_reg_top/17.chip_tl_errors.698057619
95.86	0.01	94.87	0.00	93.90	0.01	95.52	0.00			94.77	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/cover_reg_top/24.xbar_stress_all_with_error.421284098
95.86	0.01	94.87	0.00	93.90	0.01	95.52	0.00			94.77	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/cover_reg_top/38.xbar_stress_all_with_error.3210865433
95.86	0.01	94.87	0.00	93.90	0.01	95.52	0.00			94.77	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/cover_reg_top/5.xbar_error_and_unmapped_addr.4242226496
95.86	0.01	94.87	0.00	93.91	0.01	95.52	0.00			94.77	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/cover_reg_top/8.xbar_stress_all_with_error.239375615
95.86	0.01	94.87	0.00	93.91	0.01	95.52	0.00			94.77	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/cover_reg_top/88.xbar_stress_all_with_reset_error.1695860394
95.86	0.01	94.87	0.00	93.92	0.01	95.52	0.00			94.77	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.3554340768
95.86	0.01	94.87	0.00	93.92	0.01	95.52	0.00			94.77	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.878529219
95.86	0.01	94.87	0.00	93.92	0.01	95.52	0.00			94.77	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.34506387
95.86	0.01	94.87	0.00	93.92	0.00	95.52	0.01			94.77	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_edn_boot_mode.2360578264
95.86	0.01	94.87	0.00	93.92	0.00	95.52	0.01			94.77	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.3688201738
95.86	0.01	94.87	0.00	93.92	0.00	95.52	0.01			94.77	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.4181376075
95.86	0.01	94.87	0.00	93.92	0.00	95.53	0.01			94.77	0.00	96.50	0.00	99.59	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.2704873917

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.3385351592
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.1811349859
/workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.2592281253
/workspace/coverage/cover_reg_top/0.chip_csr_rw.3376874069
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.1123163062
/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.2361892407
/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.3628648174
/workspace/coverage/cover_reg_top/0.chip_tl_errors.4249695117
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.838932801
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.1689232295
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.1170285980
/workspace/coverage/cover_reg_top/0.xbar_error_random.2206354488
/workspace/coverage/cover_reg_top/0.xbar_random.3359944792
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.4018898471
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.3291002483
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.3421235432
/workspace/coverage/cover_reg_top/0.xbar_same_source.3119378043
/workspace/coverage/cover_reg_top/0.xbar_smoke.611506332
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.984334416
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.2098275653
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.2321925013
/workspace/coverage/cover_reg_top/0.xbar_stress_all.1728949514
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.3033026392
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.3259702800
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.1262934788
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.1385476076
/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.3194929416
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.3317826696
/workspace/coverage/cover_reg_top/1.chip_csr_rw.3822793207
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.501678431
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.59792732
/workspace/coverage/cover_reg_top/1.chip_tl_errors.1051929213
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.1616285065
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.2230867918
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.1981331353
/workspace/coverage/cover_reg_top/1.xbar_error_random.2746383995
/workspace/coverage/cover_reg_top/1.xbar_random.355843428
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.2603335003
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.2981267371
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.3516411975
/workspace/coverage/cover_reg_top/1.xbar_same_source.3051121804
/workspace/coverage/cover_reg_top/1.xbar_smoke.3669965971
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.2086090908
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.1464946466
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.1407295357
/workspace/coverage/cover_reg_top/1.xbar_stress_all.1364929815
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.1684318390
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.2340948169
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.2181255195
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.1756804053
/workspace/coverage/cover_reg_top/10.chip_csr_rw.2576312390
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.1458503080
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.3641205929
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.102102916
/workspace/coverage/cover_reg_top/10.xbar_error_random.3214316033
/workspace/coverage/cover_reg_top/10.xbar_random.1242430647
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.545230532
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.3076887850
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.790642981
/workspace/coverage/cover_reg_top/10.xbar_same_source.2813093519
/workspace/coverage/cover_reg_top/10.xbar_smoke.3876468924
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.2332659510
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.2516127848
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.1101519340
/workspace/coverage/cover_reg_top/10.xbar_stress_all.4278166509
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.3718761378
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.3930833697
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.1197252888
/workspace/coverage/cover_reg_top/11.chip_csr_rw.2881988485
/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.2276446801
/workspace/coverage/cover_reg_top/11.chip_tl_errors.4277149102
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.3834577885
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.2695232161
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.3354548725
/workspace/coverage/cover_reg_top/11.xbar_error_random.467298143
/workspace/coverage/cover_reg_top/11.xbar_random.179138480
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.4061985160
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.3254207824
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.4135935797
/workspace/coverage/cover_reg_top/11.xbar_same_source.4020850298
/workspace/coverage/cover_reg_top/11.xbar_smoke.3397659794
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.1443044400
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.2193198795
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.3221824798
/workspace/coverage/cover_reg_top/11.xbar_stress_all.1276653429
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.2385971957
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.2289133894
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.1660754442
/workspace/coverage/cover_reg_top/12.chip_csr_rw.1583997922
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.300758074
/workspace/coverage/cover_reg_top/12.chip_tl_errors.3468058142
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.512989914
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.884495011
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.265189355
/workspace/coverage/cover_reg_top/12.xbar_error_random.3716395860
/workspace/coverage/cover_reg_top/12.xbar_random.3937124790
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.428065274
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.1687267201
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.2551626467
/workspace/coverage/cover_reg_top/12.xbar_same_source.3692384598
/workspace/coverage/cover_reg_top/12.xbar_smoke.2166876314
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.3274701787
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.2311716890
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.3170545946
/workspace/coverage/cover_reg_top/12.xbar_stress_all.2709767589
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.3567622735
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.2992603766
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.3516815338
/workspace/coverage/cover_reg_top/13.chip_csr_rw.850801446
/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.2149538860
/workspace/coverage/cover_reg_top/13.chip_tl_errors.3977471711
/workspace/coverage/cover_reg_top/13.xbar_access_same_device.35343573
/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.3211033226
/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.3613868654
/workspace/coverage/cover_reg_top/13.xbar_error_random.997070808
/workspace/coverage/cover_reg_top/13.xbar_random.1733435645
/workspace/coverage/cover_reg_top/13.xbar_random_large_delays.2924383272
/workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.3311393954
/workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.4003138866
/workspace/coverage/cover_reg_top/13.xbar_same_source.3741660551
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/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3833523844
/workspace/coverage/default/2.chip_sw_uart_rand_baudrate.2708660237
/workspace/coverage/default/2.chip_sw_uart_smoketest.2128937256
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/workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.1258075151
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/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.2495968060
/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.696479304
/workspace/coverage/default/31.chip_sw_all_escalation_resets.3201514956
/workspace/coverage/default/32.chip_sw_all_escalation_resets.538291536
/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.468617355
/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.485360297
/workspace/coverage/default/35.chip_sw_all_escalation_resets.960842223
/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.1026095087
/workspace/coverage/default/36.chip_sw_all_escalation_resets.2154989717
/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.1558035475
/workspace/coverage/default/38.chip_sw_all_escalation_resets.36992695
/workspace/coverage/default/39.chip_sw_all_escalation_resets.2831299885
/workspace/coverage/default/4.chip_sw_all_escalation_resets.1767593709
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.529167188
/workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.2567236293
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.4117150895
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.1855554099
/workspace/coverage/default/4.chip_sw_uart_tx_rx.484667238
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.2950984702
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1652948020
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.352444370
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.1299791468
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/workspace/coverage/default/4.chip_tap_straps_testunlock0.1121944784
/workspace/coverage/default/41.chip_sw_all_escalation_resets.3237951972
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/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.3543211278
/workspace/coverage/default/43.chip_sw_all_escalation_resets.3278447404
/workspace/coverage/default/44.chip_sw_all_escalation_resets.702463342
/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.3941110572
/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.75944506
/workspace/coverage/default/46.chip_sw_all_escalation_resets.3422539506
/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.2616989697
/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.676953939
/workspace/coverage/default/48.chip_sw_all_escalation_resets.299350726
/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.1836654529
/workspace/coverage/default/5.chip_sw_all_escalation_resets.3055556358
/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.3522251419
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.1879143449
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.3066332110
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.320695154
/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.1468139745
/workspace/coverage/default/52.chip_sw_all_escalation_resets.2429313590
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.1093726455
/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.2100511686
/workspace/coverage/default/54.chip_sw_all_escalation_resets.2569233104
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.1184623199
/workspace/coverage/default/55.chip_sw_all_escalation_resets.98517947
/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.282973378
/workspace/coverage/default/56.chip_sw_all_escalation_resets.3377582140
/workspace/coverage/default/57.chip_sw_all_escalation_resets.3064881634
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.563152106
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.2574792784
/workspace/coverage/default/59.chip_sw_all_escalation_resets.3560446272
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.2418815543
/workspace/coverage/default/6.chip_sw_all_escalation_resets.391400795
/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.3840775342
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.3169354299
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.3385549638
/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.435360205
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.2759817439
/workspace/coverage/default/61.chip_sw_all_escalation_resets.544401096
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.2600501529
/workspace/coverage/default/62.chip_sw_all_escalation_resets.2144426257
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.2506201518
/workspace/coverage/default/63.chip_sw_all_escalation_resets.2110654354
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.334574506
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.2954482207
/workspace/coverage/default/65.chip_sw_all_escalation_resets.1696700439
/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.2995508711
/workspace/coverage/default/66.chip_sw_all_escalation_resets.997753322
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.1848448277
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.3719007832
/workspace/coverage/default/68.chip_sw_all_escalation_resets.1605479435
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.786352475
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.19755494
/workspace/coverage/default/7.chip_sw_all_escalation_resets.2575151215
/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.298584273
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.4000892272
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.948236075
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.3645653079
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.3099442580
/workspace/coverage/default/71.chip_sw_all_escalation_resets.2477296303
/workspace/coverage/default/72.chip_sw_all_escalation_resets.3787189027
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.2445508131
/workspace/coverage/default/73.chip_sw_all_escalation_resets.165554358
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.2772721637
/workspace/coverage/default/74.chip_sw_all_escalation_resets.1811423303
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.3314194890
/workspace/coverage/default/75.chip_sw_all_escalation_resets.737820251
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.4232876333
/workspace/coverage/default/76.chip_sw_all_escalation_resets.3334315210
/workspace/coverage/default/77.chip_sw_all_escalation_resets.1361223951
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.2197200994
/workspace/coverage/default/78.chip_sw_all_escalation_resets.2543501368
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.1805407665
/workspace/coverage/default/79.chip_sw_all_escalation_resets.493427904
/workspace/coverage/default/8.chip_sw_all_escalation_resets.2997791691
/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.1695426189
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.126002182
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.1734850727
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.2275204579
/workspace/coverage/default/80.chip_sw_all_escalation_resets.2752290390
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.3937998015
/workspace/coverage/default/81.chip_sw_all_escalation_resets.504373697
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.2062897004
/workspace/coverage/default/84.chip_sw_all_escalation_resets.501274305
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.1019772549
/workspace/coverage/default/86.chip_sw_all_escalation_resets.3097013197
/workspace/coverage/default/87.chip_sw_all_escalation_resets.2727764457
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.496518879
/workspace/coverage/default/88.chip_sw_all_escalation_resets.1370667976
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.2016829905
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.965595593
/workspace/coverage/default/9.chip_sw_all_escalation_resets.791343298
/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.3633887113
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.553329225
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.952513163
/workspace/coverage/default/90.chip_sw_all_escalation_resets.3600059049
/workspace/coverage/default/92.chip_sw_all_escalation_resets.962712390
/workspace/coverage/default/93.chip_sw_all_escalation_resets.1723100018
/workspace/coverage/default/94.chip_sw_all_escalation_resets.4080723087
/workspace/coverage/default/96.chip_sw_all_escalation_resets.869347458
/workspace/coverage/default/97.chip_sw_all_escalation_resets.225430689
/workspace/coverage/default/98.chip_sw_all_escalation_resets.4069364737
/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.1818956341
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.2637605931
/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.222875289
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.159136609
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.2332780451
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.998264066
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.2822890789
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.4178071454

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Total test records in report: 2885

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T4	/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.2910331771			Jun 05 07:21:29 PM PDT 24	Jun 05 08:21:42 PM PDT 24	15473092480 ps
T5	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.12319965			Jun 05 07:23:43 PM PDT 24	Jun 05 08:10:41 PM PDT 24	10755497074 ps
T6	/workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1190519862			Jun 05 07:36:22 PM PDT 24	Jun 05 07:42:05 PM PDT 24	4505865380 ps
T45	/workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.2681647457			Jun 05 07:36:22 PM PDT 24	Jun 05 07:43:12 PM PDT 24	3446132740 ps
T44	/workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.4112396294			Jun 05 07:11:14 PM PDT 24	Jun 05 08:36:43 PM PDT 24	25836543352 ps
T17	/workspace/coverage/default/85.chip_sw_all_escalation_resets.2426148469			Jun 05 07:48:48 PM PDT 24	Jun 05 08:02:08 PM PDT 24	6413866120 ps
T59	/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.1614772475			Jun 05 07:11:30 PM PDT 24	Jun 05 07:13:23 PM PDT 24	2337631151 ps
T18	/workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.2965923409			Jun 05 07:12:02 PM PDT 24	Jun 05 07:19:00 PM PDT 24	3806077250 ps
T82	/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3771810778			Jun 05 07:26:59 PM PDT 24	Jun 05 07:31:35 PM PDT 24	2820500360 ps
T56	/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.2123909121			Jun 05 07:33:29 PM PDT 24	Jun 05 08:26:16 PM PDT 24	15161995408 ps
T129	/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.1805407665			Jun 05 07:50:37 PM PDT 24	Jun 05 07:57:54 PM PDT 24	4134766864 ps
T1	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2657935751			Jun 05 07:32:10 PM PDT 24	Jun 05 07:58:38 PM PDT 24	23770308704 ps
T102	/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.2636644832			Jun 05 07:45:10 PM PDT 24	Jun 05 07:50:43 PM PDT 24	4139353080 ps
T103	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.3635004476			Jun 05 07:24:12 PM PDT 24	Jun 05 07:56:02 PM PDT 24	7810051128 ps
T19	/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.4289014157			Jun 05 07:30:45 PM PDT 24	Jun 05 08:50:45 PM PDT 24	42929732822 ps
T104	/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1248431850			Jun 05 07:30:22 PM PDT 24	Jun 05 07:48:21 PM PDT 24	8379804376 ps
T105	/workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.2098829116			Jun 05 07:27:05 PM PDT 24	Jun 05 07:34:32 PM PDT 24	3756354560 ps
T106	/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.1879852963			Jun 05 07:12:42 PM PDT 24	Jun 05 07:28:45 PM PDT 24	6362745121 ps
T107	/workspace/coverage/default/0.chip_sw_aes_idle.498778051			Jun 05 07:13:08 PM PDT 24	Jun 05 07:16:14 PM PDT 24	2637093704 ps
T20	/workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.3228678041			Jun 05 07:28:30 PM PDT 24	Jun 05 07:59:03 PM PDT 24	20038673764 ps
T57	/workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.372893080			Jun 05 07:28:51 PM PDT 24	Jun 05 07:37:43 PM PDT 24	5143647448 ps
T125	/workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.2405019984			Jun 05 07:25:41 PM PDT 24	Jun 05 07:47:27 PM PDT 24	6165748384 ps
T122	/workspace/coverage/default/1.chip_sw_entropy_src_csrng.504348241			Jun 05 07:24:39 PM PDT 24	Jun 05 07:53:05 PM PDT 24	7214581010 ps
T114	/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.995689461			Jun 05 07:14:31 PM PDT 24	Jun 05 07:19:00 PM PDT 24	3034941805 ps
T209	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.1821183960			Jun 05 07:10:31 PM PDT 24	Jun 05 07:22:34 PM PDT 24	4665307720 ps
T437	/workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.4003177112			Jun 05 07:38:33 PM PDT 24	Jun 05 07:56:01 PM PDT 24	5580374812 ps
T58	/workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.1051447257			Jun 05 07:19:05 PM PDT 24	Jun 05 07:52:15 PM PDT 24	24250205384 ps
T215	/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.2029367172			Jun 05 07:22:27 PM PDT 24	Jun 05 07:33:33 PM PDT 24	3927496158 ps
T27	/workspace/coverage/default/1.chip_sw_uart_rand_baudrate.3989637017			Jun 05 07:21:01 PM PDT 24	Jun 05 08:05:43 PM PDT 24	12900317640 ps
T2	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1188883355			Jun 05 07:36:03 PM PDT 24	Jun 05 08:00:16 PM PDT 24	18902051492 ps
T46	/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.2263740606			Jun 05 07:12:41 PM PDT 24	Jun 05 07:17:39 PM PDT 24	2977153900 ps
T391	/workspace/coverage/default/1.rom_e2e_asm_init_rma.948123471			Jun 05 07:35:07 PM PDT 24	Jun 05 08:22:50 PM PDT 24	14303871524 ps
T126	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation.2240890989			Jun 05 07:14:49 PM PDT 24	Jun 05 07:37:49 PM PDT 24	7487632700 ps
T211	/workspace/coverage/default/3.chip_sw_uart_rand_baudrate.96751614			Jun 05 07:41:10 PM PDT 24	Jun 05 07:52:33 PM PDT 24	4204353934 ps
T207	/workspace/coverage/default/17.chip_sw_uart_rand_baudrate.4215455			Jun 05 07:45:38 PM PDT 24	Jun 05 08:08:09 PM PDT 24	8093339934 ps
T238	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.2704873917			Jun 05 07:23:34 PM PDT 24	Jun 05 08:57:10 PM PDT 24	23326162448 ps
T936	/workspace/coverage/default/2.chip_sw_rstmgr_smoketest.381998052			Jun 05 07:39:11 PM PDT 24	Jun 05 07:42:57 PM PDT 24	2570400436 ps
T64	/workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.3688201738			Jun 05 07:20:15 PM PDT 24	Jun 05 07:50:06 PM PDT 24	10047608353 ps
T63	/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.126002182			Jun 05 07:41:47 PM PDT 24	Jun 05 07:50:55 PM PDT 24	5982098148 ps
T118	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.3706344827			Jun 05 07:15:48 PM PDT 24	Jun 05 07:30:20 PM PDT 24	10930633299 ps
T223	/workspace/coverage/default/58.chip_sw_all_escalation_resets.1794858998			Jun 05 07:48:00 PM PDT 24	Jun 05 07:58:36 PM PDT 24	5744488992 ps
T224	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.477950261			Jun 05 07:11:16 PM PDT 24	Jun 05 07:37:25 PM PDT 24	16452308504 ps
T937	/workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.29438538			Jun 05 07:13:46 PM PDT 24	Jun 05 07:17:15 PM PDT 24	3268504512 ps
T165	/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1897973315			Jun 05 07:21:55 PM PDT 24	Jun 05 07:23:48 PM PDT 24	2462411549 ps
T208	/workspace/coverage/default/1.chip_sw_power_idle_load.2103811112			Jun 05 07:27:12 PM PDT 24	Jun 05 07:39:52 PM PDT 24	4034993322 ps
T357	/workspace/coverage/default/0.chip_sw_aon_timer_irq.495826233			Jun 05 07:19:54 PM PDT 24	Jun 05 07:26:24 PM PDT 24	3826857342 ps
T532	/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.2304411204			Jun 05 07:47:09 PM PDT 24	Jun 05 07:52:47 PM PDT 24	4305806216 ps
T438	/workspace/coverage/default/0.chip_sw_kmac_entropy.288420621			Jun 05 07:13:41 PM PDT 24	Jun 05 07:17:42 PM PDT 24	3232934722 ps
T326	/workspace/coverage/default/0.chip_sival_flash_info_access.1805441193			Jun 05 07:12:30 PM PDT 24	Jun 05 07:17:38 PM PDT 24	3314642200 ps
T28	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.2700025245			Jun 05 07:13:11 PM PDT 24	Jun 05 07:43:16 PM PDT 24	8739108839 ps
T339	/workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.2038390246			Jun 05 07:32:31 PM PDT 24	Jun 05 07:41:28 PM PDT 24	4671291180 ps
T540	/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.1884879025			Jun 05 07:25:06 PM PDT 24	Jun 05 07:35:26 PM PDT 24	7486427400 ps
T221	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3113758484			Jun 05 07:21:21 PM PDT 24	Jun 05 08:17:51 PM PDT 24	34097298130 ps
T337	/workspace/coverage/default/14.chip_sw_all_escalation_resets.1906865132			Jun 05 07:42:39 PM PDT 24	Jun 05 07:51:23 PM PDT 24	5830527658 ps
T938	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1202288972			Jun 05 07:32:34 PM PDT 24	Jun 05 07:43:31 PM PDT 24	3666647224 ps
T213	/workspace/coverage/default/2.chip_sw_pattgen_ios.847957288			Jun 05 07:31:28 PM PDT 24	Jun 05 07:33:58 PM PDT 24	2338486560 ps
T222	/workspace/coverage/default/0.chip_sw_flash_crash_alert.3984196999			Jun 05 07:14:55 PM PDT 24	Jun 05 07:24:29 PM PDT 24	5780138116 ps
T24	/workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.3132500205			Jun 05 07:19:59 PM PDT 24	Jun 05 07:30:09 PM PDT 24	4663489545 ps
T166	/workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.2208713861			Jun 05 07:19:54 PM PDT 24	Jun 05 08:49:06 PM PDT 24	48826951520 ps
T747	/workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.4088400218			Jun 05 07:14:12 PM PDT 24	Jun 05 07:22:21 PM PDT 24	3605486856 ps
T123	/workspace/coverage/default/2.chip_sw_edn_kat.1032135434			Jun 05 07:33:44 PM PDT 24	Jun 05 07:46:27 PM PDT 24	3611178300 ps
T225	/workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.1793204776			Jun 05 07:26:14 PM PDT 24	Jun 05 07:56:15 PM PDT 24	8446151560 ps
T253	/workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.3455138672			Jun 05 07:36:31 PM PDT 24	Jun 05 07:42:26 PM PDT 24	4869052392 ps
T54	/workspace/coverage/default/2.rom_e2e_shutdown_exception_c.3678074234			Jun 05 07:42:47 PM PDT 24	Jun 05 08:34:16 PM PDT 24	14062265000 ps
T78	/workspace/coverage/default/1.chip_sw_alert_handler_entropy.3540246570			Jun 05 07:23:04 PM PDT 24	Jun 05 07:28:21 PM PDT 24	3501368623 ps
T29	/workspace/coverage/default/1.chip_sw_gpio.1724838583			Jun 05 07:19:23 PM PDT 24	Jun 05 07:26:46 PM PDT 24	3479289371 ps
T119	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.230871704			Jun 05 07:27:35 PM PDT 24	Jun 05 07:40:10 PM PDT 24	5564386688 ps
T190	/workspace/coverage/default/1.rom_volatile_raw_unlock.2769437032			Jun 05 07:29:12 PM PDT 24	Jun 05 07:31:10 PM PDT 24	2638935581 ps
T260	/workspace/coverage/default/1.chip_sw_rv_timer_smoketest.4118439196			Jun 05 07:29:53 PM PDT 24	Jun 05 07:34:55 PM PDT 24	2422805636 ps
T237	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.711550087			Jun 05 07:21:35 PM PDT 24	Jun 05 08:48:21 PM PDT 24	23004186032 ps
T749	/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.3565891145			Jun 05 07:43:52 PM PDT 24	Jun 05 07:49:31 PM PDT 24	3524130208 ps
T111	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2039442715			Jun 05 07:29:58 PM PDT 24	Jun 05 08:36:28 PM PDT 24	25089629764 ps
T737	/workspace/coverage/default/1.chip_sw_hmac_multistream.2257393909			Jun 05 07:25:16 PM PDT 24	Jun 05 07:53:48 PM PDT 24	6542782362 ps
T30	/workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.512660993			Jun 05 07:17:49 PM PDT 24	Jun 05 07:22:15 PM PDT 24	2714963689 ps
T939	/workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.3373500826			Jun 05 07:21:33 PM PDT 24	Jun 05 07:35:10 PM PDT 24	9150440440 ps
T748	/workspace/coverage/default/83.chip_sw_all_escalation_resets.4209258893			Jun 05 07:48:37 PM PDT 24	Jun 05 07:58:46 PM PDT 24	4874264020 ps
T68	/workspace/coverage/default/1.chip_jtag_mem_access.2508534260			Jun 05 07:19:29 PM PDT 24	Jun 05 07:47:13 PM PDT 24	14140683811 ps
T336	/workspace/coverage/default/2.chip_sw_otbn_randomness.3496653870			Jun 05 07:34:24 PM PDT 24	Jun 05 07:50:54 PM PDT 24	5991074924 ps
T940	/workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.422457391			Jun 05 07:25:30 PM PDT 24	Jun 05 07:34:11 PM PDT 24	4494677480 ps
T773	/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.2995508711			Jun 05 07:48:19 PM PDT 24	Jun 05 07:55:15 PM PDT 24	3736068840 ps
T323	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2729760587			Jun 05 07:38:07 PM PDT 24	Jun 05 07:52:11 PM PDT 24	4750379690 ps
T735	/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.2100511686			Jun 05 07:48:24 PM PDT 24	Jun 05 07:55:10 PM PDT 24	3931370064 ps
T941	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1756902364			Jun 05 07:38:20 PM PDT 24	Jun 05 07:42:47 PM PDT 24	2912558921 ps
T338	/workspace/coverage/default/41.chip_sw_all_escalation_resets.3237951972			Jun 05 07:44:52 PM PDT 24	Jun 05 07:55:14 PM PDT 24	5802250352 ps
T3	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.1359028840			Jun 05 07:17:39 PM PDT 24	Jun 05 07:21:06 PM PDT 24	2783634528 ps
T363	/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.2885216925			Jun 05 07:49:56 PM PDT 24	Jun 05 07:57:33 PM PDT 24	3987839624 ps
T227	/workspace/coverage/default/19.chip_sw_all_escalation_resets.632991411			Jun 05 07:43:48 PM PDT 24	Jun 05 07:55:26 PM PDT 24	5680341196 ps
T25	/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.752722291			Jun 05 07:20:16 PM PDT 24	Jun 05 07:24:08 PM PDT 24	2958733096 ps
T369	/workspace/coverage/default/74.chip_sw_all_escalation_resets.1811423303			Jun 05 07:48:17 PM PDT 24	Jun 05 07:59:03 PM PDT 24	5728127016 ps
T124	/workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.1525151043			Jun 05 07:33:53 PM PDT 24	Jun 05 07:43:47 PM PDT 24	5666604200 ps
T174	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.3416653358			Jun 05 07:14:41 PM PDT 24	Jun 05 07:23:10 PM PDT 24	3986726000 ps
T293	/workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.3390640359			Jun 05 07:29:31 PM PDT 24	Jun 05 07:34:39 PM PDT 24	2533723020 ps
T226	/workspace/coverage/default/1.chip_sw_alert_handler_escalation.2796886341			Jun 05 07:23:40 PM PDT 24	Jun 05 07:32:56 PM PDT 24	5166384450 ps
T55	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.1202725740			Jun 05 07:23:39 PM PDT 24	Jun 05 08:19:16 PM PDT 24	14103157688 ps
T294	/workspace/coverage/default/1.chip_plic_all_irqs_0.970777534			Jun 05 07:25:16 PM PDT 24	Jun 05 07:42:56 PM PDT 24	6191335560 ps
T295	/workspace/coverage/default/1.chip_sw_edn_sw_mode.3924247630			Jun 05 07:25:20 PM PDT 24	Jun 05 07:58:40 PM PDT 24	10347969848 ps
T296	/workspace/coverage/default/22.chip_sw_all_escalation_resets.3926219105			Jun 05 07:43:19 PM PDT 24	Jun 05 07:52:23 PM PDT 24	4755008450 ps
T147	/workspace/coverage/default/1.chip_sw_inject_scramble_seed.770281459			Jun 05 07:17:49 PM PDT 24	Jun 05 10:17:14 PM PDT 24	63888003925 ps
T69	/workspace/coverage/default/2.chip_tap_straps_testunlock0.3671195289			Jun 05 07:35:59 PM PDT 24	Jun 05 07:41:08 PM PDT 24	4069280315 ps
T156	/workspace/coverage/default/2.chip_plic_all_irqs_10.3145888519			Jun 05 07:39:12 PM PDT 24	Jun 05 07:51:05 PM PDT 24	4347289888 ps
T942	/workspace/coverage/default/1.chip_sw_entropy_src_smoketest.3525514854			Jun 05 07:31:44 PM PDT 24	Jun 05 07:42:05 PM PDT 24	3621921700 ps
T450	/workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.4001430837			Jun 05 07:25:15 PM PDT 24	Jun 05 08:08:00 PM PDT 24	31599083143 ps
T943	/workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.566609251			Jun 05 07:15:10 PM PDT 24	Jun 05 07:32:27 PM PDT 24	6082174460 ps
T332	/workspace/coverage/default/14.chip_sw_uart_rand_baudrate.3829056962			Jun 05 07:43:04 PM PDT 24	Jun 05 07:52:56 PM PDT 24	4260203214 ps
T944	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.3216934054			Jun 05 07:14:34 PM PDT 24	Jun 05 07:24:17 PM PDT 24	5774806630 ps
T108	/workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1466802757			Jun 05 07:32:21 PM PDT 24	Jun 05 07:42:44 PM PDT 24	19549593440 ps
T159	/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.2689482455			Jun 05 07:47:37 PM PDT 24	Jun 05 07:53:04 PM PDT 24	3208664440 ps
T449	/workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.42371968			Jun 05 07:31:23 PM PDT 24	Jun 05 07:54:10 PM PDT 24	8858333531 ps
T79	/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.2495968060			Jun 05 07:44:41 PM PDT 24	Jun 05 07:50:24 PM PDT 24	3814299844 ps
T91	/workspace/coverage/default/70.chip_sw_all_escalation_resets.2248604787			Jun 05 07:49:11 PM PDT 24	Jun 05 07:56:37 PM PDT 24	4501188832 ps
T92	/workspace/coverage/default/23.chip_sw_all_escalation_resets.1935443014			Jun 05 07:44:06 PM PDT 24	Jun 05 07:51:27 PM PDT 24	4189036154 ps
T93	/workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.163465980			Jun 05 07:15:27 PM PDT 24	Jun 05 07:22:05 PM PDT 24	4172426312 ps
T94	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.2482018747			Jun 05 07:23:45 PM PDT 24	Jun 05 08:52:48 PM PDT 24	22054795457 ps
T95	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.1159136305			Jun 05 07:21:06 PM PDT 24	Jun 05 07:32:47 PM PDT 24	4246288732 ps
T96	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.3573458281			Jun 05 07:14:36 PM PDT 24	Jun 05 07:41:49 PM PDT 24	8006241550 ps
T97	/workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.2072088637			Jun 05 07:12:15 PM PDT 24	Jun 05 07:34:53 PM PDT 24	8996885720 ps
T98	/workspace/coverage/default/1.rom_e2e_shutdown_output.3451252808			Jun 05 07:32:33 PM PDT 24	Jun 05 08:20:09 PM PDT 24	22801610340 ps
T99	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2650885476			Jun 05 07:15:27 PM PDT 24	Jun 05 07:23:54 PM PDT 24	5693944100 ps
T275	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.2547527377			Jun 05 07:12:21 PM PDT 24	Jun 05 07:22:48 PM PDT 24	7244536524 ps
T945	/workspace/coverage/default/0.chip_sw_clkmgr_jitter.2784270083			Jun 05 07:14:43 PM PDT 24	Jun 05 07:18:28 PM PDT 24	2681737181 ps
T533	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.34506387			Jun 05 07:13:31 PM PDT 24	Jun 05 07:29:21 PM PDT 24	4130921140 ps
T31	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.620741498			Jun 05 07:12:24 PM PDT 24	Jun 05 07:20:17 PM PDT 24	3475960506 ps
T946	/workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.1349781213			Jun 05 07:24:33 PM PDT 24	Jun 05 07:44:57 PM PDT 24	8158206950 ps
T201	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.659683753			Jun 05 07:13:22 PM PDT 24	Jun 05 07:24:19 PM PDT 24	4569295890 ps
T308	/workspace/coverage/default/1.chip_plic_all_irqs_20.432215136			Jun 05 07:28:44 PM PDT 24	Jun 05 07:40:01 PM PDT 24	4293852660 ps
T144	/workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.2800315785			Jun 05 07:31:26 PM PDT 24	Jun 05 07:39:12 PM PDT 24	6748889655 ps
T212	/workspace/coverage/default/16.chip_sw_uart_rand_baudrate.4009587377			Jun 05 07:43:20 PM PDT 24	Jun 05 07:55:20 PM PDT 24	4467938038 ps
T112	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.2701288923			Jun 05 07:32:42 PM PDT 24	Jun 05 08:25:42 PM PDT 24	18704978342 ps
T152	/workspace/coverage/default/0.chip_sw_otbn_smoketest.3417866179			Jun 05 07:18:19 PM PDT 24	Jun 05 07:56:50 PM PDT 24	11351858838 ps
T738	/workspace/coverage/default/1.chip_sw_hmac_oneshot.1425540565			Jun 05 07:24:49 PM PDT 24	Jun 05 07:31:36 PM PDT 24	3847216976 ps
T341	/workspace/coverage/default/12.chip_sw_uart_rand_baudrate.4005388971			Jun 05 07:41:59 PM PDT 24	Jun 05 08:17:00 PM PDT 24	13069113422 ps
T115	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.1701563245			Jun 05 07:26:35 PM PDT 24	Jun 05 07:38:24 PM PDT 24	4477974572 ps
T160	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.878529219			Jun 05 07:13:01 PM PDT 24	Jun 05 07:47:23 PM PDT 24	13516295050 ps
T217	/workspace/coverage/default/4.chip_sw_uart_tx_rx.484667238			Jun 05 07:41:21 PM PDT 24	Jun 05 07:54:13 PM PDT 24	4634655910 ps
T265	/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.283776349			Jun 05 07:33:40 PM PDT 24	Jun 05 08:09:30 PM PDT 24	8849891184 ps
T266	/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.3633887113			Jun 05 07:44:16 PM PDT 24	Jun 05 08:23:01 PM PDT 24	10748173624 ps
T184	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.369253292			Jun 05 07:36:09 PM PDT 24	Jun 05 07:43:07 PM PDT 24	5303034376 ps
T170	/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.3091405759			Jun 05 07:16:08 PM PDT 24	Jun 05 08:50:21 PM PDT 24	47641940058 ps
T947	/workspace/coverage/default/10.chip_sw_lc_ctrl_transition.1749224573			Jun 05 07:42:42 PM PDT 24	Jun 05 07:56:06 PM PDT 24	9859409792 ps
T349	/workspace/coverage/default/2.chip_sw_hmac_enc.3960267275			Jun 05 07:34:00 PM PDT 24	Jun 05 07:38:55 PM PDT 24	3494602446 ps
T220	/workspace/coverage/default/1.chip_tap_straps_prod.469926177			Jun 05 07:26:49 PM PDT 24	Jun 05 07:29:49 PM PDT 24	2584449919 ps
T8	/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.4240068364			Jun 05 07:16:00 PM PDT 24	Jun 05 07:24:10 PM PDT 24	4100008738 ps
T145	/workspace/coverage/default/2.chip_sw_sensor_ctrl_status.867200624			Jun 05 07:34:17 PM PDT 24	Jun 05 07:38:35 PM PDT 24	2643076394 ps
T424	/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.496518879			Jun 05 07:49:37 PM PDT 24	Jun 05 07:54:18 PM PDT 24	3609650584 ps
T358	/workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.392665765			Jun 05 07:31:36 PM PDT 24	Jun 05 08:01:24 PM PDT 24	10697628878 ps
T425	/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.2062897004			Jun 05 07:49:16 PM PDT 24	Jun 05 07:55:40 PM PDT 24	3282395280 ps
T426	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.4198482529			Jun 05 07:11:53 PM PDT 24	Jun 05 07:23:52 PM PDT 24	4331931750 ps
T364	/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.3719007832			Jun 05 07:49:05 PM PDT 24	Jun 05 07:55:04 PM PDT 24	4410730256 ps
T427	/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.1623506307			Jun 05 07:22:19 PM PDT 24	Jun 05 08:24:32 PM PDT 24	14795589960 ps
T276	/workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.500049124			Jun 05 07:26:15 PM PDT 24	Jun 05 07:31:16 PM PDT 24	3307293189 ps
T71	/workspace/coverage/default/4.chip_tap_straps_dev.3511513417			Jun 05 07:41:04 PM PDT 24	Jun 05 07:50:43 PM PDT 24	6163839251 ps
T21	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.2023933672			Jun 05 07:20:58 PM PDT 24	Jun 05 07:25:43 PM PDT 24	2960326648 ps
T70	/workspace/coverage/default/3.chip_tap_straps_testunlock0.3485573155			Jun 05 07:40:47 PM PDT 24	Jun 05 07:44:11 PM PDT 24	3651012890 ps
T267	/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.3840775342			Jun 05 07:42:47 PM PDT 24	Jun 05 08:36:33 PM PDT 24	12441461668 ps
T538	/workspace/coverage/default/71.chip_sw_all_escalation_resets.2477296303			Jun 05 07:47:41 PM PDT 24	Jun 05 07:55:27 PM PDT 24	4912409696 ps
T948	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac.4069142234			Jun 05 07:15:16 PM PDT 24	Jun 05 07:21:08 PM PDT 24	3553672206 ps
T346	/workspace/coverage/default/88.chip_sw_all_escalation_resets.1370667976			Jun 05 07:48:51 PM PDT 24	Jun 05 08:00:38 PM PDT 24	4488913528 ps
T347	/workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.1614463747			Jun 05 07:21:17 PM PDT 24	Jun 05 07:35:20 PM PDT 24	5601036340 ps
T949	/workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.4060331139			Jun 05 07:29:53 PM PDT 24	Jun 05 07:36:15 PM PDT 24	5239129304 ps
T116	/workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.470771892			Jun 05 07:34:48 PM PDT 24	Jun 05 07:56:18 PM PDT 24	6754647511 ps
T146	/workspace/coverage/default/0.chip_sw_sensor_ctrl_status.3008685451			Jun 05 07:13:44 PM PDT 24	Jun 05 07:18:16 PM PDT 24	2507268969 ps
T950	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.4095358040			Jun 05 07:24:06 PM PDT 24	Jun 05 08:09:48 PM PDT 24	10794438680 ps
T214	/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.979214757			Jun 05 07:18:49 PM PDT 24	Jun 05 07:31:55 PM PDT 24	4315929000 ps
T951	/workspace/coverage/default/0.chip_sw_rstmgr_sw_req.4045805253			Jun 05 07:13:34 PM PDT 24	Jun 05 07:20:53 PM PDT 24	4594870040 ps
T202	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.3493231409			Jun 05 07:12:33 PM PDT 24	Jun 05 07:17:41 PM PDT 24	3307498370 ps
T38	/workspace/coverage/default/2.chip_sw_gpio_smoketest.4261943877			Jun 05 07:37:51 PM PDT 24	Jun 05 07:42:59 PM PDT 24	3497317395 ps
T385	/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.3525985076			Jun 05 07:46:22 PM PDT 24	Jun 05 07:53:51 PM PDT 24	3600574520 ps
T781	/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.1623063266			Jun 05 07:50:37 PM PDT 24	Jun 05 07:57:26 PM PDT 24	3909392198 ps
T80	/workspace/coverage/default/2.chip_sw_alert_handler_entropy.2272171534			Jun 05 07:34:27 PM PDT 24	Jun 05 07:38:17 PM PDT 24	2938197309 ps
T350	/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.2246023425			Jun 05 07:23:51 PM PDT 24	Jun 05 07:29:05 PM PDT 24	3460284113 ps
T952	/workspace/coverage/default/0.chip_sw_otbn_randomness.326598442			Jun 05 07:13:05 PM PDT 24	Jun 05 07:31:01 PM PDT 24	6024025146 ps
T148	/workspace/coverage/default/2.chip_sw_inject_scramble_seed.3745994330			Jun 05 07:30:06 PM PDT 24	Jun 05 10:24:57 PM PDT 24	65241717667 ps
T953	/workspace/coverage/default/1.chip_sw_kmac_mode_cshake.2942918677			Jun 05 07:26:11 PM PDT 24	Jun 05 07:31:46 PM PDT 24	3329848784 ps
T954	/workspace/coverage/default/2.chip_sw_entropy_src_kat_test.3183878573			Jun 05 07:34:19 PM PDT 24	Jun 05 07:38:41 PM PDT 24	2823589312 ps
T32	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.2175093066			Jun 05 07:13:43 PM PDT 24	Jun 05 07:48:13 PM PDT 24	23890147476 ps
T776	/workspace/coverage/default/73.chip_sw_all_escalation_resets.165554358			Jun 05 07:49:36 PM PDT 24	Jun 05 07:59:38 PM PDT 24	4327216328 ps
T218	/workspace/coverage/default/2.chip_sw_uart_tx_rx.1373952351			Jun 05 07:30:31 PM PDT 24	Jun 05 07:42:09 PM PDT 24	3871714448 ps
T775	/workspace/coverage/default/6.chip_sw_all_escalation_resets.391400795			Jun 05 07:40:59 PM PDT 24	Jun 05 07:52:41 PM PDT 24	5333783100 ps
T762	/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.3937998015			Jun 05 07:49:35 PM PDT 24	Jun 05 07:56:04 PM PDT 24	4065789212 ps
T176	/workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.3806138278			Jun 05 07:26:41 PM PDT 24	Jun 05 07:31:38 PM PDT 24	2913003000 ps
T303	/workspace/coverage/default/1.chip_sw_edn_entropy_reqs.631967063			Jun 05 07:24:00 PM PDT 24	Jun 05 07:43:18 PM PDT 24	5996069320 ps
T261	/workspace/coverage/default/1.chip_sw_rv_timer_irq.3242319220			Jun 05 07:22:07 PM PDT 24	Jun 05 07:26:50 PM PDT 24	3059171624 ps
T304	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.343175030			Jun 05 07:40:43 PM PDT 24	Jun 05 07:51:04 PM PDT 24	4573709282 ps
T228	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.2612971769			Jun 05 07:11:54 PM PDT 24	Jun 05 07:28:44 PM PDT 24	6169245528 ps
T305	/workspace/coverage/default/2.chip_sw_flash_ctrl_access.2060056232			Jun 05 07:32:15 PM PDT 24	Jun 05 07:47:47 PM PDT 24	5851708308 ps
T83	/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.336153723			Jun 05 07:45:09 PM PDT 24	Jun 05 07:51:26 PM PDT 24	3426803400 ps
T51	/workspace/coverage/default/0.chip_sw_spi_device_tpm.1923668501			Jun 05 07:11:51 PM PDT 24	Jun 05 07:18:09 PM PDT 24	4206703381 ps
T306	/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.1575560269			Jun 05 07:43:43 PM PDT 24	Jun 05 07:51:37 PM PDT 24	3275823800 ps
T307	/workspace/coverage/default/0.chip_sw_example_concurrency.3725446373			Jun 05 07:11:18 PM PDT 24	Jun 05 07:14:18 PM PDT 24	3003676116 ps
T772	/workspace/coverage/default/49.chip_sw_all_escalation_resets.3624765636			Jun 05 07:46:45 PM PDT 24	Jun 05 07:55:16 PM PDT 24	5524464300 ps
T955	/workspace/coverage/default/1.chip_sw_rstmgr_smoketest.3114302576			Jun 05 07:30:35 PM PDT 24	Jun 05 07:33:58 PM PDT 24	2014463534 ps
T704	/workspace/coverage/default/91.chip_sw_all_escalation_resets.2321949103			Jun 05 07:49:41 PM PDT 24	Jun 05 08:00:08 PM PDT 24	5511009356 ps
T65	/workspace/coverage/default/4.chip_tap_straps_rma.1055130864			Jun 05 07:40:44 PM PDT 24	Jun 05 07:46:27 PM PDT 24	4261378534 ps
T203	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.2181572534			Jun 05 07:32:18 PM PDT 24	Jun 05 07:43:05 PM PDT 24	4754231310 ps
T765	/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.2445508131			Jun 05 07:49:33 PM PDT 24	Jun 05 07:56:35 PM PDT 24	3127918956 ps
T130	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.2779790460			Jun 05 07:27:29 PM PDT 24	Jun 05 07:34:38 PM PDT 24	6181442892 ps
T956	/workspace/coverage/default/0.chip_sw_example_manufacturer.1100703968			Jun 05 07:11:27 PM PDT 24	Jun 05 07:14:16 PM PDT 24	2666229740 ps
T229	/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.65941339			Jun 05 07:45:00 PM PDT 24	Jun 05 07:51:16 PM PDT 24	3378394028 ps
T7	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.2560832919			Jun 05 07:14:45 PM PDT 24	Jun 05 07:43:00 PM PDT 24	23841685178 ps
T957	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1457200348			Jun 05 07:24:22 PM PDT 24	Jun 05 07:50:34 PM PDT 24	12834650176 ps
T958	/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.3403331025			Jun 05 07:15:34 PM PDT 24	Jun 05 07:28:12 PM PDT 24	7250149718 ps
T739	/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.1683649118			Jun 05 07:43:52 PM PDT 24	Jun 05 07:50:38 PM PDT 24	3436063000 ps
T959	/workspace/coverage/default/2.chip_sw_alert_handler_escalation.2654770936			Jun 05 07:33:21 PM PDT 24	Jun 05 07:44:24 PM PDT 24	4844564892 ps
T177	/workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.1386196882			Jun 05 07:38:35 PM PDT 24	Jun 05 07:43:48 PM PDT 24	3244034042 ps
T763	/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.2506201518			Jun 05 07:47:32 PM PDT 24	Jun 05 07:54:05 PM PDT 24	3560614204 ps
T392	/workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.4054898039			Jun 05 07:39:05 PM PDT 24	Jun 05 07:47:59 PM PDT 24	6067184198 ps
T960	/workspace/coverage/default/1.chip_sw_hmac_smoketest.1678399653			Jun 05 07:31:47 PM PDT 24	Jun 05 07:36:58 PM PDT 24	2838332714 ps
T961	/workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.2220298094			Jun 05 07:17:45 PM PDT 24	Jun 05 07:25:51 PM PDT 24	6536486220 ps
T962	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.671884071			Jun 05 07:29:51 PM PDT 24	Jun 05 07:41:04 PM PDT 24	3748479720 ps
T60	/workspace/coverage/default/0.chip_sw_alert_test.860932891			Jun 05 07:14:36 PM PDT 24	Jun 05 07:19:15 PM PDT 24	3103960832 ps
T963	/workspace/coverage/default/1.chip_sw_kmac_mode_kmac.3957519417			Jun 05 07:25:05 PM PDT 24	Jun 05 07:31:12 PM PDT 24	3370760036 ps
T239	/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.3433150689			Jun 05 07:11:32 PM PDT 24	Jun 05 08:43:10 PM PDT 24	46102404042 ps
T964	/workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.381552751			Jun 05 07:32:22 PM PDT 24	Jun 05 07:52:03 PM PDT 24	5011409112 ps
T965	/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.875319530			Jun 05 07:12:09 PM PDT 24	Jun 05 07:23:20 PM PDT 24	4107491750 ps
T777	/workspace/coverage/default/1.chip_sw_aes_masking_off.3330027258			Jun 05 07:22:39 PM PDT 24	Jun 05 07:27:41 PM PDT 24	3038959887 ps
T331	/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.320695154			Jun 05 07:42:26 PM PDT 24	Jun 05 08:05:50 PM PDT 24	8373166000 ps
T120	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.4270928924			Jun 05 07:28:09 PM PDT 24	Jun 05 07:39:42 PM PDT 24	4484191888 ps
T344	/workspace/coverage/default/0.chip_sw_pattgen_ios.1750656246			Jun 05 07:11:47 PM PDT 24	Jun 05 07:18:01 PM PDT 24	3247030192 ps
T378	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.2990142288			Jun 05 07:21:31 PM PDT 24	Jun 05 09:01:25 PM PDT 24	22401157668 ps
T966	/workspace/coverage/default/1.chip_sival_flash_info_access.4058316971			Jun 05 07:18:16 PM PDT 24	Jun 05 07:22:25 PM PDT 24	2321286178 ps
T753	/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.75944506			Jun 05 07:46:25 PM PDT 24	Jun 05 07:54:35 PM PDT 24	4472039702 ps
T254	/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.3941110572			Jun 05 07:46:45 PM PDT 24	Jun 05 07:52:43 PM PDT 24	4402910760 ps
T297	/workspace/coverage/default/2.chip_tap_straps_prod.4035469321			Jun 05 07:36:37 PM PDT 24	Jun 05 07:38:56 PM PDT 24	2573307056 ps
T33	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.1415700712			Jun 05 07:25:14 PM PDT 24	Jun 05 07:51:26 PM PDT 24	22799143900 ps
T26	/workspace/coverage/default/1.chip_sw_spi_device_pass_through.2171802114			Jun 05 07:19:51 PM PDT 24	Jun 05 07:35:56 PM PDT 24	8627646031 ps
T255	/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.3926866565			Jun 05 07:45:06 PM PDT 24	Jun 05 07:52:56 PM PDT 24	4350596456 ps
T249	/workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.258303665			Jun 05 07:20:41 PM PDT 24	Jun 05 10:25:08 PM PDT 24	254940157282 ps
T298	/workspace/coverage/default/2.chip_sw_rv_plic_smoketest.4213373139			Jun 05 07:38:48 PM PDT 24	Jun 05 07:41:58 PM PDT 24	2413629098 ps
T299	/workspace/coverage/default/40.chip_sw_all_escalation_resets.2544235144			Jun 05 07:46:15 PM PDT 24	Jun 05 07:56:07 PM PDT 24	4857184418 ps
T171	/workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.285897322			Jun 05 07:15:54 PM PDT 24	Jun 05 07:18:11 PM PDT 24	3103472508 ps
T269	/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.121589889			Jun 05 07:45:37 PM PDT 24	Jun 05 07:53:00 PM PDT 24	4408185134 ps
T250	/workspace/coverage/default/2.chip_sw_otbn_mem_scramble.694053461			Jun 05 07:32:47 PM PDT 24	Jun 05 07:41:04 PM PDT 24	3371277416 ps
T113	/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.1607238533			Jun 05 07:39:36 PM PDT 24	Jun 05 08:28:17 PM PDT 24	20761112998 ps
T251	/workspace/coverage/default/26.chip_sw_all_escalation_resets.2387755127			Jun 05 07:43:49 PM PDT 24	Jun 05 07:55:11 PM PDT 24	5101985226 ps
T967	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.3343923966			Jun 05 07:21:06 PM PDT 24	Jun 05 07:28:19 PM PDT 24	4538024554 ps
T968	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.3799164055			Jun 05 07:33:33 PM PDT 24	Jun 05 07:42:18 PM PDT 24	6081402577 ps
T721	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.3856969470			Jun 05 07:14:14 PM PDT 24	Jun 05 07:19:13 PM PDT 24	2603880760 ps
T351	/workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.3075421416			Jun 05 07:29:46 PM PDT 24	Jun 05 07:38:32 PM PDT 24	3491895296 ps
T779	/workspace/coverage/default/28.chip_sw_all_escalation_resets.3274715810			Jun 05 07:43:57 PM PDT 24	Jun 05 07:53:18 PM PDT 24	5655482024 ps
T354	/workspace/coverage/default/66.chip_sw_all_escalation_resets.997753322			Jun 05 07:47:28 PM PDT 24	Jun 05 07:58:05 PM PDT 24	6020481810 ps
T778	/workspace/coverage/default/16.chip_sw_all_escalation_resets.370613869			Jun 05 07:43:13 PM PDT 24	Jun 05 07:54:40 PM PDT 24	5746410946 ps
T969	/workspace/coverage/default/18.chip_sw_uart_rand_baudrate.2927929884			Jun 05 07:45:46 PM PDT 24	Jun 05 08:19:53 PM PDT 24	13419848184 ps
T780	/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.786352475			Jun 05 07:48:32 PM PDT 24	Jun 05 07:53:56 PM PDT 24	3600887078 ps
T309	/workspace/coverage/default/90.chip_sw_all_escalation_resets.3600059049			Jun 05 07:49:32 PM PDT 24	Jun 05 07:58:18 PM PDT 24	4805254640 ps
T312	/workspace/coverage/default/0.chip_sw_rv_timer_smoketest.2174269953			Jun 05 07:21:18 PM PDT 24	Jun 05 07:27:11 PM PDT 24	3430263608 ps
T313	/workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.1359473153			Jun 05 07:23:41 PM PDT 24	Jun 05 07:28:11 PM PDT 24	3078686360 ps
T314	/workspace/coverage/default/0.chip_sw_clkmgr_smoketest.3396527580			Jun 05 07:17:13 PM PDT 24	Jun 05 07:20:31 PM PDT 24	2693702074 ps
T172	/workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.2181570685			Jun 05 07:16:06 PM PDT 24	Jun 05 07:18:44 PM PDT 24	2330429458 ps
T315	/workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.3414466081			Jun 05 07:29:41 PM PDT 24	Jun 05 07:34:15 PM PDT 24	2471646152 ps
T316	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.1704238084			Jun 05 07:31:52 PM PDT 24	Jun 05 08:39:06 PM PDT 24	16757520712 ps