Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.rstmgr_aon_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	132119	1			T73	4		T74	89		T75	16
values[2]	8523	1			T74	6		T128	2		T440	1
values[3]	3007	1			T536	1		T537	21		T750	22
values[4]	1728	1			T536	1		T537	31		T750	5
values[5]	1082	1			T536	1		T537	33		T417	1
values[6]	709	1			T536	1		T537	28		T417	1
values[7]	461	1			T536	1		T537	31		T417	1
values[8]	368	1			T536	1		T537	12		T417	1
values[9]	343	1			T536	1		T537	4		T417	1
values[10]	256	1			T536	1		T417	1		T855	1
values[11]	261	1			T536	1		T417	1		T855	1
values[12]	218	1			T536	1		T417	1		T855	1
values[13]	192	1			T536	1		T417	1		T855	1
values[14]	191	1			T536	1		T417	1		T855	1
values[15]	204	1			T536	1		T417	1		T855	1
values[16]	215	1			T536	1		T417	1		T855	1
values[17]	205	1			T536	1		T417	1		T855	1
values[18]	195	1			T536	1		T417	1		T855	1
values[19]	199	1			T536	1		T417	1		T855	1
values[20]	186	1			T536	1		T417	1		T855	1
values[21]	192	1			T536	1		T417	1		T855	1
values[22]	211	1			T536	1		T417	1		T855	1
values[23]	222	1			T536	1		T417	1		T855	1
values[24]	226	1			T536	1		T417	1		T855	1
values[25]	180	1			T536	1		T417	1		T855	1
values[26]	231	1			T536	1		T417	1		T855	1
values[27]	214	1			T536	1		T417	1		T855	1
values[28]	206	1			T536	1		T417	1		T855	1
values[29]	181	1			T536	1		T417	1		T855	1
values[30]	184	1			T536	1		T417	1		T855	1
values[31]	160	1			T536	1		T417	1		T855	1
values[32]	162	1			T536	1		T417	1		T855	1
values[33]	173	1			T536	1		T417	1		T855	1
values[34]	199	1			T536	1		T417	1		T855	1
values[35]	171	1			T536	1		T417	1		T855	1
values[36]	186	1			T536	1		T417	1		T855	1
values[37]	191	1			T536	1		T417	1		T855	1
values[38]	191	1			T536	1		T417	1		T855	1
values[39]	177	1			T536	1		T417	1		T855	1
values[40]	155	1			T536	1		T417	1		T855	1
values[41]	172	1			T536	1		T417	1		T855	1
values[42]	152	1			T536	1		T417	2		T855	1
values[43]	149	1			T536	2		T417	1		T855	1
values[44]	184	1			T536	1		T417	1		T855	1
values[45]	122	1			T536	1		T417	1		T855	1
values[46]	183	1			T536	1		T417	1		T855	1
values[47]	147	1			T536	1		T417	1		T855	1
values[48]	169	1			T536	1		T417	1		T855	1
values[49]	142	1			T536	1		T417	1		T855	1
values[50]	162	1			T536	1		T417	1		T855	1
values[51]	161	1			T536	1		T417	1		T855	1
values[52]	173	1			T536	1		T417	1		T855	1
values[53]	178	1			T536	1		T417	1		T855	1
values[54]	181	1			T536	1		T417	1		T855	1
values[55]	197	1			T536	1		T417	1		T855	1
values[56]	160	1			T536	1		T417	1		T855	1
values[57]	136	1			T536	1		T417	1		T855	1
values[58]	172	1			T536	1		T417	1		T855	1
values[59]	179	1			T536	1		T417	1		T855	1
values[60]	154	1			T536	1		T417	1		T855	1
values[61]	129	1			T536	1		T417	1		T855	1
values[62]	135	1			T536	1		T417	1		T855	1
values[63]	121	1			T536	1		T417	1		T855	1
values[64]	96	1			T536	1		T417	1		T855	1
values[65]	108	1			T536	1		T417	1		T855	1
values[66]	80	1			T536	1		T417	1		T855	1
values[67]	100	1			T536	1		T417	1		T855	1
values[68]	104	1			T536	1		T417	1		T855	1
values[69]	90	1			T536	1		T417	1		T855	1
values[70]	67	1			T536	1		T417	1		T855	1
values[71]	63	1			T536	1		T417	1		T855	1
values[72]	64	1			T536	1		T417	1		T855	1
values[73]	64	1			T536	1		T417	1		T855	1
values[74]	69	1			T536	1		T417	1		T855	1
values[75]	66	1			T536	1		T417	1		T855	1
values[76]	56	1			T536	1		T417	1		T855	1
values[77]	55	1			T536	1		T417	1		T855	1
values[78]	63	1			T536	1		T417	1		T855	1
values[79]	73	1			T536	1		T417	1		T855	1
values[80]	71	1			T536	1		T417	1		T855	1
values[81]	70	1			T536	1		T417	1		T855	1
values[82]	72	1			T536	1		T417	1		T855	1
values[83]	65	1			T536	1		T417	1		T855	1
values[84]	50	1			T536	1		T417	1		T855	1
values[85]	69	1			T536	1		T417	1		T855	1
values[86]	66	1			T536	1		T417	1		T855	1
values[87]	66	1			T536	1		T417	1		T855	1
values[88]	65	1			T536	1		T417	1		T855	1
values[89]	66	1			T536	1		T417	2		T855	1
values[90]	63	1			T536	1		T417	9		T855	1
values[91]	61	1			T536	1		T417	1		T855	1
values[92]	59	1			T536	1		T417	1		T855	1
values[93]	51	1			T536	1		T417	5		T855	1
values[94]	68	1			T536	1		T417	1		T855	1
values[95]	74	1			T536	1		T417	4		T855	1
values[96]	48	1			T536	1		T417	2		T855	1
values[97]	66	1			T536	1		T417	4		T855	1
values[98]	60	1			T536	1		T417	4		T855	1
values[99]	69	1			T536	1		T417	3		T855	1
values[100]	65	1			T536	1		T417	2		T855	1
values[101]	72	1			T536	1		T417	1		T855	1
values[102]	58	1			T536	1		T417	2		T855	1
values[103]	64	1			T536	1		T417	3		T855	1
values[104]	63	1			T536	1		T417	1		T855	1
values[105]	67	1			T536	1		T417	2		T855	1
values[106]	68	1			T536	1		T417	3		T855	1
values[107]	73	1			T536	1		T417	2		T855	2
values[108]	62	1			T536	1		T417	1		T855	3
values[109]	67	1			T536	1		T417	1		T855	8
values[110]	75	1			T536	1		T417	3		T855	1
values[111]	74	1			T536	1		T417	1		T855	2
values[112]	74	1			T536	1		T417	2		T855	2
values[113]	61	1			T536	1		T417	1		T855	1
values[114]	82	1			T536	1		T417	3		T855	2
values[115]	81	1			T536	1		T417	1		T855	1
values[116]	80	1			T536	1		T417	1		T855	1
values[117]	70	1			T536	1		T417	1		T855	2
values[118]	59	1			T536	1		T417	3		T855	7
values[119]	62	1			T536	1		T417	2		T855	1
values[120]	64	1			T536	2		T417	1		T855	1
values[121]	62	1			T536	4		T417	1		T855	1
values[122]	67	1			T536	1		T417	1		T855	1
values[123]	67	1			T536	3		T417	3		T855	1
values[124]	75	1			T536	2		T417	1		T855	2
values[125]	95	1			T536	1		T417	1		T855	4
values[126]	132	1			T536	3		T417	2		T855	3
values[127]	878	1			T536	39		T417	32		T855	28
values[128]	7108	1			T536	327		T417	292		T855	270