Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__regs_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	152900	1			T73	4		T74	71		T75	14
values[2]	4837	1			T74	7		T128	114		T537	3
values[3]	2537	1			T128	43		T541	1		T549	22
values[4]	1778	1			T128	25		T541	1		T549	21
values[5]	1289	1			T128	12		T541	1		T549	24
values[6]	1008	1			T541	1		T549	33		T862	4
values[7]	930	1			T541	1		T549	30		T862	2
values[8]	867	1			T541	1		T549	25		T862	6
values[9]	767	1			T541	1		T549	21		T862	9
values[10]	617	1			T541	1		T549	28		T862	8
values[11]	520	1			T541	1		T549	27		T862	13
values[12]	529	1			T541	1		T549	13		T862	20
values[13]	562	1			T541	1		T862	5		T507	24
values[14]	529	1			T541	1		T862	4		T507	22
values[15]	440	1			T541	1		T862	2		T507	24
values[16]	353	1			T541	1		T862	2		T507	34
values[17]	248	1			T541	1		T862	1		T507	14
values[18]	234	1			T541	1		T862	4		T507	12
values[19]	215	1			T541	1		T862	8		T507	14
values[20]	211	1			T541	1		T507	3		T476	2
values[21]	190	1			T541	1		T476	2		T888	2
values[22]	191	1			T541	1		T476	2		T888	2
values[23]	208	1			T541	1		T476	2		T888	2
values[24]	225	1			T541	1		T476	2		T888	1
values[25]	209	1			T541	1		T476	2		T888	1
values[26]	204	1			T541	1		T476	2		T888	3
values[27]	174	1			T541	1		T476	2		T888	4
values[28]	174	1			T541	1		T476	2		T888	8
values[29]	204	1			T541	1		T476	2		T888	5
values[30]	182	1			T541	1		T476	2		T888	4
values[31]	195	1			T541	1		T476	2		T888	1
values[32]	191	1			T541	1		T476	2		T888	3
values[33]	161	1			T541	1		T476	2		T888	2
values[34]	146	1			T541	1		T476	2		T888	1
values[35]	123	1			T541	1		T476	2		T888	1
values[36]	123	1			T541	1		T476	2		T888	3
values[37]	121	1			T541	1		T476	2		T888	4
values[38]	99	1			T541	1		T476	2		T888	6
values[39]	90	1			T541	1		T476	2		T888	1
values[40]	90	1			T541	1		T476	2		T888	2
values[41]	83	1			T541	1		T476	2		T888	3
values[42]	92	1			T541	1		T476	2		T888	2
values[43]	81	1			T541	1		T476	2		T888	1
values[44]	78	1			T541	1		T476	2		T888	1
values[45]	87	1			T541	1		T476	2		T888	3
values[46]	84	1			T541	1		T476	2		T888	3
values[47]	98	1			T541	1		T476	2		T888	2
values[48]	79	1			T541	1		T476	2		T888	3
values[49]	68	1			T541	1		T476	2		T888	2
values[50]	79	1			T541	1		T476	2		T888	1
values[51]	81	1			T541	1		T476	2		T888	1
values[52]	92	1			T541	1		T476	2		T888	6
values[53]	96	1			T541	1		T476	2		T888	4
values[54]	102	1			T541	1		T476	2		T888	3
values[55]	95	1			T541	1		T476	2		T888	1
values[56]	91	1			T541	1		T476	2		T888	2
values[57]	96	1			T541	1		T476	2		T888	2
values[58]	112	1			T541	1		T476	2		T888	2
values[59]	124	1			T541	1		T476	2		T888	2
values[60]	75	1			T541	1		T476	2		T888	2
values[61]	71	1			T541	1		T476	2		T888	2
values[62]	74	1			T541	1		T476	2		T888	2
values[63]	71	1			T541	1		T476	2		T888	1
values[64]	63	1			T541	1		T476	2		T888	1
values[65]	70	1			T541	1		T476	2		T888	1
values[66]	78	1			T541	1		T476	2		T888	8
values[67]	77	1			T541	1		T476	2		T888	4
values[68]	76	1			T541	1		T476	2		T888	5
values[69]	63	1			T541	1		T476	2		T888	4
values[70]	95	1			T541	1		T476	2		T888	8
values[71]	93	1			T541	1		T476	2		T888	10
values[72]	84	1			T541	1		T476	2		T888	3
values[73]	77	1			T541	1		T476	2		T888	1
values[74]	77	1			T541	1		T476	2		T888	2
values[75]	85	1			T541	1		T476	2		T888	2
values[76]	76	1			T541	1		T476	2		T888	5
values[77]	78	1			T541	1		T476	2		T888	6
values[78]	61	1			T541	1		T476	2		T888	3
values[79]	75	1			T541	1		T476	2		T888	2
values[80]	78	1			T541	1		T476	2		T888	1
values[81]	69	1			T541	1		T476	2		T888	3
values[82]	76	1			T541	1		T476	2		T888	3
values[83]	95	1			T541	1		T476	2		T888	3
values[84]	71	1			T541	1		T476	3		T888	1
values[85]	81	1			T541	2		T476	2		T888	4
values[86]	74	1			T541	3		T476	2		T888	1
values[87]	89	1			T541	2		T476	2		T888	1
values[88]	90	1			T541	2		T476	2		T888	1
values[89]	82	1			T541	6		T476	2		T888	2
values[90]	105	1			T541	17		T476	2		T888	2
values[91]	99	1			T541	6		T476	2		T888	2
values[92]	77	1			T541	1		T476	2		T888	3
values[93]	107	1			T541	5		T476	2		T888	3
values[94]	94	1			T541	1		T476	2		T888	1
values[95]	91	1			T541	3		T476	2		T888	2
values[96]	100	1			T541	2		T476	2		T888	3
values[97]	94	1			T541	4		T476	2		T888	2
values[98]	109	1			T541	2		T476	2		T888	10
values[99]	94	1			T541	1		T476	2		T888	7
values[100]	96	1			T541	2		T476	2		T888	5
values[101]	119	1			T541	1		T476	2		T888	9
values[102]	124	1			T541	5		T476	2		T888	2
values[103]	115	1			T541	2		T476	2		T888	2
values[104]	96	1			T541	2		T476	2		T888	4
values[105]	118	1			T541	2		T476	2		T888	4
values[106]	125	1			T541	1		T476	2		T888	7
values[107]	135	1			T541	2		T476	2		T888	8
values[108]	143	1			T541	3		T476	2		T888	12
values[109]	122	1			T541	2		T476	2		T888	5
values[110]	150	1			T541	3		T476	2		T888	4
values[111]	129	1			T541	2		T476	2		T888	5
values[112]	129	1			T541	4		T476	2		T888	3
values[113]	120	1			T541	3		T476	2		T888	3
values[114]	126	1			T541	1		T476	2		T888	1
values[115]	140	1			T541	5		T476	2		T888	10
values[116]	126	1			T541	5		T476	2		T888	3
values[117]	124	1			T541	3		T476	2		T888	3
values[118]	136	1			T541	1		T476	2		T888	4
values[119]	114	1			T541	3		T476	2		T888	6
values[120]	148	1			T541	2		T476	2		T888	4
values[121]	115	1			T541	4		T476	2		T888	6
values[122]	140	1			T541	4		T476	2		T888	4
values[123]	175	1			T541	2		T476	2		T888	8
values[124]	304	1			T541	4		T476	2		T888	7
values[125]	700	1			T541	1		T476	4		T888	21
values[126]	1194	1			T541	10		T476	27		T888	28
values[127]	3374	1			T541	102		T476	231		T888	22
values[128]	5717	1			T541	191		T476	420		T888	2