Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.rv_timer_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	133922	1			T73	10		T74	80		T75	10
values[2]	9812	1			T74	8		T128	107		T537	5
values[3]	3766	1			T128	36		T537	1		T419	31
values[4]	2090	1			T128	15		T419	28		T549	56
values[5]	1462	1			T128	14		T419	10		T549	18
values[6]	970	1			T128	5		T419	2		T549	2
values[7]	749	1			T128	6		T419	2		T640	22
values[8]	649	1			T128	7		T640	4		T750	10
values[9]	585	1			T128	6		T640	6		T750	10
values[10]	486	1			T128	1		T640	3		T750	4
values[11]	444	1			T128	2		T750	5		T418	6
values[12]	464	1			T128	7		T750	17		T418	8
values[13]	400	1			T128	2		T750	7		T418	15
values[14]	363	1			T128	2		T750	4		T418	9
values[15]	330	1			T128	1		T750	5		T418	8
values[16]	332	1			T128	3		T750	4		T418	7
values[17]	353	1			T128	2		T750	5		T418	10
values[18]	361	1			T128	1		T750	9		T418	7
values[19]	307	1			T128	2		T750	20		T418	1
values[20]	312	1			T128	4		T750	5		T418	1
values[21]	301	1			T128	3		T750	5		T418	1
values[22]	339	1			T128	1		T750	10		T418	9
values[23]	360	1			T128	2		T750	4		T418	6
values[24]	307	1			T128	2		T750	4		T418	5
values[25]	316	1			T128	6		T750	9		T418	2
values[26]	287	1			T128	5		T750	10		T418	6
values[27]	299	1			T128	3		T750	3		T418	6
values[28]	300	1			T128	4		T750	4		T418	5
values[29]	298	1			T128	3		T750	19		T418	3
values[30]	281	1			T128	1		T750	3		T418	2
values[31]	315	1			T128	4		T750	11		T418	1
values[32]	332	1			T128	6		T750	7		T418	1
values[33]	308	1			T128	8		T750	6		T418	2
values[34]	348	1			T128	3		T750	19		T418	1
values[35]	318	1			T128	2		T750	24		T418	3
values[36]	304	1			T128	1		T750	3		T418	11
values[37]	347	1			T128	5		T750	5		T418	4
values[38]	263	1			T128	1		T750	6		T418	1
values[39]	304	1			T128	3		T750	9		T418	4
values[40]	309	1			T128	3		T750	2		T418	1
values[41]	367	1			T128	1		T750	11		T418	3
values[42]	289	1			T128	1		T750	4		T418	1
values[43]	323	1			T128	2		T750	7		T418	2
values[44]	322	1			T128	6		T750	7		T418	1
values[45]	285	1			T128	6		T750	6		T418	5
values[46]	266	1			T128	8		T750	6		T418	7
values[47]	267	1			T128	2		T750	2		T418	2
values[48]	249	1			T128	3		T750	8		T418	3
values[49]	239	1			T128	9		T750	6		T418	2
values[50]	250	1			T128	1		T750	8		T418	4
values[51]	242	1			T128	2		T750	4		T418	2
values[52]	219	1			T128	1		T750	6		T418	1
values[53]	228	1			T128	1		T750	3		T418	2
values[54]	234	1			T128	1		T750	4		T418	6
values[55]	223	1			T128	2		T750	6		T418	5
values[56]	221	1			T128	4		T750	3		T418	8
values[57]	221	1			T128	7		T750	4		T418	5
values[58]	202	1			T128	1		T750	3		T418	12
values[59]	217	1			T750	8		T418	4		T878	7
values[60]	206	1			T750	8		T418	2		T878	3
values[61]	220	1			T750	5		T418	7		T878	7
values[62]	207	1			T750	26		T418	2		T878	7
values[63]	177	1			T750	17		T418	1		T878	5
values[64]	195	1			T750	7		T418	3		T878	9
values[65]	188	1			T750	6		T418	9		T878	6
values[66]	191	1			T750	12		T418	10		T878	9
values[67]	161	1			T750	6		T418	10		T878	10
values[68]	132	1			T750	4		T418	10		T878	2
values[69]	135	1			T750	3		T418	5		T878	8
values[70]	141	1			T750	6		T418	6		T878	9
values[71]	130	1			T750	9		T418	7		T878	5
values[72]	163	1			T750	6		T418	6		T878	3
values[73]	111	1			T750	3		T418	7		T888	3
values[74]	102	1			T750	3		T418	8		T888	5
values[75]	88	1			T750	1		T418	9		T888	4
values[76]	94	1			T418	6		T888	2		T484	1
values[77]	96	1			T418	11		T888	17		T484	2
values[78]	84	1			T418	3		T888	6		T484	1
values[79]	87	1			T418	3		T888	14		T484	1
values[80]	69	1			T418	5		T888	3		T484	1
values[81]	87	1			T418	3		T888	4		T484	1
values[82]	94	1			T418	9		T888	3		T484	1
values[83]	76	1			T418	8		T888	5		T484	1
values[84]	75	1			T418	7		T888	4		T484	1
values[85]	80	1			T418	10		T888	4		T484	1
values[86]	83	1			T418	8		T888	4		T484	1
values[87]	97	1			T418	4		T888	6		T484	1
values[88]	99	1			T418	4		T888	3		T484	1
values[89]	92	1			T418	6		T888	16		T484	1
values[90]	72	1			T418	1		T888	6		T484	1
values[91]	90	1			T418	4		T888	4		T484	1
values[92]	78	1			T418	6		T888	6		T484	1
values[93]	72	1			T418	1		T888	4		T484	1
values[94]	77	1			T418	1		T484	1		T890	3
values[95]	75	1			T484	1		T890	3		T891	3
values[96]	73	1			T484	1		T890	6		T891	3
values[97]	86	1			T484	1		T890	10		T891	8
values[98]	76	1			T484	1		T890	8		T891	6
values[99]	64	1			T484	1		T890	3		T891	2
values[100]	89	1			T484	1		T890	3		T891	4
values[101]	91	1			T484	1		T890	8		T891	9
values[102]	69	1			T484	1		T890	4		T891	2
values[103]	81	1			T484	1		T890	7		T891	1
values[104]	66	1			T484	1		T890	7		T891	3
values[105]	110	1			T484	1		T890	3		T891	4
values[106]	119	1			T484	1		T890	14		T891	5
values[107]	84	1			T484	1		T890	6		T891	7
values[108]	66	1			T484	1		T890	3		T891	5
values[109]	66	1			T484	1		T890	7		T891	4
values[110]	70	1			T484	1		T890	2		T891	8
values[111]	63	1			T484	1		T891	4		T892	4
values[112]	57	1			T484	1		T891	2		T892	2
values[113]	71	1			T484	1		T891	6		T892	1
values[114]	75	1			T484	4		T891	2		T892	1
values[115]	63	1			T484	1		T891	3		T893	2
values[116]	54	1			T484	3		T891	2		T893	1
values[117]	60	1			T484	1		T891	4		T893	2
values[118]	57	1			T484	1		T891	7		T893	1
values[119]	52	1			T484	1		T891	9		T893	2
values[120]	47	1			T484	1		T891	2		T893	1
values[121]	65	1			T484	1		T891	4		T893	1
values[122]	53	1			T484	1		T891	3		T893	3
values[123]	57	1			T484	2		T891	9		T893	1
values[124]	53	1			T484	2		T891	1		T893	3
values[125]	63	1			T484	2		T891	13		T893	1
values[126]	99	1			T484	2		T891	19		T893	4
values[127]	658	1			T484	27		T891	32		T893	38
values[128]	5691	1			T484	284		T891	12		T893	267