Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.spi_device_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	134728	1			T73	7		T74	76		T75	11
values[2]	9472	1			T74	5		T128	8		T537	174
values[3]	3457	1			T128	9		T537	84		T549	161
values[4]	2038	1			T128	5		T537	48		T549	128
values[5]	1391	1			T128	2		T537	37		T549	91
values[6]	920	1			T128	1		T537	16		T549	29
values[7]	684	1			T128	3		T537	8		T549	14
values[8]	534	1			T128	1		T537	5		T549	5
values[9]	417	1			T128	1		T537	3		T429	6
values[10]	370	1			T128	2		T429	10		T894	1
values[11]	339	1			T128	4		T429	3		T894	1
values[12]	302	1			T128	1		T429	4		T894	1
values[13]	340	1			T128	2		T429	8		T894	1
values[14]	346	1			T128	3		T429	4		T894	1
values[15]	293	1			T128	1		T429	11		T894	1
values[16]	345	1			T128	3		T429	5		T894	1
values[17]	377	1			T128	2		T429	5		T894	1
values[18]	325	1			T128	1		T429	9		T894	1
values[19]	312	1			T128	2		T429	8		T894	1
values[20]	289	1			T128	2		T429	7		T894	1
values[21]	304	1			T128	1		T429	4		T894	1
values[22]	294	1			T128	4		T429	4		T894	1
values[23]	309	1			T128	6		T429	4		T894	1
values[24]	336	1			T128	4		T429	2		T894	1
values[25]	259	1			T128	4		T429	1		T894	1
values[26]	302	1			T128	1		T429	2		T894	1
values[27]	292	1			T128	3		T429	4		T894	1
values[28]	325	1			T128	8		T429	2		T894	1
values[29]	309	1			T128	4		T429	3		T894	1
values[30]	312	1			T128	1		T429	1		T894	1
values[31]	327	1			T128	2		T429	2		T894	1
values[32]	301	1			T128	3		T429	3		T894	1
values[33]	290	1			T128	3		T429	3		T894	1
values[34]	298	1			T128	1		T429	2		T894	1
values[35]	304	1			T128	2		T429	4		T894	1
values[36]	315	1			T128	6		T429	1		T894	1
values[37]	294	1			T128	7		T429	1		T894	1
values[38]	268	1			T128	3		T429	1		T894	1
values[39]	271	1			T128	1		T429	3		T894	1
values[40]	294	1			T128	2		T429	2		T894	1
values[41]	261	1			T128	2		T429	3		T894	1
values[42]	293	1			T128	1		T429	1		T894	1
values[43]	328	1			T128	3		T429	1		T894	1
values[44]	258	1			T128	2		T429	7		T894	1
values[45]	304	1			T128	4		T429	9		T894	1
values[46]	253	1			T128	1		T429	7		T894	1
values[47]	253	1			T128	1		T429	2		T894	1
values[48]	286	1			T128	2		T894	1		T878	10
values[49]	250	1			T128	2		T894	1		T878	5
values[50]	241	1			T128	2		T894	1		T878	9
values[51]	217	1			T128	2		T894	1		T878	7
values[52]	219	1			T128	1		T894	1		T878	6
values[53]	254	1			T128	1		T894	1		T878	5
values[54]	245	1			T128	2		T894	1		T878	9
values[55]	229	1			T128	1		T894	1		T878	17
values[56]	240	1			T128	2		T894	1		T878	6
values[57]	237	1			T128	1		T894	1		T878	6
values[58]	237	1			T128	2		T894	1		T878	4
values[59]	214	1			T128	3		T894	1		T878	7
values[60]	210	1			T128	1		T894	1		T878	8
values[61]	188	1			T128	3		T894	1		T878	6
values[62]	169	1			T128	3		T894	1		T878	4
values[63]	161	1			T128	2		T894	1		T878	9
values[64]	149	1			T128	3		T894	1		T878	5
values[65]	148	1			T128	3		T894	1		T878	2
values[66]	143	1			T128	3		T894	1		T878	3
values[67]	149	1			T128	9		T894	1		T878	3
values[68]	169	1			T128	22		T894	1		T878	5
values[69]	160	1			T128	24		T894	1		T878	4
values[70]	130	1			T128	13		T894	1		T878	6
values[71]	153	1			T128	7		T894	1		T878	15
values[72]	140	1			T128	4		T894	1		T878	9
values[73]	106	1			T128	4		T894	1		T878	12
values[74]	127	1			T128	4		T894	1		T878	14
values[75]	116	1			T128	8		T894	1		T878	4
values[76]	89	1			T128	3		T894	1		T866	1
values[77]	82	1			T128	1		T894	1		T866	1
values[78]	87	1			T128	3		T894	1		T866	1
values[79]	82	1			T128	14		T894	1		T866	1
values[80]	93	1			T128	13		T894	1		T866	1
values[81]	102	1			T128	14		T894	1		T866	1
values[82]	82	1			T128	2		T894	1		T866	1
values[83]	87	1			T128	7		T894	1		T866	1
values[84]	77	1			T128	4		T894	1		T866	1
values[85]	57	1			T128	1		T894	1		T866	1
values[86]	58	1			T128	5		T894	1		T866	1
values[87]	66	1			T128	4		T894	1		T866	1
values[88]	70	1			T128	4		T894	1		T866	1
values[89]	64	1			T128	3		T894	1		T866	1
values[90]	75	1			T128	2		T894	1		T866	1
values[91]	84	1			T128	2		T894	1		T866	1
values[92]	69	1			T128	10		T894	1		T866	1
values[93]	77	1			T128	5		T894	1		T866	3
values[94]	81	1			T128	4		T894	1		T866	1
values[95]	64	1			T128	4		T894	1		T866	1
values[96]	83	1			T128	5		T894	1		T866	1
values[97]	79	1			T128	4		T894	2		T866	1
values[98]	86	1			T128	3		T894	1		T866	5
values[99]	73	1			T128	2		T894	1		T866	7
values[100]	92	1			T128	7		T894	1		T866	4
values[101]	72	1			T128	4		T894	1		T866	1
values[102]	84	1			T128	6		T894	1		T866	1
values[103]	95	1			T128	9		T894	1		T866	8
values[104]	81	1			T128	6		T894	1		T866	2
values[105]	78	1			T128	4		T894	1		T866	4
values[106]	91	1			T128	6		T894	1		T866	3
values[107]	79	1			T128	3		T894	1		T866	1
values[108]	86	1			T128	1		T894	1		T866	2
values[109]	86	1			T128	1		T894	1		T866	1
values[110]	82	1			T128	4		T894	1		T866	1
values[111]	82	1			T128	4		T894	1		T866	1
values[112]	76	1			T128	4		T894	1		T866	1
values[113]	95	1			T128	12		T894	1		T866	1
values[114]	86	1			T128	4		T894	1		T866	1
values[115]	74	1			T128	7		T894	1		T866	4
values[116]	72	1			T128	5		T894	1		T866	2
values[117]	66	1			T128	5		T894	1		T866	1
values[118]	102	1			T128	3		T894	1		T866	2
values[119]	109	1			T128	8		T894	1		T866	5
values[120]	74	1			T128	3		T894	1		T866	1
values[121]	79	1			T128	4		T894	1		T866	1
values[122]	55	1			T128	1		T894	2		T866	1
values[123]	62	1			T128	2		T894	1		T866	1
values[124]	65	1			T128	8		T894	1		T866	1
values[125]	99	1			T128	14		T894	1		T866	2
values[126]	131	1			T128	19		T894	1		T866	5
values[127]	822	1			T128	34		T894	31		T866	28
values[128]	6351	1			T128	14		T894	348		T866	245