Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_main__regs_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	152874	1			T73	4		T74	101		T75	4
values[2]	4232	1			T73	1		T74	7		T127	1
values[3]	2031	1			T74	1		T536	1		T549	41
values[4]	1548	1			T536	1		T549	65		T640	25
values[5]	1073	1			T536	1		T549	54		T640	20
values[6]	900	1			T536	1		T549	51		T640	5
values[7]	911	1			T536	1		T549	44		T640	7
values[8]	732	1			T536	1		T549	37		T640	4
values[9]	641	1			T536	1		T549	32		T640	9
values[10]	626	1			T536	1		T549	22		T640	23
values[11]	517	1			T536	1		T549	3		T640	16
values[12]	397	1			T536	1		T640	13		T860	35
values[13]	338	1			T536	1		T640	4		T860	39
values[14]	272	1			T536	1		T640	3		T860	33
values[15]	295	1			T536	1		T640	2		T860	23
values[16]	222	1			T536	1		T640	8		T860	1
values[17]	185	1			T536	1		T640	12		T429	1
values[18]	237	1			T536	1		T640	21		T429	2
values[19]	196	1			T536	1		T640	13		T429	3
values[20]	177	1			T536	1		T640	5		T429	2
values[21]	204	1			T536	1		T640	1		T429	6
values[22]	213	1			T536	1		T640	1		T429	3
values[23]	180	1			T536	1		T640	5		T429	2
values[24]	215	1			T536	1		T640	8		T429	2
values[25]	216	1			T536	1		T640	8		T429	3
values[26]	225	1			T536	1		T640	15		T429	3
values[27]	180	1			T536	1		T640	9		T429	1
values[28]	188	1			T536	1		T640	3		T429	2
values[29]	121	1			T536	1		T640	1		T429	2
values[30]	122	1			T536	1		T640	2		T429	2
values[31]	135	1			T536	1		T640	1		T429	4
values[32]	108	1			T536	1		T640	9		T429	3
values[33]	122	1			T536	1		T640	12		T429	1
values[34]	79	1			T536	1		T640	4		T429	2
values[35]	100	1			T536	1		T640	8		T429	3
values[36]	88	1			T536	1		T640	31		T429	1
values[37]	100	1			T536	1		T640	38		T429	3
values[38]	96	1			T536	1		T640	28		T429	2
values[39]	84	1			T536	1		T640	21		T429	4
values[40]	84	1			T536	1		T640	31		T429	3
values[41]	80	1			T536	1		T640	21		T429	5
values[42]	60	1			T536	1		T640	9		T429	3
values[43]	44	1			T536	1		T429	1		T408	2
values[44]	47	1			T536	1		T429	1		T408	2
values[45]	49	1			T536	1		T429	2		T408	3
values[46]	49	1			T536	1		T429	3		T408	3
values[47]	43	1			T536	1		T429	2		T408	1
values[48]	46	1			T536	1		T429	1		T408	4
values[49]	52	1			T536	1		T429	1		T408	5
values[50]	54	1			T536	1		T429	1		T408	5
values[51]	56	1			T536	1		T429	5		T408	9
values[52]	52	1			T536	1		T429	1		T408	8
values[53]	56	1			T536	1		T429	1		T408	5
values[54]	47	1			T536	1		T429	3		T408	3
values[55]	60	1			T536	1		T429	4		T408	5
values[56]	62	1			T536	1		T429	4		T408	3
values[57]	62	1			T536	1		T429	1		T408	6
values[58]	52	1			T536	1		T429	2		T408	7
values[59]	60	1			T536	1		T429	3		T408	9
values[60]	55	1			T536	1		T429	3		T408	3
values[61]	53	1			T536	1		T429	2		T408	2
values[62]	51	1			T536	1		T429	4		T408	1
values[63]	70	1			T536	1		T429	1		T408	2
values[64]	56	1			T536	1		T429	2		T408	8
values[65]	56	1			T536	1		T429	3		T408	6
values[66]	43	1			T536	1		T429	1		T408	2
values[67]	47	1			T536	1		T429	2		T408	3
values[68]	56	1			T536	1		T429	3		T408	3
values[69]	58	1			T536	1		T429	3		T408	3
values[70]	47	1			T536	1		T429	2		T408	2
values[71]	63	1			T536	1		T429	8		T408	2
values[72]	47	1			T536	1		T429	2		T408	2
values[73]	46	1			T536	1		T429	2		T408	1
values[74]	55	1			T536	1		T429	2		T408	3
values[75]	52	1			T536	1		T429	5		T408	3
values[76]	60	1			T536	1		T429	4		T408	3
values[77]	55	1			T536	1		T429	1		T408	4
values[78]	54	1			T536	1		T429	1		T408	1
values[79]	49	1			T536	1		T429	1		T408	1
values[80]	59	1			T536	1		T429	2		T408	2
values[81]	67	1			T536	1		T429	2		T408	4
values[82]	61	1			T536	1		T429	1		T408	2
values[83]	63	1			T536	1		T429	1		T408	4
values[84]	73	1			T536	1		T429	6		T408	4
values[85]	69	1			T536	1		T429	2		T408	5
values[86]	91	1			T536	1		T429	10		T408	2
values[87]	84	1			T536	1		T429	5		T408	2
values[88]	80	1			T536	1		T429	5		T408	8
values[89]	73	1			T536	1		T429	2		T408	4
values[90]	60	1			T536	1		T429	5		T408	1
values[91]	83	1			T536	1		T429	1		T408	2
values[92]	91	1			T536	1		T429	2		T408	2
values[93]	89	1			T536	1		T429	3		T408	6
values[94]	92	1			T536	1		T429	6		T408	1
values[95]	71	1			T536	1		T429	1		T408	2
values[96]	73	1			T536	1		T429	2		T408	2
values[97]	86	1			T536	1		T429	4		T408	1
values[98]	64	1			T536	1		T429	4		T408	1
values[99]	84	1			T536	2		T429	5		T408	3
values[100]	76	1			T536	3		T429	4		T408	2
values[101]	66	1			T536	5		T429	3		T408	2
values[102]	67	1			T536	2		T429	2		T408	3
values[103]	82	1			T536	2		T429	4		T408	3
values[104]	85	1			T536	2		T429	4		T408	4
values[105]	83	1			T536	3		T429	10		T408	1
values[106]	78	1			T536	3		T429	4		T408	5
values[107]	86	1			T536	3		T429	2		T408	6
values[108]	74	1			T536	1		T429	2		T408	4
values[109]	94	1			T536	2		T429	7		T408	5
values[110]	86	1			T536	3		T429	1		T408	3
values[111]	77	1			T536	2		T429	4		T408	5
values[112]	88	1			T536	2		T429	4		T408	4
values[113]	79	1			T536	2		T429	7		T408	1
values[114]	84	1			T536	6		T429	6		T408	2
values[115]	83	1			T536	1		T429	2		T408	8
values[116]	93	1			T536	2		T429	6		T408	8
values[117]	96	1			T536	2		T429	4		T408	7
values[118]	125	1			T536	1		T429	10		T408	4
values[119]	99	1			T536	2		T429	3		T408	9
values[120]	94	1			T536	1		T429	6		T408	7
values[121]	94	1			T536	1		T429	4		T408	5
values[122]	124	1			T536	1		T429	13		T408	6
values[123]	130	1			T536	2		T429	16		T408	4
values[124]	159	1			T536	5		T429	2		T408	15
values[125]	299	1			T536	3		T429	22		T408	48
values[126]	573	1			T536	11		T429	44		T408	59
values[127]	2141	1			T536	105		T429	22		T408	30
values[128]	3573	1			T536	240		T429	3		T408	2