Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_ret_aon__ram_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	129937	1			T73	2		T74	70		T75	13
values[2]	8747	1			T74	2		T128	1		T536	1
values[3]	2974	1			T536	1		T419	21		T541	1
values[4]	1638	1			T536	1		T541	1		T543	25
values[5]	1005	1			T536	1		T541	1		T543	15
values[6]	719	1			T536	1		T541	1		T543	3
values[7]	481	1			T536	1		T541	1		T542	3
values[8]	435	1			T536	1		T541	1		T542	10
values[9]	278	1			T536	1		T541	1		T542	10
values[10]	259	1			T536	1		T541	1		T542	3
values[11]	251	1			T536	1		T541	1		T542	3
values[12]	233	1			T536	1		T541	1		T542	14
values[13]	233	1			T536	1		T541	1		T542	4
values[14]	208	1			T536	1		T541	1		T542	4
values[15]	231	1			T536	1		T541	1		T542	4
values[16]	220	1			T536	1		T541	1		T542	11
values[17]	204	1			T536	1		T541	1		T542	3
values[18]	232	1			T536	1		T541	1		T542	25
values[19]	203	1			T536	1		T541	1		T542	7
values[20]	186	1			T536	1		T541	1		T542	4
values[21]	176	1			T536	1		T541	1		T542	4
values[22]	189	1			T536	1		T541	1		T542	3
values[23]	217	1			T536	1		T541	1		T542	11
values[24]	166	1			T536	1		T541	1		T542	8
values[25]	177	1			T536	1		T541	2		T542	5
values[26]	187	1			T536	1		T541	1		T542	5
values[27]	207	1			T536	1		T541	1		T542	12
values[28]	198	1			T536	1		T541	1		T542	14
values[29]	146	1			T536	1		T541	1		T542	7
values[30]	174	1			T536	1		T541	1		T542	15
values[31]	177	1			T536	1		T541	1		T542	2
values[32]	183	1			T536	1		T541	1		T542	4
values[33]	197	1			T536	1		T541	1		T542	8
values[34]	153	1			T536	1		T541	1		T542	10
values[35]	166	1			T536	1		T541	1		T542	8
values[36]	161	1			T536	1		T541	1		T542	12
values[37]	201	1			T536	1		T541	1		T542	11
values[38]	191	1			T536	1		T541	1		T542	3
values[39]	175	1			T536	1		T541	1		T542	5
values[40]	184	1			T536	1		T541	1		T542	8
values[41]	176	1			T536	1		T541	1		T542	5
values[42]	166	1			T536	1		T541	1		T542	7
values[43]	170	1			T536	1		T541	1		T542	5
values[44]	167	1			T536	1		T541	1		T542	6
values[45]	155	1			T536	1		T541	1		T542	4
values[46]	155	1			T536	1		T541	1		T542	7
values[47]	167	1			T536	1		T541	1		T542	3
values[48]	128	1			T536	1		T541	1		T542	3
values[49]	145	1			T536	1		T541	1		T542	3
values[50]	159	1			T536	1		T541	1		T542	6
values[51]	174	1			T536	1		T541	1		T542	9
values[52]	128	1			T536	1		T541	1		T542	7
values[53]	156	1			T536	1		T541	1		T542	15
values[54]	199	1			T536	1		T541	1		T542	21
values[55]	167	1			T536	1		T541	1		T542	8
values[56]	152	1			T536	1		T541	1		T542	17
values[57]	155	1			T536	1		T541	1		T542	7
values[58]	164	1			T536	1		T541	1		T542	5
values[59]	175	1			T536	1		T541	2		T542	3
values[60]	176	1			T536	1		T541	1		T542	5
values[61]	153	1			T536	1		T541	1		T542	8
values[62]	155	1			T536	1		T541	1		T542	7
values[63]	152	1			T536	1		T541	1		T860	2
values[64]	174	1			T536	1		T541	1		T860	2
values[65]	163	1			T536	1		T541	1		T860	2
values[66]	180	1			T536	1		T541	1		T860	3
values[67]	144	1			T536	1		T541	1		T860	2
values[68]	159	1			T536	1		T541	1		T860	1
values[69]	163	1			T536	1		T541	1		T860	4
values[70]	143	1			T536	1		T541	1		T860	3
values[71]	138	1			T536	1		T541	1		T860	2
values[72]	146	1			T536	1		T541	1		T860	4
values[73]	116	1			T536	1		T541	1		T860	1
values[74]	128	1			T536	1		T541	1		T860	5
values[75]	126	1			T536	1		T541	1		T860	11
values[76]	113	1			T536	1		T541	1		T860	16
values[77]	123	1			T536	1		T541	1		T860	11
values[78]	113	1			T536	1		T541	1		T860	9
values[79]	128	1			T536	1		T541	1		T860	10
values[80]	154	1			T536	1		T541	1		T860	11
values[81]	106	1			T536	1		T541	2		T860	12
values[82]	91	1			T536	1		T541	9		T860	4
values[83]	113	1			T536	1		T541	7		T860	5
values[84]	129	1			T536	1		T541	2		T860	8
values[85]	141	1			T536	1		T541	4		T860	7
values[86]	145	1			T536	1		T541	2		T860	8
values[87]	150	1			T536	1		T541	2		T860	10
values[88]	115	1			T536	1		T541	1		T860	6
values[89]	101	1			T536	1		T541	4		T860	6
values[90]	97	1			T536	1		T541	3		T860	3
values[91]	127	1			T536	1		T541	5		T860	6
values[92]	92	1			T536	1		T541	1		T860	8
values[93]	111	1			T536	1		T541	1		T860	5
values[94]	65	1			T536	1		T541	3		T860	1
values[95]	74	1			T536	1		T541	2		T860	3
values[96]	89	1			T536	1		T541	1		T860	3
values[97]	107	1			T536	1		T541	6		T860	8
values[98]	88	1			T536	1		T541	2		T860	3
values[99]	74	1			T536	1		T541	4		T860	1
values[100]	76	1			T536	1		T541	1		T860	4
values[101]	80	1			T536	2		T541	6		T860	8
values[102]	79	1			T536	1		T541	2		T860	6
values[103]	87	1			T536	4		T541	2		T860	5
values[104]	74	1			T536	3		T541	1		T860	4
values[105]	73	1			T536	7		T541	1		T860	1
values[106]	78	1			T536	4		T541	2		T860	5
values[107]	67	1			T536	3		T541	2		T860	1
values[108]	63	1			T536	4		T541	1		T860	3
values[109]	80	1			T536	7		T541	1		T860	4
values[110]	58	1			T536	1		T541	1		T860	1
values[111]	74	1			T536	1		T541	2		T860	3
values[112]	103	1			T536	1		T541	3		T860	4
values[113]	72	1			T536	1		T541	1		T860	3
values[114]	74	1			T536	3		T541	4		T860	2
values[115]	76	1			T536	1		T541	1		T860	3
values[116]	64	1			T536	1		T541	1		T860	3
values[117]	62	1			T536	1		T541	1		T860	5
values[118]	65	1			T536	2		T541	2		T860	3
values[119]	81	1			T536	2		T541	1		T860	6
values[120]	84	1			T536	5		T541	1		T860	7
values[121]	91	1			T536	1		T541	3		T860	3
values[122]	75	1			T536	2		T541	7		T860	3
values[123]	67	1			T536	1		T541	3		T860	6
values[124]	83	1			T536	2		T541	3		T860	3
values[125]	81	1			T536	2		T541	2		T860	3
values[126]	164	1			T536	2		T541	4		T860	7
values[127]	917	1			T536	42		T541	20		T860	18
values[128]	6407	1			T536	314		T541	258		T860	13