Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	489	1			T127	1		T128	2		T537	4
all_values[1]	477	1			T127	5		T537	2		T419	1
all_values[2]	474	1			T128	3		T537	2		T430	1
all_values[3]	464	1			T128	1		T536	2		T537	1
all_values[4]	471	1			T127	2		T537	2		T430	1
all_values[5]	480	1			T127	1		T128	2		T537	3
all_values[6]	494	1			T127	1		T537	1		T419	1
all_values[7]	474	1			T127	3		T128	3		T537	1
all_values[8]	494	1			T128	1		T537	3		T543	3
all_values[9]	500	1			T127	2		T537	1		T543	2
all_values[10]	509	1			T128	3		T537	1		T430	1
all_values[11]	495	1			T127	2		T128	1		T537	1
all_values[12]	504	1			T127	2		T128	2		T536	2
all_values[13]	507	1			T127	3		T128	2		T543	2
all_values[14]	468	1			T127	1		T537	1		T430	1
all_values[15]	457	1			T127	1		T128	1		T536	1
all_values[16]	399	1			T543	2		T549	1		T750	1
all_values[17]	505	1			T127	2		T128	2		T537	3
all_values[18]	458	1			T127	1		T128	1		T537	3
all_values[19]	495	1			T127	2		T128	3		T537	2
all_values[20]	460	1			T128	2		T537	2		T430	1
all_values[21]	459	1			T128	3		T536	1		T537	2
all_values[22]	468	1			T127	1		T128	2		T537	2
all_values[23]	472	1			T537	4		T430	3		T543	2
all_values[24]	457	1			T127	1		T537	1		T430	1
all_values[25]	436	1			T128	3		T537	2		T419	2
all_values[26]	487	1			T127	3		T128	1		T537	1
all_values[27]	471	1			T127	1		T128	2		T536	1
all_values[28]	486	1			T128	2		T537	3		T541	1
all_values[29]	500	1			T128	2		T537	2		T541	1
all_values[30]	496	1			T537	5		T430	1		T543	6
all_values[31]	513	1			T127	1		T128	1		T537	4
all_values[32]	529	1			T127	1		T128	1		T536	2
all_values[33]	495	1			T127	1		T128	3		T537	3
all_values[34]	468	1			T127	2		T128	2		T537	2
all_values[35]	454	1			T127	2		T128	2		T537	3
all_values[36]	440	1			T127	2		T536	1		T537	5
all_values[37]	485	1			T127	2		T128	1		T537	4
all_values[38]	477	1			T128	3		T537	2		T430	2
all_values[39]	467	1			T128	1		T537	1		T419	1
all_values[40]	493	1			T127	2		T128	3		T536	1
all_values[41]	494	1			T128	5		T536	1		T537	3
all_values[42]	444	1			T128	1		T537	1		T430	2
all_values[43]	465	1			T127	1		T128	2		T536	1
all_values[44]	511	1			T127	2		T128	5		T537	4
all_values[45]	440	1			T127	4		T536	1		T537	1
all_values[46]	485	1			T127	2		T128	3		T537	2
all_values[47]	491	1			T127	2		T128	1		T537	2
all_values[48]	527	1			T128	3		T537	1		T430	3
all_values[49]	453	1			T127	1		T128	1		T537	4