Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}
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Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv



Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 64 0 64 100.00


Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_dev 64 0 64 100.00 100 1 1 0


Summary for Variable cp_dev

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 64 0 64 100.00


User Defined Bins for cp_dev

Excluded/Illegal bins
NAMECOUNTSTATUS
bin_others 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 3378 1 T127 26 T128 16 T537 37
all_values[1] 3595 1 T127 31 T128 12 T537 37
all_values[2] 3549 1 T127 25 T128 13 T537 30
all_values[3] 3561 1 T127 24 T128 7 T537 29
all_values[4] 3524 1 T127 21 T128 15 T537 33
all_values[5] 3502 1 T127 31 T128 14 T537 22
all_values[6] 3528 1 T127 20 T128 15 T537 23
all_values[7] 3413 1 T127 28 T128 10 T537 24
all_values[8] 3466 1 T127 22 T128 17 T537 29
all_values[9] 3551 1 T127 31 T128 18 T537 32
all_values[10] 3456 1 T127 18 T128 12 T537 18
all_values[11] 3479 1 T127 28 T128 15 T537 37
all_values[12] 3530 1 T127 20 T128 12 T537 27
all_values[13] 3529 1 T127 23 T128 9 T537 27
all_values[14] 3570 1 T127 32 T128 19 T537 29
all_values[15] 3510 1 T127 26 T128 6 T537 40
all_values[16] 3554 1 T127 44 T128 10 T537 24
all_values[17] 3537 1 T127 28 T128 18 T537 34
all_values[18] 3508 1 T127 33 T128 14 T537 28
all_values[19] 3470 1 T127 23 T128 15 T537 23
all_values[20] 3428 1 T127 16 T128 12 T537 31
all_values[21] 3583 1 T127 18 T128 20 T537 26
all_values[22] 3497 1 T127 26 T128 16 T537 31
all_values[23] 3609 1 T127 18 T128 12 T537 27
all_values[24] 3542 1 T127 24 T128 17 T537 35
all_values[25] 3526 1 T127 23 T128 12 T537 24
all_values[26] 3546 1 T127 20 T128 12 T537 28
all_values[27] 3594 1 T127 31 T128 6 T537 34
all_values[28] 3586 1 T127 22 T128 14 T537 37
all_values[29] 3538 1 T127 25 T128 9 T537 26
all_values[30] 3500 1 T127 28 T128 11 T537 29
all_values[31] 3604 1 T127 22 T128 16 T537 33
all_values[32] 3524 1 T127 25 T128 18 T537 21
all_values[33] 3459 1 T127 30 T128 23 T537 34
all_values[34] 3531 1 T127 26 T128 14 T537 24
all_values[35] 3495 1 T127 32 T128 18 T537 29
all_values[36] 3506 1 T127 23 T128 20 T537 19
all_values[37] 3400 1 T127 20 T128 12 T537 21
all_values[38] 3529 1 T127 18 T128 10 T537 33
all_values[39] 3491 1 T127 23 T128 10 T537 28
all_values[40] 3520 1 T127 30 T128 14 T537 28
all_values[41] 3501 1 T127 28 T128 16 T537 30
all_values[42] 3534 1 T127 29 T128 18 T537 25
all_values[43] 3500 1 T127 29 T128 10 T537 30
all_values[44] 3613 1 T127 27 T128 9 T537 30
all_values[45] 3598 1 T127 27 T128 14 T537 29
all_values[46] 3538 1 T127 26 T128 16 T537 31
all_values[47] 3551 1 T127 25 T128 15 T537 37
all_values[48] 3597 1 T127 26 T128 15 T537 38
all_values[49] 3549 1 T127 24 T128 10 T537 31
all_values[50] 3488 1 T127 21 T128 19 T537 37
all_values[51] 3521 1 T127 28 T128 16 T537 34
all_values[52] 3546 1 T127 21 T128 14 T537 38
all_values[53] 3481 1 T127 33 T128 11 T537 26
all_values[54] 3497 1 T127 29 T128 14 T537 33
all_values[55] 3561 1 T127 13 T128 12 T537 23
all_values[56] 3551 1 T127 28 T128 13 T537 39
all_values[57] 3490 1 T127 24 T128 11 T537 36
all_values[58] 3406 1 T127 33 T128 14 T537 28
all_values[59] 3525 1 T127 24 T128 12 T537 32
all_values[60] 3414 1 T127 23 T128 7 T537 24
all_values[61] 3430 1 T127 22 T128 10 T537 22
all_values[62] 3536 1 T127 27 T128 15 T537 36
all_values[63] 3456 1 T127 21 T128 13 T537 26

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