CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 369429 | 1 | T80 | 2 | T82 | 203 | T86 | 551 | ||||
rising | 369544 | 1 | T80 | 2 | T82 | 203 | T86 | 550 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 1043031 | 1 | T80 | 4 | T82 | 906 | T86 | 2314 | ||||
auto[1] | 9289105 | 1 | T80 | 5518 | T81 | 300 | T82 | 898 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 327284 | 1 | T80 | 1 | T82 | 214 | T86 | 557 | ||||
rising | 327384 | 1 | T80 | 1 | T82 | 214 | T86 | 558 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 1163638 | 1 | T80 | 2 | T82 | 864 | T86 | 2386 | ||||
auto[1] | 9993543 | 1 | T80 | 5520 | T81 | 370 | T82 | 868 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 648188 | 1 | T80 | 4 | T82 | 422 | T86 | 1010 | ||||
rising | 648282 | 1 | T80 | 4 | T82 | 421 | T86 | 1010 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 1051003 | 1 | T80 | 4 | T82 | 840 | T86 | 2200 | ||||
auto[1] | 9363022 | 1 | T80 | 5530 | T81 | 218 | T82 | 904 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 8533 | 1 | T80 | 1 | T86 | 2 | T472 | 5 | ||||
rising | 8584 | 1 | T80 | 1 | T86 | 2 | T472 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 169164 | 1 | T80 | 111 | T81 | 5 | T82 | 17 | ||||
auto[1] | 17819 | 1 | T80 | 1 | T86 | 2 | T472 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 4827 | 1 | T82 | 1 | T86 | 2 | T472 | 5 | ||||
rising | 4860 | 1 | T82 | 1 | T86 | 2 | T472 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 167996 | 1 | T80 | 112 | T81 | 7 | T82 | 18 | ||||
auto[1] | 7550 | 1 | T82 | 1 | T86 | 2 | T472 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 3647 | 1 | T80 | 1 | T86 | 2 | T252 | 1 | ||||
rising | 3668 | 1 | T80 | 1 | T86 | 2 | T252 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 183521 | 1 | T80 | 124 | T81 | 2 | T82 | 20 | ||||
auto[1] | 3956 | 1 | T80 | 1 | T86 | 2 | T252 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 5644 | 1 | T86 | 1 | T253 | 1 | T472 | 2 | ||||
rising | 5686 | 1 | T86 | 1 | T253 | 1 | T472 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 152965 | 1 | T80 | 127 | T81 | 6 | T82 | 16 | ||||
auto[1] | 15346 | 1 | T86 | 1 | T253 | 1 | T472 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 3876 | 1 | T86 | 1 | T472 | 6 | T559 | 52 | ||||
rising | 3902 | 1 | T86 | 1 | T472 | 6 | T559 | 52 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 173167 | 1 | T80 | 91 | T81 | 6 | T82 | 15 | ||||
auto[1] | 4453 | 1 | T86 | 1 | T472 | 6 | T559 | 60 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 6643 | 1 | T80 | 2 | T86 | 1 | T472 | 6 | ||||
rising | 6681 | 1 | T80 | 2 | T86 | 1 | T472 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 165542 | 1 | T80 | 100 | T81 | 1 | T82 | 17 | ||||
auto[1] | 13637 | 1 | T80 | 2 | T86 | 1 | T472 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 5554 | 1 | T82 | 1 | T472 | 5 | T559 | 50 | ||||
rising | 5591 | 1 | T82 | 1 | T472 | 5 | T559 | 50 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 170486 | 1 | T80 | 130 | T81 | 4 | T82 | 25 | ||||
auto[1] | 11863 | 1 | T82 | 1 | T472 | 6 | T559 | 54 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 6641 | 1 | T82 | 1 | T472 | 2 | T473 | 2 | ||||
rising | 6674 | 1 | T82 | 1 | T472 | 2 | T473 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 177466 | 1 | T80 | 99 | T81 | 9 | T82 | 19 | ||||
auto[1] | 13844 | 1 | T82 | 1 | T472 | 2 | T473 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 5531 | 1 | T86 | 3 | T472 | 8 | T473 | 1 | ||||
rising | 5570 | 1 | T86 | 3 | T472 | 8 | T473 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 176973 | 1 | T80 | 99 | T81 | 3 | T82 | 16 | ||||
auto[1] | 10509 | 1 | T86 | 4 | T472 | 8 | T473 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 5965 | 1 | T472 | 4 | T473 | 1 | T562 | 2 | ||||
rising | 6008 | 1 | T472 | 4 | T473 | 1 | T562 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 184143 | 1 | T80 | 117 | T81 | 8 | T82 | 13 | ||||
auto[1] | 9472 | 1 | T472 | 4 | T473 | 1 | T562 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 5204 | 1 | T82 | 1 | T86 | 1 | T472 | 8 | ||||
rising | 5240 | 1 | T82 | 1 | T86 | 1 | T472 | 8 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 183658 | 1 | T80 | 102 | T81 | 2 | T82 | 20 | ||||
auto[1] | 6745 | 1 | T82 | 1 | T86 | 1 | T472 | 9 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 14838 | 1 | T82 | 4 | T86 | 6 | T472 | 35 | ||||
rising | 14873 | 1 | T82 | 4 | T86 | 6 | T472 | 35 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 1416599 | 1 | T80 | 770 | T81 | 47 | T82 | 127 | ||||
auto[1] | 15478 | 1 | T82 | 5 | T86 | 7 | T472 | 36 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 6484 | 1 | T472 | 5 | T473 | 3 | T562 | 1 | ||||
rising | 6528 | 1 | T472 | 5 | T473 | 3 | T562 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 190246 | 1 | T80 | 117 | T81 | 4 | T82 | 15 | ||||
auto[1] | 13727 | 1 | T472 | 5 | T473 | 3 | T562 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 7440 | 1 | T82 | 1 | T86 | 2 | T253 | 1 | ||||
rising | 7487 | 1 | T82 | 1 | T86 | 2 | T253 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 160397 | 1 | T80 | 120 | T81 | 5 | T82 | 14 | ||||
auto[1] | 21301 | 1 | T82 | 2 | T86 | 2 | T253 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 2459 | 1 | T82 | 1 | T472 | 4 | T473 | 1 | ||||
rising | 2489 | 1 | T82 | 1 | T472 | 4 | T473 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 188365 | 1 | T80 | 98 | T81 | 13 | T82 | 16 | ||||
auto[1] | 2591 | 1 | T82 | 1 | T472 | 4 | T473 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 7138 | 1 | T80 | 1 | T82 | 1 | T86 | 3 | ||||
rising | 7177 | 1 | T80 | 1 | T82 | 1 | T86 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 167590 | 1 | T80 | 120 | T81 | 7 | T82 | 21 | ||||
auto[1] | 14268 | 1 | T80 | 1 | T82 | 1 | T86 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 7614 | 1 | T86 | 1 | T472 | 1 | T559 | 27 | ||||
rising | 7659 | 1 | T86 | 1 | T472 | 1 | T559 | 27 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 170930 | 1 | T80 | 107 | T81 | 9 | T82 | 12 | ||||
auto[1] | 15605 | 1 | T86 | 1 | T472 | 1 | T559 | 28 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 6358 | 1 | T80 | 1 | T86 | 1 | T472 | 1 | ||||
rising | 6396 | 1 | T80 | 1 | T86 | 1 | T472 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 164124 | 1 | T80 | 86 | T81 | 7 | T82 | 14 | ||||
auto[1] | 12305 | 1 | T80 | 1 | T86 | 1 | T472 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 5491 | 1 | T559 | 43 | T473 | 1 | T562 | 3 | ||||
rising | 5528 | 1 | T252 | 1 | T559 | 43 | T473 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 178684 | 1 | T80 | 99 | T81 | 6 | T82 | 14 | ||||
auto[1] | 8800 | 1 | T252 | 1 | T559 | 49 | T473 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 3206 | 1 | T86 | 1 | T472 | 4 | T473 | 1 | ||||
rising | 3233 | 1 | T86 | 1 | T472 | 4 | T473 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 192216 | 1 | T80 | 105 | T81 | 5 | T82 | 20 | ||||
auto[1] | 3446 | 1 | T86 | 1 | T472 | 4 | T473 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 6878 | 1 | T80 | 1 | T82 | 1 | T86 | 2 | ||||
rising | 6916 | 1 | T80 | 1 | T82 | 1 | T86 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 169550 | 1 | T80 | 123 | T81 | 3 | T82 | 19 | ||||
auto[1] | 10538 | 1 | T80 | 1 | T82 | 1 | T86 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 39625 | 1 | T586 | 1191 | T587 | 918 | T580 | 2812 | ||||
rising | 39624 | 1 | T586 | 1191 | T587 | 918 | T580 | 2812 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 86453 | 1 | T586 | 2636 | T587 | 2124 | T580 | 5808 | ||||
auto[1] | 76771 | 1 | T586 | 2299 | T587 | 1713 | T580 | 5477 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 22952 | 1 | T586 | 749 | T587 | 577 | T580 | 1511 | ||||
rising | 22948 | 1 | T586 | 748 | T587 | 577 | T580 | 1511 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 134672 | 1 | T586 | 3998 | T587 | 3061 | T580 | 9485 | ||||
auto[1] | 28552 | 1 | T586 | 937 | T587 | 776 | T580 | 1800 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 22952 | 1 | T586 | 749 | T587 | 577 | T580 | 1511 | ||||
rising | 22948 | 1 | T586 | 748 | T587 | 577 | T580 | 1511 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 134672 | 1 | T586 | 3998 | T587 | 3061 | T580 | 9485 | ||||
auto[1] | 28552 | 1 | T586 | 937 | T587 | 776 | T580 | 1800 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 4105 | 1 | T586 | 171 | T587 | 148 | T580 | 132 | ||||
rising | 4100 | 1 | T586 | 170 | T587 | 148 | T580 | 132 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 157335 | 1 | T586 | 4687 | T587 | 3585 | T580 | 11129 | ||||
auto[1] | 5889 | 1 | T586 | 248 | T587 | 252 | T580 | 156 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 97782 | 1 | T586 | 1 | T147 | 267 | T587 | 1 | ||||
rising | 97805 | 1 | T586 | 1 | T147 | 268 | T587 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 33687681 | 1 | T4 | 5652 | T5 | 7398 | T6 | 19209 | ||||
auto[1] | 584032 | 1 | T586 | 1 | T147 | 331 | T587 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 40298 | 1 | T586 | 1241 | T587 | 929 | T580 | 2821 | ||||
rising | 40297 | 1 | T586 | 1242 | T587 | 929 | T580 | 2821 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 86390 | 1 | T586 | 2633 | T587 | 2090 | T580 | 5732 | ||||
auto[1] | 76834 | 1 | T586 | 2302 | T587 | 1747 | T580 | 5553 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 34449 | 1 | T586 | 1064 | T587 | 803 | T580 | 2370 | ||||
rising | 34453 | 1 | T586 | 1064 | T587 | 803 | T580 | 2370 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 113917 | 1 | T586 | 3415 | T587 | 2661 | T580 | 7891 | ||||
auto[1] | 49307 | 1 | T586 | 1520 | T587 | 1176 | T580 | 3394 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 2259 | 1 | T472 | 3 | T473 | 2 | T562 | 1 | ||||
rising | 2280 | 1 | T472 | 3 | T473 | 2 | T562 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 184615 | 1 | T80 | 110 | T81 | 7 | T82 | 11 | ||||
auto[1] | 2387 | 1 | T472 | 3 | T473 | 3 | T562 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 3227 | 1 | T80 | 1 | T86 | 1 | T472 | 5 | ||||
rising | 3258 | 1 | T80 | 1 | T86 | 1 | T472 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 182194 | 1 | T80 | 105 | T81 | 6 | T82 | 19 | ||||
auto[1] | 3449 | 1 | T80 | 1 | T86 | 1 | T472 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 5803 | 1 | T86 | 1 | T472 | 1 | T473 | 4 | ||||
rising | 5844 | 1 | T86 | 1 | T472 | 1 | T473 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 164707 | 1 | T80 | 116 | T81 | 6 | T82 | 17 | ||||
auto[1] | 19750 | 1 | T86 | 1 | T472 | 1 | T473 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 6318 | 1 | T472 | 7 | T559 | 26 | T562 | 1 | ||||
rising | 6368 | 1 | T472 | 7 | T559 | 26 | T562 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 160270 | 1 | T80 | 131 | T81 | 2 | T82 | 20 | ||||
auto[1] | 16519 | 1 | T472 | 9 | T559 | 27 | T562 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 2925 | 1 | T80 | 1 | T86 | 3 | T472 | 1 | ||||
rising | 2951 | 1 | T80 | 1 | T86 | 3 | T472 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 182309 | 1 | T80 | 113 | T81 | 2 | T82 | 19 | ||||
auto[1] | 3122 | 1 | T80 | 1 | T86 | 3 | T472 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 7429 | 1 | T472 | 2 | T473 | 1 | T565 | 1 | ||||
rising | 7464 | 1 | T472 | 2 | T473 | 1 | T565 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 167001 | 1 | T80 | 113 | T81 | 3 | T82 | 21 | ||||
auto[1] | 14045 | 1 | T472 | 2 | T473 | 1 | T565 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 7143 | 1 | T472 | 1 | T473 | 2 | T565 | 1 | ||||
rising | 7181 | 1 | T472 | 1 | T473 | 2 | T565 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 171838 | 1 | T80 | 111 | T81 | 9 | T82 | 21 | ||||
auto[1] | 14122 | 1 | T472 | 1 | T473 | 2 | T565 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 5464 | 1 | T86 | 3 | T472 | 2 | T473 | 1 | ||||
rising | 5499 | 1 | T86 | 3 | T472 | 2 | T473 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 181945 | 1 | T80 | 130 | T81 | 7 | T82 | 10 | ||||
auto[1] | 11013 | 1 | T86 | 3 | T472 | 2 | T473 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 22243 | 1 | T80 | 13 | T82 | 4 | T86 | 6 | ||||
rising | 22270 | 1 | T80 | 13 | T82 | 4 | T86 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 1426776 | 1 | T80 | 828 | T81 | 51 | T82 | 128 | ||||
auto[1] | 23285 | 1 | T80 | 14 | T82 | 4 | T86 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 7369 | 1 | T472 | 1 | T562 | 2 | T563 | 1 | ||||
rising | 7416 | 1 | T472 | 1 | T562 | 2 | T563 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 170015 | 1 | T80 | 112 | T81 | 4 | T82 | 17 | ||||
auto[1] | 15524 | 1 | T472 | 1 | T562 | 2 | T563 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 5314 | 1 | T472 | 2 | T559 | 95 | T473 | 1 | ||||
rising | 5336 | 1 | T472 | 2 | T559 | 95 | T473 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 182799 | 1 | T80 | 96 | T82 | 19 | T86 | 39 | ||||
auto[1] | 8259 | 1 | T472 | 2 | T559 | 151 | T473 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 187769 | 1 | T82 | 70 | T86 | 218 | T253 | 50 | ||||
rising | 187773 | 1 | T82 | 70 | T86 | 218 | T253 | 50 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 1685513 | 1 | T82 | 783 | T86 | 1956 | T253 | 436 | ||||
auto[1] | 211286 | 1 | T82 | 76 | T86 | 242 | T253 | 55 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 465936 | 1 | T82 | 200 | T86 | 534 | T253 | 117 | ||||
rising | 465945 | 1 | T82 | 200 | T86 | 535 | T253 | 117 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 843018 | 1 | T82 | 375 | T86 | 975 | T253 | 232 | ||||
auto[1] | 1053781 | 1 | T82 | 484 | T86 | 1223 | T253 | 259 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 465936 | 1 | T82 | 200 | T86 | 534 | T253 | 117 | ||||
rising | 465945 | 1 | T82 | 200 | T86 | 535 | T253 | 117 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 843018 | 1 | T82 | 375 | T86 | 975 | T253 | 232 | ||||
auto[1] | 1053781 | 1 | T82 | 484 | T86 | 1223 | T253 | 259 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |