Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.06	95.60	94.23	95.49		95.03	96.47	99.51

Total tests in report: 2881

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
39.58	39.58	44.82	44.82	43.08	43.08	31.56	31.56			57.97	57.97	59.62	59.62	0.43	0.43	/workspace/coverage/default/93.chip_sw_all_escalation_resets.1132204894
48.81	9.22	53.16	8.34	53.07	9.98	34.75	3.19			66.28	8.31	84.79	25.17	0.79	0.35	/workspace/coverage/default/0.chip_jtag_csr_rw.4195996628
54.11	5.30	63.57	10.41	60.20	7.13	38.67	3.92			75.89	9.61	85.14	0.35	1.17	0.39	/workspace/coverage/default/1.chip_jtag_csr_rw.358481714
58.87	4.77	70.34	6.77	62.80	2.60	43.11	4.44			76.11	0.22	85.14	0.00	15.74	14.57	/workspace/coverage/cover_reg_top/65.xbar_stress_all.515999151
62.89	4.01	70.34	0.00	62.84	0.04	43.11	0.00			76.13	0.02	85.14	0.00	39.77	24.03	/workspace/coverage/cover_reg_top/55.xbar_access_same_device_slow_rsp.3922055345
66.16	3.27	76.24	5.90	67.10	4.26	47.05	3.94			78.15	2.02	88.64	3.50	39.77	0.00	/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.1784377709
69.37	3.21	76.25	0.01	67.12	0.02	66.23	19.18			78.16	0.02	88.64	0.00	39.82	0.05	/workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.1757353795
71.89	2.52	76.36	0.11	68.93	1.81	66.97	0.73			78.23	0.06	88.64	0.00	52.23	12.41	/workspace/coverage/cover_reg_top/96.xbar_stress_all_with_error.3635044394
74.22	2.33	78.56	2.21	74.84	5.91	67.49	0.52			82.67	4.45	88.64	0.00	53.14	0.92	/workspace/coverage/cover_reg_top/3.chip_same_csr_outstanding.814946645
76.38	2.15	78.56	0.00	74.84	0.01	67.49	0.00			82.67	0.00	88.64	0.00	66.06	12.91	/workspace/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.2964061871
78.31	1.94	80.51	1.95	77.30	2.46	72.75	5.26			84.45	1.78	88.81	0.17	66.06	0.00	/workspace/coverage/default/1.rom_e2e_smoke.3037495276
79.79	1.47	80.68	0.17	77.42	0.12	80.95	8.20			84.62	0.17	88.99	0.17	66.06	0.00	/workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.4175662218
81.21	1.42	83.59	2.91	79.34	1.92	82.31	1.37			86.96	2.34	88.99	0.00	66.06	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_0.1202017170
82.59	1.38	83.59	0.00	79.58	0.24	82.31	0.00			87.06	0.10	88.99	0.00	74.02	7.97	/workspace/coverage/cover_reg_top/79.xbar_access_same_device_slow_rsp.724551593
83.67	1.08	85.18	1.60	81.60	2.01	82.51	0.19			89.01	1.96	89.69	0.70	74.02	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.1880537245
84.67	1.00	86.79	1.61	82.68	1.09	84.57	2.07			90.28	1.27	89.69	0.00	74.02	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_20.118755594
85.63	0.95	89.51	2.72	82.82	0.14	85.49	0.91			90.31	0.03	89.69	0.00	75.95	1.93	/workspace/coverage/cover_reg_top/92.xbar_random_zero_delays.3914137607
86.54	0.91	89.51	0.00	82.82	0.00	85.49	0.00			90.31	0.00	89.69	0.00	81.41	5.46	/workspace/coverage/cover_reg_top/80.xbar_access_same_device_slow_rsp.1266198521
87.37	0.84	89.51	0.00	82.82	0.00	85.49	0.00			90.31	0.00	89.69	0.00	86.43	5.02	/workspace/coverage/cover_reg_top/27.xbar_access_same_device_slow_rsp.1780643220
88.14	0.76	89.94	0.43	82.96	0.14	85.50	0.01			90.46	0.15	93.53	3.85	86.43	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.39217387
88.88	0.75	90.77	0.82	83.54	0.58	86.33	0.83			91.14	0.68	95.10	1.57	86.43	0.00	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.700040836
89.53	0.64	90.77	0.00	83.54	0.00	86.33	0.00			91.14	0.00	95.10	0.00	90.27	3.84	/workspace/coverage/cover_reg_top/77.xbar_access_same_device_slow_rsp.3561686004
90.17	0.64	91.63	0.86	84.83	1.29	86.84	0.51			92.32	1.18	95.10	0.00	90.27	0.00	/workspace/coverage/default/1.chip_sw_gpio_smoketest.1712082987
90.74	0.58	91.64	0.01	87.88	3.05	86.84	0.00			92.32	0.00	95.10	0.00	90.68	0.41	/workspace/coverage/cover_reg_top/11.chip_tl_errors.1389039248
91.27	0.52	92.68	1.04	88.80	0.92	87.14	0.30			93.00	0.68	95.28	0.17	90.69	0.01	/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.3605633998
91.65	0.39	92.68	0.00	88.82	0.02	88.01	0.87			93.00	0.00	95.28	0.00	92.12	1.42	/workspace/coverage/default/0.chip_sw_alert_test.3376956006
91.98	0.33	92.69	0.01	88.82	0.01	89.98	1.97			93.00	0.00	95.28	0.00	92.12	0.00	/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.4139563038
92.30	0.32	92.69	0.00	88.82	0.00	89.98	0.00			93.00	0.00	95.28	0.00	94.04	1.93	/workspace/coverage/cover_reg_top/34.xbar_access_same_device_slow_rsp.547697103
92.61	0.31	93.27	0.58	89.31	0.48	90.27	0.29			93.49	0.49	95.28	0.00	94.04	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_10.4191107562
92.85	0.24	93.27	0.00	89.31	0.00	90.27	0.00			93.49	0.00	95.28	0.00	95.49	1.45	/workspace/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.2264609517
93.06	0.21	93.27	0.00	89.32	0.01	90.27	0.00			93.49	0.00	95.28	0.00	96.75	1.26	/workspace/coverage/cover_reg_top/14.xbar_smoke_large_delays.2470216084
93.22	0.16	93.53	0.26	89.64	0.32	90.62	0.35			93.49	0.00	95.28	0.00	96.75	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2996143911
93.36	0.15	93.69	0.16	90.18	0.54	90.68	0.06			93.61	0.11	95.28	0.00	96.75	0.00	/workspace/coverage/cover_reg_top/5.chip_same_csr_outstanding.608095687
93.51	0.15	93.79	0.10	90.44	0.26	90.72	0.04			93.73	0.12	95.63	0.35	96.75	0.00	/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.1024377614
93.65	0.14	93.79	0.00	90.44	0.00	91.56	0.84			93.73	0.00	95.63	0.00	96.75	0.00	/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.4185842391
93.77	0.12	93.84	0.05	90.75	0.31	91.57	0.02			94.08	0.36	95.63	0.00	96.75	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1376786155
93.89	0.12	93.84	0.00	90.75	0.00	92.23	0.66			94.08	0.00	95.63	0.00	96.78	0.04	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.4137564548
94.00	0.11	93.84	0.00	90.88	0.13	92.23	0.00			94.08	0.00	95.63	0.00	97.32	0.54	/workspace/coverage/cover_reg_top/86.xbar_stress_all_with_error.3225071621
94.08	0.08	93.92	0.08	90.94	0.06	92.36	0.13			94.12	0.04	95.80	0.17	97.32	0.00	/workspace/coverage/default/4.chip_sw_data_integrity_escalation.1767084710
94.16	0.08	93.92	0.00	90.98	0.04	92.36	0.00			94.14	0.02	95.80	0.00	97.74	0.42	/workspace/coverage/cover_reg_top/86.xbar_access_same_device_slow_rsp.3680127104
94.24	0.08	93.92	0.00	90.98	0.00	92.83	0.47			94.14	0.00	95.80	0.00	97.74	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.3359664755
94.32	0.08	93.92	0.00	91.45	0.47	92.83	0.00			94.14	0.00	95.80	0.00	97.74	0.00	/workspace/coverage/cover_reg_top/29.chip_tl_errors.3425573570
94.39	0.08	94.09	0.17	91.51	0.05	92.84	0.01			94.19	0.05	95.98	0.17	97.76	0.01	/workspace/coverage/default/39.chip_sw_all_escalation_resets.365003873
94.47	0.08	94.25	0.16	91.62	0.11	92.91	0.06			94.31	0.12	95.98	0.00	97.76	0.00	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.3182924677
94.53	0.06	94.25	0.00	91.79	0.17	92.91	0.00			94.35	0.04	95.98	0.00	97.93	0.18	/workspace/coverage/cover_reg_top/82.xbar_stress_all.2230719947
94.60	0.06	94.27	0.02	91.95	0.16	92.92	0.02			94.53	0.18	95.98	0.00	97.93	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.221830919
94.66	0.06	94.27	0.00	91.95	0.00	93.29	0.36			94.53	0.00	95.98	0.00	97.93	0.00	/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.1702655153
94.72	0.06	94.36	0.09	92.01	0.06	93.39	0.11			94.59	0.06	95.98	0.00	97.98	0.05	/workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.3556481516
94.76	0.04	94.36	0.00	92.02	0.01	93.39	0.00			94.59	0.00	95.98	0.00	98.24	0.26	/workspace/coverage/cover_reg_top/85.xbar_stress_all_with_reset_error.3520065210
94.81	0.04	94.42	0.06	92.15	0.13	93.39	0.00			94.66	0.07	95.98	0.00	98.24	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_retention.3408857850
94.85	0.04	94.42	0.00	92.39	0.24	93.39	0.00			94.66	0.00	95.98	0.00	98.24	0.00	/workspace/coverage/cover_reg_top/18.chip_tl_errors.2812563798
94.89	0.04	94.42	0.00	92.63	0.24	93.39	0.00			94.66	0.00	95.98	0.00	98.24	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_0.2444763694
94.93	0.04	94.43	0.01	92.64	0.01	93.39	0.00			94.68	0.02	96.15	0.17	98.25	0.01	/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.3609810843
94.96	0.04	94.43	0.00	92.64	0.00	93.63	0.23			94.68	0.00	96.15	0.00	98.25	0.00	/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.2363055242
95.00	0.04	94.46	0.03	92.68	0.04	93.76	0.13			94.70	0.02	96.15	0.00	98.25	0.00	/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.2533170033
95.04	0.04	94.47	0.01	92.69	0.01	93.77	0.01			94.71	0.01	96.33	0.17	98.26	0.01	/workspace/coverage/default/25.chip_sw_all_escalation_resets.4278252821
95.07	0.04	94.47	0.00	92.70	0.01	93.80	0.03			94.71	0.00	96.50	0.17	98.26	0.00	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.330189355
95.11	0.03	94.55	0.08	92.77	0.07	93.81	0.01			94.76	0.05	96.50	0.00	98.26	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.45554739
95.14	0.03	94.55	0.00	92.77	0.00	94.02	0.21			94.76	0.00	96.50	0.00	98.26	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.1406483684
95.18	0.03	94.55	0.00	92.77	0.00	94.22	0.20			94.76	0.00	96.50	0.00	98.26	0.00	/workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.3350278039
95.20	0.03	94.58	0.03	92.81	0.04	94.29	0.07			94.78	0.02	96.50	0.00	98.26	0.00	/workspace/coverage/default/18.chip_sw_uart_rand_baudrate.3224318416
95.23	0.03	94.64	0.07	92.84	0.03	94.31	0.02			94.83	0.05	96.50	0.00	98.26	0.00	/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.4290558424
95.26	0.03	94.64	0.00	92.84	0.00	94.47	0.16			94.83	0.00	96.50	0.00	98.26	0.00	/workspace/coverage/default/2.chip_sw_kmac_entropy.2115709224
95.28	0.03	94.65	0.01	92.99	0.15	94.47	0.00			94.83	0.00	96.50	0.00	98.26	0.00	/workspace/coverage/cover_reg_top/9.chip_same_csr_outstanding.326647919
95.31	0.03	94.65	0.00	93.05	0.06	94.47	0.00			94.85	0.02	96.50	0.00	98.33	0.07	/workspace/coverage/cover_reg_top/81.xbar_stress_all_with_rand_reset.2671195855
95.33	0.02	94.72	0.07	93.05	0.00	94.54	0.07			94.86	0.01	96.50	0.00	98.33	0.00	/workspace/coverage/default/4.chip_tap_straps_rma.746640996
95.36	0.02	94.72	0.00	93.11	0.06	94.54	0.00			94.87	0.02	96.50	0.00	98.39	0.06	/workspace/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.175675401
95.38	0.02	94.77	0.06	93.16	0.05	94.55	0.01			94.89	0.02	96.50	0.00	98.39	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_wake.3517817319
95.40	0.02	94.79	0.02	93.21	0.05	94.57	0.02			94.91	0.02	96.50	0.00	98.39	0.00	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.1215859921
95.41	0.02	94.80	0.01	93.24	0.02	94.65	0.08			94.91	0.00	96.50	0.00	98.39	0.00	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2562177931
95.43	0.02	94.83	0.03	93.28	0.04	94.66	0.01			94.94	0.02	96.50	0.00	98.39	0.00	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.3569257730
95.45	0.02	94.83	0.00	93.28	0.00	94.76	0.10			94.94	0.00	96.50	0.00	98.39	0.00	/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.736785350
95.47	0.02	94.83	0.00	93.33	0.05	94.76	0.00			94.95	0.02	96.50	0.00	98.43	0.04	/workspace/coverage/cover_reg_top/36.xbar_stress_all_with_rand_reset.833979014
95.48	0.02	94.83	0.00	93.41	0.08	94.76	0.00			94.95	0.00	96.50	0.00	98.44	0.01	/workspace/coverage/cover_reg_top/1.chip_tl_errors.1774442043
95.50	0.01	94.83	0.00	93.50	0.09	94.76	0.00			94.95	0.00	96.50	0.00	98.44	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_0.3790755892
95.51	0.01	94.83	0.00	93.51	0.02	94.81	0.05			94.96	0.01	96.50	0.00	98.45	0.01	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.2637240380
95.52	0.01	94.83	0.00	93.51	0.00	94.89	0.08			94.96	0.00	96.50	0.00	98.45	0.00	/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.360554443
95.54	0.01	94.83	0.00	93.51	0.00	94.89	0.00			94.96	0.00	96.50	0.00	98.53	0.08	/workspace/coverage/cover_reg_top/94.xbar_stress_all_with_rand_reset.891129591
95.55	0.01	94.84	0.01	93.51	0.00	94.96	0.07			94.97	0.01	96.50	0.00	98.53	0.00	/workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.3403289053
95.56	0.01	94.84	0.00	93.51	0.00	95.03	0.07			94.97	0.00	96.50	0.00	98.53	0.00	/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.2000524094
95.58	0.01	94.84	0.00	93.58	0.07	95.03	0.00			94.97	0.00	96.50	0.00	98.53	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_20.1101177437
95.59	0.01	94.84	0.00	93.58	0.00	95.03	0.00			94.97	0.00	96.50	0.00	98.60	0.07	/workspace/coverage/cover_reg_top/59.xbar_stress_all_with_rand_reset.3851767249
95.60	0.01	94.85	0.01	93.63	0.04	95.04	0.01			94.98	0.01	96.50	0.00	98.60	0.00	/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.275406133
95.61	0.01	94.88	0.03	93.65	0.02	95.04	0.00			94.98	0.01	96.50	0.00	98.60	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.2158104206
95.62	0.01	94.92	0.03	93.67	0.02	95.04	0.00			94.99	0.01	96.50	0.00	98.60	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.3962278389
95.63	0.01	94.93	0.02	93.67	0.00	95.06	0.02			94.99	0.00	96.50	0.00	98.61	0.01	/workspace/coverage/default/52.chip_sw_all_escalation_resets.1823356630
95.64	0.01	94.96	0.02	93.68	0.01	95.06	0.01			95.01	0.02	96.50	0.00	98.61	0.00	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.2627203172
95.65	0.01	94.98	0.02	93.68	0.01	95.06	0.01			95.03	0.02	96.50	0.00	98.61	0.00	/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.1303076810
95.65	0.01	94.98	0.00	93.70	0.01	95.06	0.00			95.03	0.00	96.50	0.00	98.65	0.04	/workspace/coverage/cover_reg_top/85.xbar_stress_all_with_rand_reset.4146903035
95.66	0.01	94.98	0.00	93.74	0.05	95.06	0.00			95.03	0.00	96.50	0.00	98.65	0.00	/workspace/coverage/cover_reg_top/28.chip_tl_errors.721472206
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95.69	0.01	94.98	0.00	93.79	0.00	95.19	0.04			95.03	0.00	96.50	0.00	98.65	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.2666542352
95.70	0.01	94.98	0.01	93.82	0.03	95.19	0.01			95.03	0.00	96.50	0.00	98.65	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.3340403985
95.70	0.01	94.98	0.00	93.82	0.00	95.23	0.04			95.03	0.00	96.50	0.00	98.65	0.00	/workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.4046855398
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95.71	0.01	94.98	0.00	93.82	0.00	95.23	0.00			95.03	0.00	96.50	0.00	98.72	0.04	/workspace/coverage/cover_reg_top/26.xbar_stress_all_with_reset_error.784839168
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95.73	0.01	94.98	0.00	93.89	0.03	95.23	0.00			95.03	0.00	96.50	0.00	98.73	0.00	/workspace/coverage/cover_reg_top/43.xbar_stress_all.1048522520
95.73	0.01	94.98	0.00	93.89	0.00	95.26	0.03			95.03	0.00	96.50	0.00	98.73	0.00	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.757328476
95.74	0.01	94.98	0.00	93.89	0.00	95.29	0.03			95.03	0.00	96.50	0.00	98.73	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3015494675
95.74	0.01	94.98	0.00	93.90	0.01	95.29	0.00			95.03	0.00	96.50	0.00	98.75	0.02	/workspace/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.60942312
95.75	0.01	94.98	0.00	93.91	0.01	95.29	0.00			95.03	0.00	96.50	0.00	98.77	0.01	/workspace/coverage/cover_reg_top/49.xbar_stress_all_with_rand_reset.4177455968
95.75	0.01	94.98	0.00	93.91	0.00	95.31	0.03			95.03	0.00	96.50	0.00	98.77	0.00	/workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.2103390249
95.75	0.01	94.98	0.00	93.94	0.02	95.31	0.00			95.03	0.00	96.50	0.00	98.77	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_10.1074256593
95.76	0.01	94.98	0.00	93.96	0.02	95.31	0.00			95.03	0.00	96.50	0.00	98.77	0.00	/workspace/coverage/cover_reg_top/11.xbar_stress_all.2410430476
95.76	0.01	94.98	0.00	93.98	0.02	95.31	0.00			95.03	0.00	96.50	0.00	98.77	0.00	/workspace/coverage/cover_reg_top/3.chip_tl_errors.3886620635
95.77	0.01	94.98	0.00	94.00	0.02	95.31	0.00			95.03	0.00	96.50	0.00	98.77	0.00	/workspace/coverage/cover_reg_top/50.xbar_stress_all.1853299733
95.77	0.01	94.98	0.00	94.00	0.00	95.33	0.02			95.03	0.00	96.50	0.00	98.77	0.00	/workspace/coverage/default/0.chip_sw_usbdev_config_host.1750067650
95.77	0.01	94.99	0.01	94.01	0.01	95.33	0.00			95.03	0.00	96.50	0.00	98.77	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.3429802326
95.77	0.01	95.00	0.01	94.02	0.01	95.33	0.00			95.03	0.00	96.50	0.00	98.77	0.00	/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.1699981625
95.78	0.01	95.00	0.00	94.02	0.00	95.33	0.01			95.03	0.00	96.50	0.00	98.78	0.01	/workspace/coverage/default/50.chip_sw_all_escalation_resets.4239997523
95.78	0.01	95.00	0.00	94.02	0.00	95.35	0.02			95.03	0.00	96.50	0.00	98.78	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.28182420
95.78	0.01	95.00	0.00	94.02	0.00	95.37	0.02			95.03	0.00	96.50	0.00	98.78	0.00	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.327683869
95.79	0.01	95.00	0.00	94.03	0.01	95.37	0.00			95.03	0.00	96.50	0.00	98.79	0.01	/workspace/coverage/default/14.chip_sw_all_escalation_resets.285700802
95.79	0.01	95.00	0.00	94.04	0.01	95.37	0.00			95.03	0.00	96.50	0.00	98.79	0.00	/workspace/coverage/cover_reg_top/17.chip_tl_errors.2109069543
95.79	0.01	95.00	0.00	94.05	0.01	95.37	0.00			95.03	0.00	96.50	0.00	98.79	0.00	/workspace/coverage/cover_reg_top/21.xbar_stress_all.1958428800
95.79	0.01	95.00	0.00	94.07	0.01	95.37	0.00			95.03	0.00	96.50	0.00	98.79	0.00	/workspace/coverage/cover_reg_top/8.chip_csr_rw.1857386392
95.79	0.01	95.00	0.00	94.08	0.01	95.37	0.00			95.03	0.00	96.50	0.00	98.79	0.00	/workspace/coverage/cover_reg_top/80.xbar_unmapped_addr.3297374474
95.80	0.01	95.00	0.00	94.10	0.01	95.37	0.00			95.03	0.00	96.50	0.00	98.79	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_10.1013438172
95.80	0.01	95.00	0.00	94.11	0.01	95.37	0.00			95.03	0.00	96.50	0.00	98.79	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_20.3441942882
95.80	0.01	95.00	0.01	94.11	0.00	95.38	0.01			95.03	0.00	96.50	0.00	98.79	0.00	/workspace/coverage/default/0.chip_sw_power_idle_load.421856419
95.80	0.01	95.00	0.00	94.11	0.00	95.38	0.01			95.03	0.01	96.50	0.00	98.79	0.00	/workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.854595462
95.81	0.01	95.00	0.00	94.11	0.00	95.38	0.00			95.03	0.00	96.50	0.00	98.80	0.01	/workspace/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.1198275854
95.81	0.01	95.00	0.00	94.11	0.00	95.38	0.00			95.03	0.00	96.50	0.00	98.81	0.01	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.2777857219
95.81	0.01	95.00	0.00	94.11	0.00	95.38	0.00			95.03	0.00	96.50	0.00	98.83	0.01	/workspace/coverage/default/0.chip_sw_all_escalation_resets.4067482418
95.81	0.01	95.00	0.00	94.11	0.00	95.38	0.00			95.03	0.00	96.50	0.00	98.84	0.01	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.555519554
95.81	0.01	95.00	0.00	94.11	0.00	95.38	0.00			95.03	0.00	96.50	0.00	98.85	0.01	/workspace/coverage/default/1.chip_sw_all_escalation_resets.3138966348
95.82	0.01	95.00	0.00	94.11	0.00	95.38	0.00			95.03	0.00	96.50	0.00	98.86	0.01	/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.2931152622
95.82	0.01	95.00	0.00	94.11	0.00	95.38	0.00			95.03	0.00	96.50	0.00	98.87	0.01	/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.2628454395
95.82	0.01	95.00	0.00	94.11	0.00	95.38	0.00			95.03	0.00	96.50	0.00	98.88	0.01	/workspace/coverage/default/12.chip_sw_all_escalation_resets.1766112505
95.82	0.01	95.00	0.00	94.11	0.00	95.38	0.00			95.03	0.00	96.50	0.00	98.90	0.01	/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.329013421
95.82	0.01	95.00	0.00	94.11	0.00	95.38	0.00			95.03	0.00	96.50	0.00	98.91	0.01	/workspace/coverage/default/13.chip_sw_all_escalation_resets.1875658953
95.82	0.01	95.00	0.00	94.11	0.00	95.38	0.00			95.03	0.00	96.50	0.00	98.92	0.01	/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.2348502099
95.83	0.01	95.00	0.00	94.11	0.00	95.38	0.00			95.03	0.00	96.50	0.00	98.93	0.01	/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.2407200051
95.83	0.01	95.00	0.00	94.11	0.00	95.38	0.00			95.03	0.00	96.50	0.00	98.94	0.01	/workspace/coverage/default/16.chip_sw_all_escalation_resets.3102943854
95.83	0.01	95.00	0.00	94.11	0.00	95.38	0.00			95.03	0.00	96.50	0.00	98.95	0.01	/workspace/coverage/default/18.chip_sw_all_escalation_resets.109649741
95.83	0.01	95.00	0.00	94.11	0.00	95.38	0.00			95.03	0.00	96.50	0.00	98.97	0.01	/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.3673819987
95.83	0.01	95.00	0.00	94.11	0.00	95.38	0.00			95.03	0.00	96.50	0.00	98.98	0.01	/workspace/coverage/default/2.chip_sw_all_escalation_resets.1705830299
95.84	0.01	95.00	0.00	94.11	0.00	95.38	0.00			95.03	0.00	96.50	0.00	98.99	0.01	/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.2933880783
95.84	0.01	95.00	0.00	94.11	0.00	95.38	0.00			95.03	0.00	96.50	0.00	99.00	0.01	/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.1914647428
95.84	0.01	95.00	0.00	94.11	0.00	95.38	0.00			95.03	0.00	96.50	0.00	99.01	0.01	/workspace/coverage/default/21.chip_sw_all_escalation_resets.684804625
95.84	0.01	95.00	0.00	94.11	0.00	95.38	0.00			95.03	0.00	96.50	0.00	99.02	0.01	/workspace/coverage/default/24.chip_sw_all_escalation_resets.689677246
95.84	0.01	95.00	0.00	94.11	0.00	95.38	0.00			95.03	0.00	96.50	0.00	99.04	0.01	/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.2009046234
95.85	0.01	95.00	0.00	94.11	0.00	95.38	0.00			95.03	0.00	96.50	0.00	99.05	0.01	/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.1442127723
95.85	0.01	95.00	0.00	94.11	0.00	95.38	0.00			95.03	0.00	96.50	0.00	99.06	0.01	/workspace/coverage/default/26.chip_sw_all_escalation_resets.1187731226
95.85	0.01	95.00	0.00	94.11	0.00	95.38	0.00			95.03	0.00	96.50	0.00	99.07	0.01	/workspace/coverage/default/27.chip_sw_all_escalation_resets.2542758893
95.85	0.01	95.00	0.00	94.11	0.00	95.38	0.00			95.03	0.00	96.50	0.00	99.08	0.01	/workspace/coverage/default/28.chip_sw_all_escalation_resets.1798399669
95.85	0.01	95.00	0.00	94.11	0.00	95.38	0.00			95.03	0.00	96.50	0.00	99.10	0.01	/workspace/coverage/default/29.chip_sw_all_escalation_resets.482954237
95.86	0.01	95.00	0.00	94.11	0.00	95.38	0.00			95.03	0.00	96.50	0.00	99.11	0.01	/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.2587642749
95.86	0.01	95.00	0.00	94.11	0.00	95.38	0.00			95.03	0.00	96.50	0.00	99.12	0.01	/workspace/coverage/default/30.chip_sw_all_escalation_resets.97614499
95.86	0.01	95.00	0.00	94.11	0.00	95.38	0.00			95.03	0.00	96.50	0.00	99.13	0.01	/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.1922701482
95.86	0.01	95.00	0.00	94.11	0.00	95.38	0.00			95.03	0.00	96.50	0.00	99.14	0.01	/workspace/coverage/default/31.chip_sw_all_escalation_resets.3470756415
95.86	0.01	95.00	0.00	94.11	0.00	95.38	0.00			95.03	0.00	96.50	0.00	99.15	0.01	/workspace/coverage/default/32.chip_sw_all_escalation_resets.1558509976
95.87	0.01	95.00	0.00	94.11	0.00	95.38	0.00			95.03	0.00	96.50	0.00	99.17	0.01	/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.2550880019
95.87	0.01	95.00	0.00	94.11	0.00	95.38	0.00			95.03	0.00	96.50	0.00	99.18	0.01	/workspace/coverage/default/33.chip_sw_all_escalation_resets.595992261
95.87	0.01	95.00	0.00	94.11	0.00	95.38	0.00			95.03	0.00	96.50	0.00	99.19	0.01	/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.2781109960
95.87	0.01	95.00	0.00	94.11	0.00	95.38	0.00			95.03	0.00	96.50	0.00	99.20	0.01	/workspace/coverage/default/34.chip_sw_all_escalation_resets.2410203157
95.87	0.01	95.00	0.00	94.11	0.00	95.38	0.00			95.03	0.00	96.50	0.00	99.21	0.01	/workspace/coverage/default/36.chip_sw_all_escalation_resets.4193123225
95.88	0.01	95.00	0.00	94.11	0.00	95.38	0.00			95.03	0.00	96.50	0.00	99.22	0.01	/workspace/coverage/default/37.chip_sw_all_escalation_resets.1801367737
95.88	0.01	95.00	0.00	94.11	0.00	95.38	0.00			95.03	0.00	96.50	0.00	99.24	0.01	/workspace/coverage/default/38.chip_sw_all_escalation_resets.2378765375
95.88	0.01	95.00	0.00	94.11	0.00	95.38	0.00			95.03	0.00	96.50	0.00	99.25	0.01	/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.97570540
95.88	0.01	95.00	0.00	94.11	0.00	95.38	0.00			95.03	0.00	96.50	0.00	99.26	0.01	/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.3655645813
95.88	0.01	95.00	0.00	94.11	0.00	95.38	0.00			95.03	0.00	96.50	0.00	99.27	0.01	/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.2466851204
95.89	0.01	95.00	0.00	94.11	0.00	95.38	0.00			95.03	0.00	96.50	0.00	99.28	0.01	/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.3830072488
95.89	0.01	95.00	0.00	94.11	0.00	95.38	0.00			95.03	0.00	96.50	0.00	99.30	0.01	/workspace/coverage/default/44.chip_sw_all_escalation_resets.2580602854
95.89	0.01	95.00	0.00	94.11	0.00	95.38	0.00			95.03	0.00	96.50	0.00	99.31	0.01	/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.1828859719
95.89	0.01	95.00	0.00	94.11	0.00	95.38	0.00			95.03	0.00	96.50	0.00	99.32	0.01	/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.3434577524
95.89	0.01	95.00	0.00	94.11	0.00	95.38	0.00			95.03	0.00	96.50	0.00	99.33	0.01	/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.1836685472
95.90	0.01	95.00	0.00	94.11	0.00	95.38	0.00			95.03	0.00	96.50	0.00	99.34	0.01	/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.2173917928
95.90	0.01	95.00	0.00	94.11	0.00	95.38	0.00			95.03	0.00	96.50	0.00	99.35	0.01	/workspace/coverage/default/53.chip_sw_all_escalation_resets.2639962247
95.90	0.01	95.00	0.00	94.11	0.00	95.38	0.00			95.03	0.00	96.50	0.00	99.37	0.01	/workspace/coverage/default/59.chip_sw_all_escalation_resets.2839832438
95.90	0.01	95.00	0.00	94.11	0.00	95.38	0.00			95.03	0.00	96.50	0.00	99.38	0.01	/workspace/coverage/default/6.chip_sw_all_escalation_resets.1383698910
95.90	0.01	95.00	0.00	94.11	0.00	95.38	0.00			95.03	0.00	96.50	0.00	99.39	0.01	/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.986357250
95.91	0.01	95.00	0.00	94.11	0.00	95.38	0.00			95.03	0.00	96.50	0.00	99.40	0.01	/workspace/coverage/default/61.chip_sw_all_escalation_resets.946810966
95.91	0.01	95.00	0.00	94.11	0.00	95.38	0.00			95.03	0.00	96.50	0.00	99.41	0.01	/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.1521484081
95.91	0.01	95.00	0.00	94.11	0.00	95.38	0.00			95.03	0.00	96.50	0.00	99.42	0.01	/workspace/coverage/default/67.chip_sw_all_escalation_resets.4205767432
95.91	0.01	95.00	0.00	94.11	0.00	95.38	0.00			95.03	0.00	96.50	0.00	99.44	0.01	/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.467515085
95.91	0.01	95.00	0.00	94.11	0.00	95.38	0.00			95.03	0.00	96.50	0.00	99.45	0.01	/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.3643652300
95.92	0.01	95.00	0.00	94.11	0.00	95.38	0.00			95.03	0.00	96.50	0.00	99.46	0.01	/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.4024348226
95.92	0.01	95.00	0.00	94.11	0.00	95.38	0.00			95.03	0.00	96.50	0.00	99.47	0.01	/workspace/coverage/default/76.chip_sw_all_escalation_resets.2779059250
95.92	0.01	95.00	0.00	94.11	0.00	95.38	0.00			95.03	0.00	96.50	0.00	99.48	0.01	/workspace/coverage/default/79.chip_sw_all_escalation_resets.166471003
95.92	0.01	95.00	0.00	94.11	0.00	95.38	0.00			95.03	0.00	96.50	0.00	99.49	0.01	/workspace/coverage/default/80.chip_sw_all_escalation_resets.4081120490
95.92	0.01	95.00	0.00	94.11	0.00	95.38	0.00			95.03	0.00	96.50	0.00	99.51	0.01	/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.2647254300
95.92	0.01	95.00	0.00	94.12	0.01	95.38	0.00			95.03	0.00	96.50	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_entropy_src_csrng.3808462151
95.93	0.01	95.00	0.00	94.13	0.01	95.38	0.00			95.03	0.00	96.50	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.3964604532
95.93	0.01	95.00	0.00	94.14	0.01	95.38	0.00			95.03	0.00	96.50	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2872633120
95.93	0.01	95.00	0.00	94.15	0.01	95.38	0.00			95.03	0.00	96.50	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2929568374
95.93	0.01	95.00	0.00	94.16	0.01	95.38	0.00			95.03	0.00	96.50	0.00	99.51	0.00	/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.4213345011
95.93	0.01	95.00	0.00	94.17	0.01	95.38	0.00			95.03	0.00	96.50	0.00	99.51	0.00	/workspace/coverage/default/2.chip_sw_gpio.3534531329
95.94	0.01	95.01	0.01	94.17	0.00	95.39	0.01			95.03	0.00	96.50	0.00	99.51	0.00	/workspace/coverage/default/46.chip_sw_all_escalation_resets.1966121799
95.94	0.01	95.01	0.00	94.17	0.00	95.40	0.01			95.03	0.00	96.50	0.00	99.51	0.00	/workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.910727335
95.94	0.01	95.01	0.00	94.17	0.00	95.41	0.01			95.03	0.00	96.50	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.2110868886
95.94	0.01	95.01	0.00	94.17	0.00	95.42	0.01			95.03	0.00	96.50	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.3562485938
95.94	0.01	95.01	0.00	94.17	0.00	95.43	0.01			95.03	0.00	96.50	0.00	99.51	0.00	/workspace/coverage/default/1.chip_sw_hmac_enc_idle.345324909
95.94	0.01	95.01	0.00	94.17	0.00	95.44	0.01			95.03	0.00	96.50	0.00	99.51	0.00	/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.970974774
95.94	0.01	95.01	0.00	94.17	0.00	95.44	0.01			95.03	0.00	96.50	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3980309448
95.95	0.01	95.01	0.01	94.17	0.00	95.45	0.01			95.03	0.00	96.50	0.00	99.51	0.00	/workspace/coverage/cover_reg_top/4.chip_csr_rw.429926320
95.95	0.01	95.01	0.00	94.18	0.01	95.45	0.00			95.03	0.00	96.50	0.00	99.51	0.00	/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.2778246759
95.95	0.01	95.01	0.00	94.19	0.01	95.45	0.00			95.03	0.00	96.50	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.859353464
95.95	0.01	95.01	0.00	94.20	0.01	95.45	0.00			95.03	0.00	96.50	0.00	99.51	0.00	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.988514271
95.95	0.01	95.01	0.00	94.20	0.00	95.46	0.01			95.03	0.00	96.50	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3752462222
95.95	0.01	95.02	0.01	94.20	0.00	95.46	0.00			95.03	0.00	96.50	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.718696395
95.95	0.01	95.02	0.01	94.20	0.00	95.46	0.00			95.03	0.00	96.50	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_pattgen_ios.186526416
95.95	0.01	95.02	0.00	94.20	0.00	95.46	0.01			95.03	0.00	96.50	0.00	99.51	0.00	/workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.184908132
95.95	0.01	95.02	0.00	94.20	0.00	95.46	0.01			95.03	0.00	96.50	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.2462361535
95.96	0.01	95.02	0.00	94.20	0.00	95.47	0.01			95.03	0.00	96.50	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.941585033
95.96	0.01	95.02	0.00	94.20	0.00	95.47	0.01			95.03	0.00	96.50	0.00	99.51	0.00	/workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.346525450
95.96	0.01	95.02	0.00	94.20	0.00	95.48	0.01			95.03	0.00	96.50	0.00	99.51	0.00	/workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.2073984071
95.96	0.01	95.02	0.00	94.20	0.00	95.48	0.01			95.03	0.00	96.50	0.00	99.51	0.00	/workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.3050142014
95.96	0.01	95.02	0.00	94.20	0.01	95.48	0.00			95.03	0.00	96.50	0.00	99.51	0.00	/workspace/coverage/cover_reg_top/13.chip_tl_errors.3040648139
95.96	0.01	95.02	0.00	94.20	0.01	95.48	0.00			95.03	0.00	96.50	0.00	99.51	0.00	/workspace/coverage/cover_reg_top/21.xbar_stress_all_with_reset_error.1236568381
95.96	0.01	95.02	0.00	94.21	0.01	95.48	0.00			95.03	0.00	96.50	0.00	99.51	0.00	/workspace/coverage/cover_reg_top/26.xbar_stress_all_with_error.3146527749
95.96	0.01	95.02	0.00	94.21	0.01	95.48	0.00			95.03	0.00	96.50	0.00	99.51	0.00	/workspace/coverage/cover_reg_top/39.xbar_stress_all_with_error.2987708526
95.96	0.01	95.02	0.00	94.21	0.01	95.48	0.00			95.03	0.00	96.50	0.00	99.51	0.00	/workspace/coverage/cover_reg_top/59.xbar_stress_all_with_reset_error.3937402871
95.96	0.01	95.02	0.00	94.22	0.01	95.48	0.00			95.03	0.00	96.50	0.00	99.51	0.00	/workspace/coverage/cover_reg_top/64.xbar_stress_all_with_error.3558710818
95.96	0.01	95.02	0.00	94.22	0.01	95.48	0.00			95.03	0.00	96.50	0.00	99.51	0.00	/workspace/coverage/cover_reg_top/66.xbar_stress_all_with_error.3434842880
95.96	0.01	95.02	0.00	94.22	0.01	95.48	0.00			95.03	0.00	96.50	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.1836185593
95.96	0.01	95.02	0.00	94.23	0.01	95.48	0.00			95.03	0.00	96.50	0.00	99.51	0.00	/workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.2336970543
95.96	0.01	95.03	0.01	94.23	0.00	95.48	0.00			95.03	0.00	96.50	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.3158238591
95.96	0.01	95.03	0.00	94.23	0.00	95.49	0.01			95.03	0.00	96.50	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_edn_boot_mode.515767947
95.96	0.01	95.03	0.00	94.23	0.00	95.49	0.01			95.03	0.00	96.50	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.3204427090
95.96	0.01	95.03	0.00	94.23	0.00	95.49	0.01			95.03	0.00	96.50	0.00	99.51	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.2748719830

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.1262695996
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.1733247439
/workspace/coverage/cover_reg_top/0.chip_csr_rw.1191328404
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.3485189575
/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.3086230033
/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.1864862212
/workspace/coverage/cover_reg_top/0.chip_tl_errors.3558545971
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.3422808470
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.630265334
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.3868345164
/workspace/coverage/cover_reg_top/0.xbar_error_random.561555944
/workspace/coverage/cover_reg_top/0.xbar_random.1711208926
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.467925984
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.1042005198
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.2601662616
/workspace/coverage/cover_reg_top/0.xbar_same_source.2968227607
/workspace/coverage/cover_reg_top/0.xbar_smoke.2888499940
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.1643025655
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.3420828903
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.2349216957
/workspace/coverage/cover_reg_top/0.xbar_stress_all.1996134323
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.847762469
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.1936248360
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.1309921184
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.576014617
/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.3003140219
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.3121316930
/workspace/coverage/cover_reg_top/1.chip_csr_rw.1911282771
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.3078848893
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.1087372483
/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.3897388342
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.330627820
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.1703305104
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.2269473810
/workspace/coverage/cover_reg_top/1.xbar_error_random.3976619697
/workspace/coverage/cover_reg_top/1.xbar_random.2661114111
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.1046086396
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.2410114063
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.176656010
/workspace/coverage/cover_reg_top/1.xbar_same_source.3382800663
/workspace/coverage/cover_reg_top/1.xbar_smoke.3082677031
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.169094745
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.2832987043
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.3177361405
/workspace/coverage/cover_reg_top/1.xbar_stress_all.3516556737
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.1812881353
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.4282068219
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.1011614290
/workspace/coverage/cover_reg_top/10.chip_csr_rw.2307523079
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.3041273046
/workspace/coverage/cover_reg_top/10.chip_tl_errors.1627574334
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.85690324
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.715477463
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.1664435944
/workspace/coverage/cover_reg_top/10.xbar_error_random.1672752299
/workspace/coverage/cover_reg_top/10.xbar_random.3426516521
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.1497645536
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.4182355003
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.3103381943
/workspace/coverage/cover_reg_top/10.xbar_same_source.3387850006
/workspace/coverage/cover_reg_top/10.xbar_smoke.3810268976
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.2917648217
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.2545818246
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.701309854
/workspace/coverage/cover_reg_top/10.xbar_stress_all.2658846661
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.3784752466
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.118083524
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.2894058388
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.2044175866
/workspace/coverage/cover_reg_top/11.chip_csr_rw.2588839603
/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.2736665217
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.566544845
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.2730671181
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.127264681
/workspace/coverage/cover_reg_top/11.xbar_error_random.229045090
/workspace/coverage/cover_reg_top/11.xbar_random.1349364977
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.2863303821
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.3582281472
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.3194665292
/workspace/coverage/cover_reg_top/11.xbar_same_source.511610071
/workspace/coverage/cover_reg_top/11.xbar_smoke.3095394708
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.1937694660
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.328942126
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.2374368345
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.2456236455
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.4033561548
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.3777798767
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.36131060
/workspace/coverage/cover_reg_top/12.chip_csr_rw.340063575
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.2939463446
/workspace/coverage/cover_reg_top/12.chip_tl_errors.3393386346
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.2394278625
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.2388023506
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.261889192
/workspace/coverage/cover_reg_top/12.xbar_error_random.2447397440
/workspace/coverage/cover_reg_top/12.xbar_random.2109141638
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.2700754797
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.2646315801
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.4172617716
/workspace/coverage/cover_reg_top/12.xbar_same_source.3316830847
/workspace/coverage/cover_reg_top/12.xbar_smoke.2330774473
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.453246713
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.4036894093
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.705579417
/workspace/coverage/cover_reg_top/12.xbar_stress_all.1642880795
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.1047744121
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.2031621411
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.787002591
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.446568014
/workspace/coverage/cover_reg_top/13.chip_csr_rw.2478815567
/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.2402742810
/workspace/coverage/cover_reg_top/13.xbar_access_same_device.1119691685
/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.1871410083
/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.3134800392
/workspace/coverage/cover_reg_top/13.xbar_error_random.192918537
/workspace/coverage/cover_reg_top/13.xbar_random.4286959203
/workspace/coverage/cover_reg_top/13.xbar_random_large_delays.1337202985
/workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.3915020506
/workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.1200602577
/workspace/coverage/cover_reg_top/13.xbar_same_source.1890964022
/workspace/coverage/cover_reg_top/13.xbar_smoke.3245905630
/workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.3924877877
/workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.2525281678
/workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.4207795307
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/workspace/coverage/default/3.chip_tap_straps_testunlock0.3451121199
/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.4012252974
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/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.926461986
/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.1943912723
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/workspace/coverage/default/4.chip_sw_all_escalation_resets.319543974
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/workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.236717488
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.1596611950
/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.1257398807
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/workspace/coverage/default/4.chip_sw_uart_tx_rx.3042991040
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.319941686
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2865120611
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/workspace/coverage/default/48.chip_sw_all_escalation_resets.3002239502
/workspace/coverage/default/49.chip_sw_all_escalation_resets.554413607
/workspace/coverage/default/5.chip_sw_all_escalation_resets.3693284915
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.3956513808
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.825098459
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.1840022380
/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.2095100578
/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.4252148183
/workspace/coverage/default/51.chip_sw_all_escalation_resets.3709703400
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.2127799729
/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.2947736246
/workspace/coverage/default/54.chip_sw_all_escalation_resets.2163471990
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.2304907060
/workspace/coverage/default/55.chip_sw_all_escalation_resets.1220914171
/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.481707631
/workspace/coverage/default/56.chip_sw_all_escalation_resets.3975664459
/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.2481076512
/workspace/coverage/default/57.chip_sw_all_escalation_resets.2187670290
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.3420721338
/workspace/coverage/default/58.chip_sw_all_escalation_resets.3423256567
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.3337166655
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.1641665038
/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.1555300987
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.2446898630
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.3641614048
/workspace/coverage/default/60.chip_sw_all_escalation_resets.2766865939
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.4175959031
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.3847160162
/workspace/coverage/default/62.chip_sw_all_escalation_resets.2889963883
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.3379476687
/workspace/coverage/default/63.chip_sw_all_escalation_resets.1563697602
/workspace/coverage/default/64.chip_sw_all_escalation_resets.1046534783
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.2731185956
/workspace/coverage/default/65.chip_sw_all_escalation_resets.472848410
/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.79377542
/workspace/coverage/default/66.chip_sw_all_escalation_resets.2139070532
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.2048849370
/workspace/coverage/default/68.chip_sw_all_escalation_resets.1401790990
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.340248379
/workspace/coverage/default/69.chip_sw_all_escalation_resets.2546937634
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.72021664
/workspace/coverage/default/7.chip_sw_all_escalation_resets.3621308888
/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.2553071698
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.259287864
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.3024233185
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.152815451
/workspace/coverage/default/70.chip_sw_all_escalation_resets.3010175334
/workspace/coverage/default/71.chip_sw_all_escalation_resets.1767266824
/workspace/coverage/default/72.chip_sw_all_escalation_resets.2647625431
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.4218852493
/workspace/coverage/default/73.chip_sw_all_escalation_resets.1459928103
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.1407917904
/workspace/coverage/default/74.chip_sw_all_escalation_resets.2826902868
/workspace/coverage/default/75.chip_sw_all_escalation_resets.3487084447
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.3010322371
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.364538236
/workspace/coverage/default/77.chip_sw_all_escalation_resets.3061884440
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.681618396
/workspace/coverage/default/78.chip_sw_all_escalation_resets.3684886582
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.1480118804
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.1709017834
/workspace/coverage/default/8.chip_sw_all_escalation_resets.33996042
/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.980466819
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.1855750181
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.2846156203
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.2607722734
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.388416286
/workspace/coverage/default/81.chip_sw_all_escalation_resets.3141214498
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.4038233055
/workspace/coverage/default/82.chip_sw_all_escalation_resets.431725891
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.1044233730
/workspace/coverage/default/83.chip_sw_all_escalation_resets.862219127
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.3969316551
/workspace/coverage/default/84.chip_sw_all_escalation_resets.911904531
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.3418892565
/workspace/coverage/default/85.chip_sw_all_escalation_resets.3390677512
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.1503869465
/workspace/coverage/default/86.chip_sw_all_escalation_resets.1330168396
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.1566856429
/workspace/coverage/default/87.chip_sw_all_escalation_resets.3258048134
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.35357934
/workspace/coverage/default/88.chip_sw_all_escalation_resets.1396087683
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.1705167260
/workspace/coverage/default/89.chip_sw_all_escalation_resets.2885809460
/workspace/coverage/default/9.chip_sw_all_escalation_resets.4011954603
/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.2404437520
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.4103407030
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.3186703586
/workspace/coverage/default/90.chip_sw_all_escalation_resets.1188145543
/workspace/coverage/default/91.chip_sw_all_escalation_resets.281048252
/workspace/coverage/default/92.chip_sw_all_escalation_resets.2732773266
/workspace/coverage/default/95.chip_sw_all_escalation_resets.1915868921
/workspace/coverage/default/96.chip_sw_all_escalation_resets.2928433507
/workspace/coverage/default/97.chip_sw_all_escalation_resets.1866449010
/workspace/coverage/default/98.chip_sw_all_escalation_resets.2129448688
/workspace/coverage/default/99.chip_sw_all_escalation_resets.2346741058
/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.4171091435
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.608719862
/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.433067226
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.2484592743
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.1979686718
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.2268430610
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.934670082
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.1191978394

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Total test records in report: 2881

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T4	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.742033909			Jun 06 04:25:31 PM PDT 24	Jun 06 04:39:30 PM PDT 24	4988582410 ps
T5	/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.360554443			Jun 06 04:21:50 PM PDT 24	Jun 06 04:27:07 PM PDT 24	3258365506 ps
T6	/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.1048607076			Jun 06 04:32:15 PM PDT 24	Jun 06 04:47:53 PM PDT 24	7833599520 ps
T62	/workspace/coverage/default/1.chip_tap_straps_rma.3325708678			Jun 06 04:23:41 PM PDT 24	Jun 06 04:31:30 PM PDT 24	5744238546 ps
T59	/workspace/coverage/default/1.rom_e2e_smoke.3037495276			Jun 06 04:30:54 PM PDT 24	Jun 06 05:23:37 PM PDT 24	14891337976 ps
T19	/workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.3339466592			Jun 06 04:11:45 PM PDT 24	Jun 06 04:21:08 PM PDT 24	4413703116 ps
T64	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.18609142			Jun 06 04:25:08 PM PDT 24	Jun 06 04:35:26 PM PDT 24	4779903000 ps
T20	/workspace/coverage/default/93.chip_sw_all_escalation_resets.1132204894			Jun 06 04:47:06 PM PDT 24	Jun 06 04:55:31 PM PDT 24	4971971132 ps
T68	/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.3605633998			Jun 06 04:48:58 PM PDT 24	Jun 06 04:54:13 PM PDT 24	3600882716 ps
T91	/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.4139563038			Jun 06 04:38:31 PM PDT 24	Jun 06 05:47:20 PM PDT 24	19875707400 ps
T127	/workspace/coverage/default/2.chip_sw_edn_boot_mode.1508726559			Jun 06 04:32:44 PM PDT 24	Jun 06 04:44:38 PM PDT 24	2922344738 ps
T121	/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.2363055242			Jun 06 04:11:06 PM PDT 24	Jun 06 04:15:11 PM PDT 24	2413474057 ps
T124	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2562177931			Jun 06 04:17:17 PM PDT 24	Jun 06 04:35:52 PM PDT 24	8114172298 ps
T47	/workspace/coverage/default/52.chip_sw_all_escalation_resets.1823356630			Jun 06 04:43:41 PM PDT 24	Jun 06 04:54:43 PM PDT 24	4859237082 ps
T21	/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.1596611950			Jun 06 04:37:41 PM PDT 24	Jun 06 04:49:17 PM PDT 24	12820635946 ps
T126	/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.4256558029			Jun 06 04:24:03 PM PDT 24	Jun 06 04:37:53 PM PDT 24	6528036464 ps
T87	/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.467515085			Jun 06 04:46:12 PM PDT 24	Jun 06 04:53:23 PM PDT 24	3544244692 ps
T32	/workspace/coverage/default/0.chip_sw_usbdev_pullup.3982162042			Jun 06 04:11:20 PM PDT 24	Jun 06 04:16:24 PM PDT 24	2891338324 ps
T130	/workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.1757353795			Jun 06 04:21:49 PM PDT 24	Jun 06 05:30:42 PM PDT 24	15007973048 ps
T60	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.1078286328			Jun 06 04:21:16 PM PDT 24	Jun 06 05:48:55 PM PDT 24	22905715712 ps
T216	/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.417017473			Jun 06 04:29:28 PM PDT 24	Jun 06 04:45:04 PM PDT 24	5395298816 ps
T30	/workspace/coverage/default/18.chip_sw_uart_rand_baudrate.3224318416			Jun 06 04:41:56 PM PDT 24	Jun 06 04:52:45 PM PDT 24	4612183706 ps
T70	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3294141349			Jun 06 04:18:17 PM PDT 24	Jun 06 04:59:25 PM PDT 24	27282597864 ps
T171	/workspace/coverage/default/89.chip_sw_all_escalation_resets.2885809460			Jun 06 04:46:57 PM PDT 24	Jun 06 04:55:52 PM PDT 24	4986352492 ps
T63	/workspace/coverage/default/1.chip_sw_alert_handler_escalation.1005428941			Jun 06 04:20:55 PM PDT 24	Jun 06 04:31:02 PM PDT 24	4948148204 ps
T909	/workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.3246991483			Jun 06 04:33:38 PM PDT 24	Jun 06 04:42:18 PM PDT 24	4760160820 ps
T122	/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.3693078212			Jun 06 04:34:51 PM PDT 24	Jun 06 04:39:14 PM PDT 24	3276436320 ps
T73	/workspace/coverage/default/1.chip_tap_straps_dev.828609566			Jun 06 04:23:55 PM PDT 24	Jun 06 04:26:27 PM PDT 24	2641021776 ps
T256	/workspace/coverage/default/0.chip_sw_rv_timer_irq.4258253297			Jun 06 04:17:14 PM PDT 24	Jun 06 04:21:59 PM PDT 24	3454529956 ps
T191	/workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.3556481516			Jun 06 04:23:17 PM PDT 24	Jun 06 04:49:44 PM PDT 24	10582061078 ps
T454	/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.2348502099			Jun 06 04:41:33 PM PDT 24	Jun 06 04:47:13 PM PDT 24	3966737216 ps
T158	/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.926461986			Jun 06 04:48:15 PM PDT 24	Jun 06 04:56:33 PM PDT 24	3916186520 ps
T154	/workspace/coverage/default/2.chip_plic_all_irqs_10.4191107562			Jun 06 04:33:19 PM PDT 24	Jun 06 04:43:47 PM PDT 24	4108745360 ps
T329	/workspace/coverage/default/2.chip_sw_hmac_enc.291939844			Jun 06 04:32:14 PM PDT 24	Jun 06 04:35:44 PM PDT 24	2412261816 ps
T50	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.399458903			Jun 06 04:31:00 PM PDT 24	Jun 06 04:41:07 PM PDT 24	5647895302 ps
T155	/workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.4214987183			Jun 06 04:11:46 PM PDT 24	Jun 06 04:16:43 PM PDT 24	3068196250 ps
T377	/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.329013421			Jun 06 04:40:42 PM PDT 24	Jun 06 04:46:04 PM PDT 24	4124297984 ps
T222	/workspace/coverage/default/38.chip_sw_all_escalation_resets.2378765375			Jun 06 04:43:03 PM PDT 24	Jun 06 04:52:52 PM PDT 24	5838821640 ps
T378	/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.2048849370			Jun 06 04:45:44 PM PDT 24	Jun 06 04:53:07 PM PDT 24	3885183710 ps
T258	/workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.2695596533			Jun 06 04:28:29 PM PDT 24	Jun 06 04:34:12 PM PDT 24	4251267696 ps
T22	/workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.4175662218			Jun 06 04:28:34 PM PDT 24	Jun 06 06:03:42 PM PDT 24	48882305400 ps
T254	/workspace/coverage/default/1.chip_sw_plic_sw_irq.2124214447			Jun 06 04:25:46 PM PDT 24	Jun 06 04:30:43 PM PDT 24	2504042250 ps
T750	/workspace/coverage/default/1.chip_sw_aes_smoketest.312999350			Jun 06 04:35:03 PM PDT 24	Jun 06 04:38:41 PM PDT 24	2981632512 ps
T61	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.674188627			Jun 06 04:23:24 PM PDT 24	Jun 06 05:22:35 PM PDT 24	14317845610 ps
T558	/workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.3610510778			Jun 06 04:19:12 PM PDT 24	Jun 06 04:29:36 PM PDT 24	5930264996 ps
T751	/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.2992156545			Jun 06 04:25:52 PM PDT 24	Jun 06 04:31:02 PM PDT 24	2773230102 ps
T248	/workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.1033806347			Jun 06 04:18:22 PM PDT 24	Jun 06 04:31:01 PM PDT 24	7491962262 ps
T69	/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.2299040609			Jun 06 04:28:37 PM PDT 24	Jun 06 04:30:39 PM PDT 24	2386819658 ps
T27	/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.2533170033			Jun 06 04:28:09 PM PDT 24	Jun 06 04:39:05 PM PDT 24	4731122091 ps
T400	/workspace/coverage/default/1.rom_e2e_asm_init_rma.4115227190			Jun 06 04:32:18 PM PDT 24	Jun 06 05:29:32 PM PDT 24	13780731778 ps
T1	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.700040836			Jun 06 04:24:25 PM PDT 24	Jun 06 04:51:26 PM PDT 24	20464009200 ps
T74	/workspace/coverage/default/3.chip_tap_straps_testunlock0.3451121199			Jun 06 04:37:28 PM PDT 24	Jun 06 04:42:55 PM PDT 24	4386718251 ps
T107	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.3182924677			Jun 06 04:18:39 PM PDT 24	Jun 06 04:23:35 PM PDT 24	3211238940 ps
T108	/workspace/coverage/default/0.chip_plic_all_irqs_20.118755594			Jun 06 04:11:48 PM PDT 24	Jun 06 04:25:39 PM PDT 24	4170866416 ps
T109	/workspace/coverage/default/4.chip_sw_data_integrity_escalation.1767084710			Jun 06 04:38:14 PM PDT 24	Jun 06 04:51:21 PM PDT 24	6867710674 ps
T23	/workspace/coverage/default/12.chip_sw_lc_ctrl_transition.1440288933			Jun 06 04:39:17 PM PDT 24	Jun 06 04:49:46 PM PDT 24	7554527273 ps
T110	/workspace/coverage/default/97.chip_sw_all_escalation_resets.1866449010			Jun 06 04:48:30 PM PDT 24	Jun 06 04:57:42 PM PDT 24	5800078560 ps
T111	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.2076324943			Jun 06 04:09:41 PM PDT 24	Jun 06 04:21:44 PM PDT 24	9172679094 ps
T56	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.2666482347			Jun 06 04:18:42 PM PDT 24	Jun 06 05:15:27 PM PDT 24	14398570732 ps
T112	/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.4252148183			Jun 06 04:44:39 PM PDT 24	Jun 06 04:51:23 PM PDT 24	4484251678 ps
T235	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.2674282079			Jun 06 04:20:11 PM PDT 24	Jun 06 05:19:44 PM PDT 24	14513192920 ps
T272	/workspace/coverage/default/95.chip_sw_all_escalation_resets.1915868921			Jun 06 04:46:18 PM PDT 24	Jun 06 04:54:56 PM PDT 24	6223457568 ps
T128	/workspace/coverage/default/0.chip_sw_edn_boot_mode.515767947			Jun 06 04:13:22 PM PDT 24	Jun 06 04:24:05 PM PDT 24	3431459340 ps
T186	/workspace/coverage/default/13.chip_sw_lc_ctrl_transition.1091714794			Jun 06 04:43:36 PM PDT 24	Jun 06 04:51:42 PM PDT 24	7567581728 ps
T458	/workspace/coverage/default/2.chip_sw_flash_ctrl_access.1689473501			Jun 06 04:27:37 PM PDT 24	Jun 06 04:46:03 PM PDT 24	5434788616 ps
T213	/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.3641614048			Jun 06 04:38:12 PM PDT 24	Jun 06 05:23:48 PM PDT 24	13048104350 ps
T401	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.4162046552			Jun 06 04:22:51 PM PDT 24	Jun 06 05:09:49 PM PDT 24	10552834124 ps
T910	/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.1699841582			Jun 06 04:45:18 PM PDT 24	Jun 06 05:30:51 PM PDT 24	13913703800 ps
T57	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.2637240380			Jun 06 04:18:17 PM PDT 24	Jun 06 05:26:33 PM PDT 24	13608182045 ps
T169	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.888873935			Jun 06 04:11:34 PM PDT 24	Jun 06 04:29:52 PM PDT 24	8724601372 ps
T911	/workspace/coverage/default/2.chip_sw_clkmgr_smoketest.2196005			Jun 06 04:36:53 PM PDT 24	Jun 06 04:42:01 PM PDT 24	2527331480 ps
T752	/workspace/coverage/default/0.chip_sw_hmac_smoketest.1783787133			Jun 06 04:16:35 PM PDT 24	Jun 06 04:23:46 PM PDT 24	3748525454 ps
T392	/workspace/coverage/default/74.chip_sw_all_escalation_resets.2826902868			Jun 06 04:45:10 PM PDT 24	Jun 06 04:56:45 PM PDT 24	5052613806 ps
T721	/workspace/coverage/default/1.rom_e2e_asm_init_prod_end.3137940908			Jun 06 04:32:01 PM PDT 24	Jun 06 05:37:05 PM PDT 24	13926176008 ps
T125	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.808031208			Jun 06 04:33:54 PM PDT 24	Jun 06 04:43:32 PM PDT 24	4809157364 ps
T131	/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.4290558424			Jun 06 04:34:50 PM PDT 24	Jun 06 04:50:09 PM PDT 24	8541559360 ps
T468	/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.2553071698			Jun 06 04:38:56 PM PDT 24	Jun 06 05:11:13 PM PDT 24	9069687440 ps
T75	/workspace/coverage/default/1.chip_jtag_csr_rw.358481714			Jun 06 04:16:25 PM PDT 24	Jun 06 04:41:53 PM PDT 24	12019517470 ps
T912	/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.424035944			Jun 06 04:30:25 PM PDT 24	Jun 06 04:54:36 PM PDT 24	12097892521 ps
T31	/workspace/coverage/default/1.chip_sw_gpio_smoketest.1712082987			Jun 06 04:28:04 PM PDT 24	Jun 06 04:32:15 PM PDT 24	3353700794 ps
T451	/workspace/coverage/default/1.chip_sw_kmac_app_rom.3067677959			Jun 06 04:21:53 PM PDT 24	Jun 06 04:24:30 PM PDT 24	3294224120 ps
T913	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3212175461			Jun 06 04:32:42 PM PDT 24	Jun 06 04:43:46 PM PDT 24	4766496500 ps
T914	/workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.3835138200			Jun 06 04:35:44 PM PDT 24	Jun 06 04:39:00 PM PDT 24	2837926994 ps
T118	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3980309448			Jun 06 04:16:03 PM PDT 24	Jun 06 05:30:09 PM PDT 24	25140590763 ps
T395	/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.4024348226			Jun 06 04:46:11 PM PDT 24	Jun 06 04:51:17 PM PDT 24	3347607072 ps
T179	/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.3562485938			Jun 06 04:14:16 PM PDT 24	Jun 06 04:27:10 PM PDT 24	8324373820 ps
T305	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.302268319			Jun 06 04:09:31 PM PDT 24	Jun 06 04:19:15 PM PDT 24	4469114488 ps
T214	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.2055388457			Jun 06 04:39:11 PM PDT 24	Jun 06 04:48:51 PM PDT 24	4357233640 ps
T306	/workspace/coverage/default/8.chip_sw_all_escalation_resets.33996042			Jun 06 04:39:31 PM PDT 24	Jun 06 04:50:14 PM PDT 24	6328364018 ps
T307	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2865083159			Jun 06 04:18:18 PM PDT 24	Jun 06 04:30:44 PM PDT 24	4222419176 ps
T160	/workspace/coverage/default/43.chip_sw_all_escalation_resets.1724504429			Jun 06 04:42:31 PM PDT 24	Jun 06 04:52:44 PM PDT 24	4405306308 ps
T308	/workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.2112751326			Jun 06 04:35:46 PM PDT 24	Jun 06 04:55:06 PM PDT 24	5940398350 ps
T309	/workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.1455804317			Jun 06 04:10:14 PM PDT 24	Jun 06 04:19:28 PM PDT 24	5213279240 ps
T226	/workspace/coverage/default/37.chip_sw_all_escalation_resets.1801367737			Jun 06 04:42:30 PM PDT 24	Jun 06 04:52:26 PM PDT 24	4976675784 ps
T161	/workspace/coverage/default/20.chip_sw_all_escalation_resets.1818443210			Jun 06 04:40:32 PM PDT 24	Jun 06 04:49:55 PM PDT 24	4616991096 ps
T345	/workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.3964604532			Jun 06 04:12:48 PM PDT 24	Jun 06 04:21:01 PM PDT 24	4253966376 ps
T76	/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3015494675			Jun 06 04:11:43 PM PDT 24	Jun 06 04:21:33 PM PDT 24	5367023896 ps
T915	/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.3163455989			Jun 06 04:39:15 PM PDT 24	Jun 06 04:42:41 PM PDT 24	3148013113 ps
T215	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.2575804843			Jun 06 04:38:36 PM PDT 24	Jun 06 04:48:41 PM PDT 24	4446679160 ps
T24	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.1880537245			Jun 06 04:28:25 PM PDT 24	Jun 06 04:32:49 PM PDT 24	2267968416 ps
T916	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1289909908			Jun 06 04:32:42 PM PDT 24	Jun 06 04:44:32 PM PDT 24	4191608888 ps
T469	/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.889577227			Jun 06 04:21:44 PM PDT 24	Jun 06 05:22:05 PM PDT 24	14892640160 ps
T170	/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.4185842391			Jun 06 04:11:25 PM PDT 24	Jun 06 05:39:12 PM PDT 24	43663345716 ps
T166	/workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.966671709			Jun 06 04:10:26 PM PDT 24	Jun 06 04:56:25 PM PDT 24	33841398040 ps
T223	/workspace/coverage/default/0.chip_sw_alert_handler_escalation.3009551086			Jun 06 04:12:22 PM PDT 24	Jun 06 04:19:53 PM PDT 24	4809329730 ps
T359	/workspace/coverage/default/51.chip_sw_all_escalation_resets.3709703400			Jun 06 04:43:05 PM PDT 24	Jun 06 04:51:49 PM PDT 24	4235990404 ps
T917	/workspace/coverage/default/1.chip_sw_clkmgr_jitter.3399376134			Jun 06 04:24:31 PM PDT 24	Jun 06 04:28:22 PM PDT 24	2962702894 ps
T461	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.415480152			Jun 06 04:33:07 PM PDT 24	Jun 06 04:39:09 PM PDT 24	3011321628 ps
T391	/workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.2584995830			Jun 06 04:29:50 PM PDT 24	Jun 06 04:33:15 PM PDT 24	2502820564 ps
T807	/workspace/coverage/default/81.chip_sw_all_escalation_resets.3141214498			Jun 06 04:46:41 PM PDT 24	Jun 06 04:58:27 PM PDT 24	6306815272 ps
T918	/workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.1746155862			Jun 06 04:28:03 PM PDT 24	Jun 06 04:51:37 PM PDT 24	5282103286 ps
T919	/workspace/coverage/default/2.chip_sw_entropy_src_kat_test.2388644363			Jun 06 04:31:04 PM PDT 24	Jun 06 04:34:01 PM PDT 24	2823346550 ps
T722	/workspace/coverage/default/2.rom_e2e_asm_init_prod.394830081			Jun 06 04:41:15 PM PDT 24	Jun 06 05:32:01 PM PDT 24	15149066301 ps
T351	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.2911429855			Jun 06 04:17:23 PM PDT 24	Jun 06 04:29:39 PM PDT 24	4753174761 ps
T920	/workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.3583232638			Jun 06 04:32:46 PM PDT 24	Jun 06 04:39:51 PM PDT 24	5227016272 ps
T385	/workspace/coverage/default/80.chip_sw_all_escalation_resets.4081120490			Jun 06 04:46:25 PM PDT 24	Jun 06 04:55:13 PM PDT 24	5419500720 ps
T921	/workspace/coverage/default/2.chip_sw_csrng_kat_test.2464711708			Jun 06 04:31:49 PM PDT 24	Jun 06 04:35:07 PM PDT 24	2210412360 ps
T459	/workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.388784626			Jun 06 04:14:40 PM PDT 24	Jun 06 04:31:26 PM PDT 24	5596575284 ps
T2	/workspace/coverage/default/2.chip_sw_sleep_pin_retention.3408857850			Jun 06 04:27:58 PM PDT 24	Jun 06 04:34:02 PM PDT 24	4091418848 ps
T404	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1179408365			Jun 06 04:18:05 PM PDT 24	Jun 06 04:45:54 PM PDT 24	17781561522 ps
T396	/workspace/coverage/default/13.chip_sw_all_escalation_resets.1875658953			Jun 06 04:41:27 PM PDT 24	Jun 06 04:52:47 PM PDT 24	4664414538 ps
T352	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1027560940			Jun 06 04:22:04 PM PDT 24	Jun 06 04:33:10 PM PDT 24	4540194579 ps
T405	/workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.418674908			Jun 06 04:13:08 PM PDT 24	Jun 06 04:20:32 PM PDT 24	3548034840 ps
T406	/workspace/coverage/default/2.chip_sw_flash_crash_alert.697482246			Jun 06 04:35:21 PM PDT 24	Jun 06 04:46:50 PM PDT 24	5447845830 ps
T407	/workspace/coverage/default/2.chip_sw_ast_clk_outputs.1570211016			Jun 06 04:33:55 PM PDT 24	Jun 06 04:49:13 PM PDT 24	7830042856 ps
T408	/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.3828664732			Jun 06 04:32:53 PM PDT 24	Jun 06 05:29:16 PM PDT 24	14650058830 ps
T220	/workspace/coverage/default/1.chip_sw_uart_rand_baudrate.2159260203			Jun 06 04:16:24 PM PDT 24	Jun 06 04:51:12 PM PDT 24	8379584272 ps
T409	/workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.3264486886			Jun 06 04:30:02 PM PDT 24	Jun 06 04:54:35 PM PDT 24	13687822553 ps
T922	/workspace/coverage/default/2.chip_sw_example_concurrency.3901335881			Jun 06 04:27:59 PM PDT 24	Jun 06 04:33:20 PM PDT 24	2791646336 ps
T168	/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.1702655153			Jun 06 04:09:19 PM PDT 24	Jun 06 05:42:46 PM PDT 24	48842507580 ps
T923	/workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.2215001163			Jun 06 04:19:30 PM PDT 24	Jun 06 04:22:44 PM PDT 24	2021507194 ps
T462	/workspace/coverage/default/2.chip_sw_kmac_smoketest.3748926889			Jun 06 04:37:27 PM PDT 24	Jun 06 04:42:53 PM PDT 24	2909235464 ps
T78	/workspace/coverage/default/2.chip_tap_straps_prod.3120169002			Jun 06 04:33:10 PM PDT 24	Jun 06 04:57:00 PM PDT 24	12560985188 ps
T924	/workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.794689321			Jun 06 04:24:46 PM PDT 24	Jun 06 04:29:37 PM PDT 24	3477792623 ps
T312	/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.986357250			Jun 06 04:44:15 PM PDT 24	Jun 06 04:50:24 PM PDT 24	3379176128 ps
T318	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.3340403985			Jun 06 04:10:28 PM PDT 24	Jun 06 04:36:34 PM PDT 24	8090453617 ps
T319	/workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.2571584542			Jun 06 04:29:58 PM PDT 24	Jun 06 04:36:58 PM PDT 24	5747472628 ps
T320	/workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.2902211908			Jun 06 04:32:45 PM PDT 24	Jun 06 05:04:00 PM PDT 24	28823385752 ps
T321	/workspace/coverage/default/0.chip_sw_uart_smoketest.1152957773			Jun 06 04:18:54 PM PDT 24	Jun 06 04:25:02 PM PDT 24	3039478910 ps
T322	/workspace/coverage/default/50.chip_sw_all_escalation_resets.4239997523			Jun 06 04:43:03 PM PDT 24	Jun 06 04:52:30 PM PDT 24	5882820488 ps
T185	/workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.965825536			Jun 06 04:21:12 PM PDT 24	Jun 06 04:27:23 PM PDT 24	5318426508 ps
T323	/workspace/coverage/default/28.chip_sw_all_escalation_resets.1798399669			Jun 06 04:41:21 PM PDT 24	Jun 06 04:51:06 PM PDT 24	5610885500 ps
T28	/workspace/coverage/default/2.chip_sw_spi_device_pass_through.473568972			Jun 06 04:27:51 PM PDT 24	Jun 06 04:44:59 PM PDT 24	7454284974 ps
T324	/workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.105270167			Jun 06 04:37:21 PM PDT 24	Jun 06 04:42:15 PM PDT 24	2635509624 ps
T925	/workspace/coverage/default/2.chip_sw_clkmgr_off_peri.3339757872			Jun 06 04:34:56 PM PDT 24	Jun 06 05:01:04 PM PDT 24	9979588438 ps
T218	/workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.2365746175			Jun 06 04:26:36 PM PDT 24	Jun 06 04:47:46 PM PDT 24	9052897108 ps
T926	/workspace/coverage/default/0.chip_sw_clkmgr_jitter.3381397420			Jun 06 04:14:10 PM PDT 24	Jun 06 04:17:45 PM PDT 24	2366994371 ps
T225	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.899888093			Jun 06 04:10:24 PM PDT 24	Jun 06 04:29:27 PM PDT 24	7884260832 ps
T455	/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.2304907060			Jun 06 04:46:22 PM PDT 24	Jun 06 04:53:45 PM PDT 24	3733540108 ps
T927	/workspace/coverage/default/1.chip_sw_rstmgr_smoketest.2488055169			Jun 06 04:27:05 PM PDT 24	Jun 06 04:31:41 PM PDT 24	3068456772 ps
T83	/workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.375726638			Jun 06 04:14:45 PM PDT 24	Jun 06 07:36:43 PM PDT 24	59402339469 ps
T246	/workspace/coverage/default/2.chip_sw_otbn_mem_scramble.1309192860			Jun 06 04:31:34 PM PDT 24	Jun 06 04:39:03 PM PDT 24	3642816504 ps
T279	/workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.75532152			Jun 06 04:11:43 PM PDT 24	Jun 06 04:40:06 PM PDT 24	12509302190 ps
T280	/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.1555300987			Jun 06 04:39:17 PM PDT 24	Jun 06 05:43:15 PM PDT 24	16591544440 ps
T281	/workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.3182686797			Jun 06 04:12:26 PM PDT 24	Jun 06 04:18:39 PM PDT 24	7467360776 ps
T282	/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.2966839088			Jun 06 04:19:40 PM PDT 24	Jun 06 04:23:47 PM PDT 24	3049663556 ps
T283	/workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.188015018			Jun 06 04:18:54 PM PDT 24	Jun 06 04:25:57 PM PDT 24	7360842160 ps
T284	/workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.1750355418			Jun 06 04:31:56 PM PDT 24	Jun 06 04:38:55 PM PDT 24	5465747678 ps
T208	/workspace/coverage/default/0.chip_sw_power_idle_load.421856419			Jun 06 04:12:56 PM PDT 24	Jun 06 04:23:02 PM PDT 24	3953796124 ps
T285	/workspace/coverage/default/2.chip_sw_uart_smoketest.4048499405			Jun 06 04:37:14 PM PDT 24	Jun 06 04:40:59 PM PDT 24	2823887730 ps
T286	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.1372794960			Jun 06 04:24:31 PM PDT 24	Jun 06 04:34:57 PM PDT 24	5924298642 ps
T928	/workspace/coverage/default/2.chip_sw_kmac_mode_cshake.3232887819			Jun 06 04:34:22 PM PDT 24	Jun 06 04:37:45 PM PDT 24	2691868680 ps
T237	/workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.3528109925			Jun 06 04:18:05 PM PDT 24	Jun 06 05:50:59 PM PDT 24	48959205653 ps
T119	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.1345281876			Jun 06 04:14:45 PM PDT 24	Jun 06 04:32:13 PM PDT 24	6755786635 ps
T389	/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.1846852706			Jun 06 04:14:23 PM PDT 24	Jun 06 04:17:49 PM PDT 24	1918587910 ps
T929	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.3175168714			Jun 06 04:18:14 PM PDT 24	Jun 06 04:28:49 PM PDT 24	5091376350 ps
T930	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.757328476			Jun 06 04:13:29 PM PDT 24	Jun 06 04:25:06 PM PDT 24	3755205454 ps
T931	/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.2095100578			Jun 06 04:44:38 PM PDT 24	Jun 06 04:52:56 PM PDT 24	3951379304 ps
T731	/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.4012252974			Jun 06 04:47:39 PM PDT 24	Jun 06 04:55:22 PM PDT 24	4027454848 ps
T236	/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.2462361535			Jun 06 04:13:37 PM PDT 24	Jun 06 04:55:23 PM PDT 24	19737139115 ps
T3	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.2158104206			Jun 06 04:09:27 PM PDT 24	Jun 06 04:17:09 PM PDT 24	5741392222 ps
T425	/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.1898275831			Jun 06 04:20:34 PM PDT 24	Jun 06 05:35:57 PM PDT 24	14441584258 ps
T426	/workspace/coverage/default/1.chip_sw_example_flash.1345007580			Jun 06 04:20:11 PM PDT 24	Jun 06 04:24:02 PM PDT 24	3523166938 ps
T58	/workspace/coverage/default/0.rom_e2e_shutdown_exception_c.640755608			Jun 06 04:17:26 PM PDT 24	Jun 06 05:15:52 PM PDT 24	14121986150 ps
T427	/workspace/coverage/default/2.chip_sw_aes_enc.3146136516			Jun 06 04:30:16 PM PDT 24	Jun 06 04:33:40 PM PDT 24	3107023530 ps
T113	/workspace/coverage/default/0.chip_sw_power_sleep_load.3258621046			Jun 06 04:13:47 PM PDT 24	Jun 06 04:21:06 PM PDT 24	4447165000 ps
T428	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.3469917299			Jun 06 04:11:41 PM PDT 24	Jun 06 04:16:04 PM PDT 24	2885986978 ps
T249	/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.2126414927			Jun 06 04:10:35 PM PDT 24	Jun 06 04:23:12 PM PDT 24	5066164792 ps
T429	/workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.1241468713			Jun 06 04:35:56 PM PDT 24	Jun 06 04:42:56 PM PDT 24	6033153078 ps
T29	/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.2137163197			Jun 06 04:16:23 PM PDT 24	Jun 06 04:21:14 PM PDT 24	3036266676 ps
T224	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation.2194625522			Jun 06 04:33:10 PM PDT 24	Jun 06 05:03:04 PM PDT 24	9810304600 ps
T932	/workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.1378816665			Jun 06 04:23:58 PM PDT 24	Jun 06 04:32:52 PM PDT 24	3759070160 ps
T933	/workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.1976963775			Jun 06 04:29:46 PM PDT 24	Jun 06 04:42:36 PM PDT 24	5136389424 ps
T374	/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.1503869465			Jun 06 04:46:26 PM PDT 24	Jun 06 04:52:28 PM PDT 24	4669296600 ps
T209	/workspace/coverage/default/24.chip_sw_all_escalation_resets.689677246			Jun 06 04:40:51 PM PDT 24	Jun 06 04:50:39 PM PDT 24	4680882688 ps
T33	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.1215859921			Jun 06 04:10:24 PM PDT 24	Jun 06 04:17:08 PM PDT 24	3265158190 ps
T227	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.953153429			Jun 06 04:17:15 PM PDT 24	Jun 06 04:41:19 PM PDT 24	7351121200 ps
T375	/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.3609810843			Jun 06 04:39:01 PM PDT 24	Jun 06 04:45:55 PM PDT 24	3289255528 ps
T159	/workspace/coverage/default/42.chip_sw_all_escalation_resets.374316452			Jun 06 04:42:34 PM PDT 24	Jun 06 04:51:16 PM PDT 24	4608629610 ps
T247	/workspace/coverage/default/2.chip_sw_data_integrity_escalation.521593634			Jun 06 04:37:33 PM PDT 24	Jun 06 04:45:59 PM PDT 24	4508831716 ps
T382	/workspace/coverage/default/2.chip_sw_example_rom.3828157331			Jun 06 04:26:15 PM PDT 24	Jun 06 04:28:26 PM PDT 24	2448128204 ps
T383	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.2643515675			Jun 06 04:27:54 PM PDT 24	Jun 06 04:40:12 PM PDT 24	4627843886 ps
T150	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.3211293575			Jun 06 04:19:18 PM PDT 24	Jun 06 05:14:55 PM PDT 24	16860768984 ps
T259	/workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3200880104			Jun 06 04:24:02 PM PDT 24	Jun 06 04:31:27 PM PDT 24	3836035784 ps
T325	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.3521945979			Jun 06 04:09:40 PM PDT 24	Jun 06 04:22:01 PM PDT 24	4212595072 ps
T934	/workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.1891704122			Jun 06 04:30:47 PM PDT 24	Jun 06 04:35:35 PM PDT 24	3380272608 ps
T935	/workspace/coverage/default/1.chip_sw_rstmgr_sw_req.2326607372			Jun 06 04:19:06 PM PDT 24	Jun 06 04:26:21 PM PDT 24	3778664198 ps
T460	/workspace/coverage/default/1.chip_sw_flash_crash_alert.1889202748			Jun 06 04:25:17 PM PDT 24	Jun 06 04:38:11 PM PDT 24	6503164208 ps
T936	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.3780607459			Jun 06 04:30:18 PM PDT 24	Jun 06 04:42:23 PM PDT 24	7701128160 ps
T77	/workspace/coverage/default/2.chip_tap_straps_rma.728679373			Jun 06 04:35:41 PM PDT 24	Jun 06 04:38:45 PM PDT 24	2711359757 ps
T354	/workspace/coverage/default/3.chip_sw_uart_tx_rx.2891214921			Jun 06 04:37:19 PM PDT 24	Jun 06 04:50:12 PM PDT 24	4498588854 ps
T937	/workspace/coverage/default/2.chip_sw_example_manufacturer.1716215504			Jun 06 04:27:37 PM PDT 24	Jun 06 04:31:05 PM PDT 24	2671329722 ps
T342	/workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.858454079			Jun 06 04:16:05 PM PDT 24	Jun 06 04:27:17 PM PDT 24	3597609704 ps
T313	/workspace/coverage/default/22.chip_sw_all_escalation_resets.4149260275			Jun 06 04:41:51 PM PDT 24	Jun 06 04:53:03 PM PDT 24	4961609316 ps
T260	/workspace/coverage/default/0.rom_e2e_jtag_debug_dev.3219078667			Jun 06 04:19:22 PM PDT 24	Jun 06 05:04:58 PM PDT 24	13275175053 ps
T938	/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1959207251			Jun 06 04:14:42 PM PDT 24	Jun 06 04:31:41 PM PDT 24	7288785026 ps
T386	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.2748719830			Jun 06 04:17:32 PM PDT 24	Jun 06 06:08:56 PM PDT 24	22899317338 ps
T939	/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.2764596893			Jun 06 04:32:38 PM PDT 24	Jun 06 04:42:31 PM PDT 24	5274888688 ps
T10	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.2991983356			Jun 06 04:28:30 PM PDT 24	Jun 06 04:52:50 PM PDT 24	21945771930 ps
T152	/workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.3044570031			Jun 06 04:28:13 PM PDT 24	Jun 06 07:16:06 PM PDT 24	59356989180 ps
T132	/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.1257398807			Jun 06 04:38:30 PM PDT 24	Jun 06 04:53:45 PM PDT 24	7032397298 ps
T368	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.997667955			Jun 06 04:19:14 PM PDT 24	Jun 06 04:43:39 PM PDT 24	13436914289 ps
T358	/workspace/coverage/default/30.chip_sw_all_escalation_resets.97614499			Jun 06 04:43:11 PM PDT 24	Jun 06 04:53:10 PM PDT 24	6108519768 ps
T940	/workspace/coverage/default/1.chip_tap_straps_prod.802449205			Jun 06 04:23:47 PM PDT 24	Jun 06 04:26:33 PM PDT 24	2656569014 ps
T734	/workspace/coverage/default/72.chip_sw_all_escalation_resets.2647625431			Jun 06 04:45:04 PM PDT 24	Jun 06 04:56:28 PM PDT 24	5186375316 ps
T172	/workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.1406483684			Jun 06 04:10:33 PM PDT 24	Jun 06 04:12:46 PM PDT 24	2514375476 ps
T162	/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.1578512188			Jun 06 04:41:43 PM PDT 24	Jun 06 04:49:27 PM PDT 24	4285978168 ps
T114	/workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.766208984			Jun 06 04:20:42 PM PDT 24	Jun 06 04:29:38 PM PDT 24	18711244224 ps
T217	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.718696395			Jun 06 04:09:56 PM PDT 24	Jun 06 04:22:46 PM PDT 24	4334764264 ps
T941	/workspace/coverage/default/1.chip_sw_kmac_mode_cshake.3449949413			Jun 06 04:23:38 PM PDT 24	Jun 06 04:29:06 PM PDT 24	2613318080 ps
T211	/workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.3548807035			Jun 06 04:14:23 PM PDT 24	Jun 06 04:20:30 PM PDT 24	3686438442 ps
T942	/workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.289299531			Jun 06 04:38:08 PM PDT 24	Jun 06 04:41:55 PM PDT 24	2826207656 ps
T314	/workspace/coverage/default/39.chip_sw_all_escalation_resets.365003873			Jun 06 04:41:51 PM PDT 24	Jun 06 04:57:27 PM PDT 24	6373846320 ps
T129	/workspace/coverage/default/0.chip_sw_edn_auto_mode.673297618			Jun 06 04:11:07 PM PDT 24	Jun 06 04:24:42 PM PDT 24	4356581420 ps
T315	/workspace/coverage/default/3.chip_sw_all_escalation_resets.3785710224			Jun 06 04:42:41 PM PDT 24	Jun 06 04:50:58 PM PDT 24	6062223216 ps
T210	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.831703317			Jun 06 04:31:54 PM PDT 24	Jun 06 05:02:09 PM PDT 24	7744197032 ps
T943	/workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.1318545918			Jun 06 04:28:21 PM PDT 24	Jun 06 04:32:02 PM PDT 24	2644658695 ps
T944	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.1481892775			Jun 06 04:29:19 PM PDT 24	Jun 06 04:36:04 PM PDT 24	4654877280 ps
T814	/workspace/coverage/default/21.chip_sw_all_escalation_resets.684804625			Jun 06 04:42:29 PM PDT 24	Jun 06 04:51:54 PM PDT 24	5341481600 ps
T945	/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.3598206724			Jun 06 04:28:37 PM PDT 24	Jun 06 04:54:58 PM PDT 24	8750092432 ps
T732	/workspace/coverage/default/49.chip_sw_all_escalation_resets.554413607			Jun 06 04:43:37 PM PDT 24	Jun 06 04:51:14 PM PDT 24	5312402170 ps
T120	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3073890283			Jun 06 04:27:46 PM PDT 24	Jun 06 05:05:31 PM PDT 24	11117282310 ps
T736	/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.681618396			Jun 06 04:46:02 PM PDT 24	Jun 06 04:51:02 PM PDT 24	3621048664 ps
T326	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2929568374			Jun 06 04:11:23 PM PDT 24	Jun 06 04:43:12 PM PDT 24	13809194365 ps
T270	/workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.3259839670			Jun 06 04:24:59 PM PDT 24	Jun 06 04:32:52 PM PDT 24	9327841749 ps
T733	/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.2932819745			Jun 06 04:43:27 PM PDT 24	Jun 06 04:48:30 PM PDT 24	3637596216 ps
T250	/workspace/coverage/default/12.chip_sw_all_escalation_resets.1766112505			Jun 06 04:41:43 PM PDT 24	Jun 06 04:53:19 PM PDT 24	5087450340 ps
T48	/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.1024377614			Jun 06 04:27:26 PM PDT 24	Jun 06 04:31:22 PM PDT 24	2236738030 ps
T946	/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.4029797795			Jun 06 04:36:59 PM PDT 24	Jun 06 04:43:42 PM PDT 24	7975454924 ps
T353	/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.4064379159			Jun 06 04:11:04 PM PDT 24	Jun 06 04:16:04 PM PDT 24	2904965366 ps
T88	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.4020826259			Jun 06 04:31:37 PM PDT 24	Jun 06 04:48:15 PM PDT 24	9348327676 ps
T144	/workspace/coverage/default/0.chip_sw_sensor_ctrl_status.3879549288			Jun 06 04:13:00 PM PDT 24	Jun 06 04:18:18 PM PDT 24	3468856859 ps
T452	/workspace/coverage/default/2.chip_sw_kmac_app_rom.1775980944			Jun 06 04:32:06 PM PDT 24	Jun 06 04:37:13 PM PDT 24	2763366672 ps
T16	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.655460911			Jun 06 04:34:12 PM PDT 24	Jun 06 05:10:25 PM PDT 24	26968941148 ps
T947	/workspace/coverage/default/1.chip_sw_csrng_smoketest.3377892935			Jun 06 04:27:21 PM PDT 24	Jun 06 04:31:37 PM PDT 24	2766087176 ps
T173	/workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.194058271			Jun 06 04:28:49 PM PDT 24	Jun 06 05:07:01 PM PDT 24	29245287875 ps
T470	/workspace/coverage/default/0.chip_sw_edn_kat.3000745487			Jun 06 04:12:53 PM PDT 24	Jun 06 04:22:44 PM PDT 24	3774745216 ps
T799	/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.4024246391			Jun 06 04:41:03 PM PDT 24	Jun 06 04:47:17 PM PDT 24	3096121740 ps
T268	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.3218065322			Jun 06 04:19:58 PM PDT 24	Jun 06 05:12:02 PM PDT 24	13793743471 ps
T65	/workspace/coverage/default/0.chip_sw_alert_test.3376956006			Jun 06 04:12:42 PM PDT 24	Jun 06 04:18:50 PM PDT 24	3691900360 ps