| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins | 2 | 0 | 2 | 100.00 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| falling | 15833 | 1 | T82 | 2 | T86 | 5 | T472 | 35 | ||||
| rising | 15852 | 1 | T82 | 2 | T86 | 5 | T472 | 35 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| auto[0] | 1429024 | 1 | T80 | 848 | T81 | 51 | T82 | 108 | ||||
| auto[1] | 16650 | 1 | T82 | 2 | T86 | 5 | T472 | 35 |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |