Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	439	1			T449	1		T574	1		T424	1
all_values[1]	494	1			T559	2		T421	1		T569	1
all_values[2]	493	1			T568	1		T449	1		T508	1
all_values[3]	462	1			T568	1		T508	2		T574	2
all_values[4]	479	1			T421	1		T571	1		T574	1
all_values[5]	482	1			T568	1		T571	1		T574	1
all_values[6]	504	1			T568	3		T449	1		T421	1
all_values[7]	439	1			T568	1		T569	1		T574	1
all_values[8]	461	1			T878	1		T569	1		T435	1
all_values[9]	439	1			T508	1		T424	1		T726	1
all_values[10]	468	1			T568	1		T449	1		T508	1
all_values[11]	479	1			T574	1		T868	1		T647	1
all_values[12]	445	1			T559	1		T449	1		T569	1
all_values[13]	477	1			T421	1		T508	2		T424	1
all_values[14]	425	1			T559	1		T568	1		T569	2
all_values[15]	469	1			T878	1		T569	2		T508	1
all_values[16]	462	1			T568	2		T421	1		T569	2
all_values[17]	488	1			T559	1		T569	1		T574	1
all_values[18]	478	1			T568	2		T421	1		T574	1
all_values[19]	451	1			T559	1		T568	3		T569	1
all_values[20]	435	1			T559	1		T421	1		T569	1
all_values[21]	482	1			T508	2		T574	1		T647	2
all_values[22]	490	1			T568	1		T421	1		T571	1
all_values[23]	481	1			T559	1		T421	2		T571	1
all_values[24]	516	1			T421	1		T574	1		T424	1
all_values[25]	464	1			T568	1		T508	1		T574	2
all_values[26]	479	1			T559	1		T568	1		T569	1
all_values[27]	483	1			T559	1		T574	1		T726	1
all_values[28]	481	1			T559	1		T421	1		T569	1
all_values[29]	446	1			T568	1		T424	1		T868	1
all_values[30]	461	1			T559	1		T574	1		T726	1
all_values[31]	487	1			T568	1		T569	3		T571	2
all_values[32]	458	1			T559	1		T574	1		T868	1
all_values[33]	462	1			T559	1		T568	1		T569	1
all_values[34]	468	1			T568	2		T571	1		T424	1
all_values[35]	476	1			T421	1		T571	1		T424	1
all_values[36]	489	1			T878	1		T569	2		T571	1
all_values[37]	507	1			T868	2		T858	2		T727	1
all_values[38]	474	1			T568	1		T449	1		T421	1
all_values[39]	449	1			T568	2		T574	2		T424	1
all_values[40]	500	1			T568	2		T424	1		T726	1
all_values[41]	492	1			T567	1		T868	3		T858	2
all_values[42]	431	1			T421	1		T508	1		T574	1
all_values[43]	499	1			T568	1		T508	1		T574	1
all_values[44]	441	1			T569	1		T868	1		T647	1
all_values[45]	469	1			T568	1		T449	1		T868	4
all_values[46]	442	1			T571	1		T424	1		T647	1
all_values[47]	497	1			T568	1		T449	1		T508	1
all_values[48]	505	1			T568	1		T449	3		T571	1
all_values[49]	472	1			T559	1		T569	2		T574	1