Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3400	1			T563	4		T573	1		T486	1
all_values[1]	3336	1			T563	4		T486	1		T568	2
all_values[2]	3377	1			T563	4		T573	1		T486	2
all_values[3]	3401	1			T563	4		T573	1		T486	3
all_values[4]	3386	1			T563	2		T573	3		T486	4
all_values[5]	3378	1			T561	2		T563	3		T486	3
all_values[6]	3444	1			T563	4		T568	6		T421	4
all_values[7]	3454	1			T561	2		T563	2		T573	2
all_values[8]	3393	1			T561	1		T563	2		T573	2
all_values[9]	3344	1			T561	2		T563	4		T486	2
all_values[10]	3349	1			T563	6		T573	1		T486	3
all_values[11]	3430	1			T563	3		T486	1		T568	3
all_values[12]	3329	1			T561	4		T563	2		T486	3
all_values[13]	3289	1			T563	4		T573	1		T486	1
all_values[14]	3382	1			T561	2		T563	2		T486	5
all_values[15]	3394	1			T561	3		T563	2		T568	1
all_values[16]	3430	1			T561	2		T563	1		T486	1
all_values[17]	3357	1			T563	3		T573	1		T568	1
all_values[18]	3371	1			T561	1		T563	5		T486	1
all_values[19]	3356	1			T563	1		T486	2		T421	8
all_values[20]	3385	1			T561	1		T563	3		T573	1
all_values[21]	3368	1			T561	3		T563	1		T486	2
all_values[22]	3376	1			T561	2		T573	2		T486	5
all_values[23]	3420	1			T563	1		T486	1		T568	4
all_values[24]	3429	1			T563	5		T573	2		T486	2
all_values[25]	3457	1			T563	5		T486	2		T568	1
all_values[26]	3493	1			T563	3		T486	1		T568	4
all_values[27]	3365	1			T561	1		T563	5		T568	4
all_values[28]	3328	1			T563	3		T573	4		T568	1
all_values[29]	3409	1			T561	1		T563	5		T573	2
all_values[30]	3433	1			T563	3		T573	1		T486	1
all_values[31]	3376	1			T563	7		T573	1		T486	1
all_values[32]	3439	1			T561	1		T563	3		T573	1
all_values[33]	3392	1			T561	1		T563	4		T486	1
all_values[34]	3397	1			T561	1		T563	1		T421	11
all_values[35]	3410	1			T563	12		T486	1		T568	5
all_values[36]	3454	1			T561	1		T563	2		T573	1
all_values[37]	3402	1			T563	1		T486	1		T568	1
all_values[38]	3358	1			T563	5		T573	1		T486	1
all_values[39]	3314	1			T561	1		T563	3		T486	2
all_values[40]	3383	1			T561	1		T563	4		T486	2
all_values[41]	3483	1			T561	2		T563	1		T486	1
all_values[42]	3374	1			T561	1		T563	4		T573	1
all_values[43]	3416	1			T563	3		T573	2		T568	1
all_values[44]	3353	1			T563	1		T568	2		T421	3
all_values[45]	3371	1			T563	1		T573	1		T486	1
all_values[46]	3318	1			T561	2		T563	2		T568	1
all_values[47]	3256	1			T561	3		T563	1		T573	1
all_values[48]	3477	1			T563	2		T573	4		T486	2
all_values[49]	3294	1			T561	1		T563	4		T573	2
all_values[50]	3467	1			T563	2		T573	1		T486	3
all_values[51]	3439	1			T563	1		T486	2		T568	5
all_values[52]	3374	1			T563	6		T573	1		T486	2
all_values[53]	3346	1			T561	1		T563	2		T486	1
all_values[54]	3339	1			T563	2		T486	3		T568	2
all_values[55]	3385	1			T563	2		T486	2		T568	2
all_values[56]	3378	1			T561	1		T563	3		T486	2
all_values[57]	3340	1			T563	5		T486	2		T568	2
all_values[58]	3464	1			T561	1		T563	2		T486	2
all_values[59]	3368	1			T563	2		T573	1		T568	1
all_values[60]	3325	1			T561	1		T563	2		T486	3
all_values[61]	3387	1			T563	1		T486	1		T568	4
all_values[62]	3365	1			T563	3		T573	1		T421	2
all_values[63]	3331	1			T561	1		T563	4		T573	1