Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.flash_ctrl__prim_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	152284	1			T73	118		T74	1		T78	19
values[2]	4237	1			T73	1		T262	3		T557	3
values[3]	1974	1			T836	1		T485	1		T553	1
values[4]	1373	1			T836	1		T553	1		T555	1
values[5]	973	1			T836	1		T553	1		T555	1
values[6]	730	1			T836	1		T553	1		T555	1
values[7]	607	1			T836	1		T553	1		T555	1
values[8]	602	1			T836	1		T553	1		T555	1
values[9]	549	1			T836	1		T553	1		T555	1
values[10]	521	1			T836	1		T553	2		T555	1
values[11]	531	1			T836	1		T553	1		T555	1
values[12]	505	1			T836	1		T553	1		T555	1
values[13]	463	1			T836	1		T553	1		T555	1
values[14]	459	1			T836	1		T553	1		T555	1
values[15]	429	1			T836	1		T553	1		T555	1
values[16]	321	1			T836	1		T553	1		T555	1
values[17]	291	1			T836	1		T553	1		T555	1
values[18]	244	1			T836	1		T553	1		T555	1
values[19]	261	1			T836	1		T553	1		T555	1
values[20]	238	1			T836	1		T553	1		T555	1
values[21]	201	1			T836	1		T553	1		T555	1
values[22]	204	1			T836	1		T553	1		T555	1
values[23]	213	1			T836	1		T553	1		T555	1
values[24]	168	1			T836	1		T553	1		T555	1
values[25]	179	1			T836	1		T553	1		T555	1
values[26]	184	1			T836	1		T553	1		T555	1
values[27]	148	1			T836	1		T553	1		T555	1
values[28]	149	1			T836	1		T553	1		T555	1
values[29]	127	1			T836	1		T553	1		T555	1
values[30]	144	1			T836	1		T553	1		T555	1
values[31]	134	1			T836	1		T553	1		T555	1
values[32]	112	1			T836	1		T553	1		T555	1
values[33]	121	1			T836	1		T553	1		T555	1
values[34]	104	1			T836	1		T553	1		T555	1
values[35]	115	1			T836	1		T553	1		T555	1
values[36]	121	1			T836	1		T553	1		T555	1
values[37]	127	1			T836	1		T553	1		T555	1
values[38]	99	1			T836	1		T553	1		T555	1
values[39]	98	1			T836	1		T553	1		T555	1
values[40]	103	1			T836	1		T553	1		T555	1
values[41]	95	1			T836	1		T553	1		T555	1
values[42]	82	1			T836	1		T553	1		T555	1
values[43]	86	1			T836	1		T553	1		T555	1
values[44]	79	1			T836	1		T553	1		T555	1
values[45]	71	1			T836	1		T553	1		T555	1
values[46]	77	1			T836	1		T553	1		T555	1
values[47]	58	1			T836	1		T553	1		T555	1
values[48]	69	1			T836	1		T553	1		T555	1
values[49]	56	1			T836	1		T553	1		T555	1
values[50]	56	1			T836	1		T553	1		T555	1
values[51]	65	1			T836	1		T553	1		T555	1
values[52]	66	1			T836	1		T553	1		T555	1
values[53]	71	1			T836	1		T553	2		T555	1
values[54]	77	1			T836	1		T553	1		T555	1
values[55]	63	1			T836	1		T553	1		T555	1
values[56]	64	1			T836	1		T553	1		T555	1
values[57]	72	1			T836	1		T553	1		T555	1
values[58]	58	1			T836	1		T553	1		T555	1
values[59]	66	1			T836	1		T553	1		T555	1
values[60]	60	1			T836	1		T553	1		T555	1
values[61]	58	1			T836	1		T553	1		T555	1
values[62]	69	1			T836	1		T553	1		T555	1
values[63]	67	1			T836	1		T553	1		T555	1
values[64]	58	1			T836	1		T553	1		T555	1
values[65]	71	1			T836	1		T553	1		T555	1
values[66]	60	1			T836	1		T553	1		T555	1
values[67]	54	1			T836	1		T553	1		T555	1
values[68]	53	1			T836	1		T553	1		T555	1
values[69]	54	1			T836	1		T553	1		T555	1
values[70]	66	1			T836	1		T553	1		T555	1
values[71]	68	1			T836	1		T553	1		T555	1
values[72]	65	1			T836	1		T553	1		T555	1
values[73]	65	1			T836	1		T553	1		T555	1
values[74]	61	1			T836	1		T553	1		T555	1
values[75]	49	1			T836	1		T553	1		T555	1
values[76]	67	1			T836	1		T553	1		T555	1
values[77]	79	1			T836	1		T553	1		T555	1
values[78]	72	1			T836	1		T553	1		T555	1
values[79]	74	1			T836	1		T553	1		T555	1
values[80]	79	1			T836	1		T553	1		T555	1
values[81]	87	1			T836	1		T553	1		T555	1
values[82]	82	1			T836	1		T553	1		T555	1
values[83]	81	1			T836	1		T553	1		T555	2
values[84]	89	1			T836	1		T553	1		T555	1
values[85]	87	1			T836	1		T553	1		T555	1
values[86]	75	1			T836	1		T553	1		T555	1
values[87]	78	1			T836	1		T553	1		T555	1
values[88]	99	1			T836	1		T553	1		T555	1
values[89]	93	1			T836	1		T553	1		T555	1
values[90]	73	1			T836	1		T553	1		T555	1
values[91]	87	1			T836	1		T553	1		T555	1
values[92]	97	1			T836	1		T553	1		T555	1
values[93]	97	1			T836	1		T553	1		T555	1
values[94]	81	1			T836	1		T553	1		T555	1
values[95]	68	1			T836	1		T553	1		T555	1
values[96]	93	1			T836	1		T553	1		T555	1
values[97]	91	1			T836	1		T553	1		T555	1
values[98]	71	1			T836	2		T553	1		T555	1
values[99]	95	1			T836	2		T553	2		T555	1
values[100]	86	1			T836	2		T553	2		T555	1
values[101]	87	1			T836	3		T553	4		T555	1
values[102]	90	1			T836	1		T553	2		T555	3
values[103]	96	1			T836	3		T553	2		T555	3
values[104]	106	1			T836	3		T553	2		T555	2
values[105]	84	1			T836	2		T553	2		T555	3
values[106]	95	1			T836	3		T553	4		T555	3
values[107]	90	1			T836	2		T553	3		T555	1
values[108]	98	1			T836	3		T553	3		T555	2
values[109]	90	1			T836	3		T553	1		T555	2
values[110]	84	1			T836	2		T553	1		T555	1
values[111]	97	1			T836	3		T553	1		T555	1
values[112]	98	1			T836	3		T553	2		T555	1
values[113]	110	1			T836	1		T553	3		T555	1
values[114]	109	1			T836	4		T553	1		T555	2
values[115]	130	1			T836	3		T553	3		T555	2
values[116]	125	1			T836	1		T553	1		T555	2
values[117]	141	1			T836	2		T553	1		T555	1
values[118]	136	1			T836	1		T553	2		T555	1
values[119]	114	1			T836	2		T553	1		T555	3
values[120]	111	1			T836	1		T553	3		T555	2
values[121]	100	1			T836	1		T553	2		T555	1
values[122]	116	1			T836	1		T553	1		T555	1
values[123]	170	1			T836	1		T553	1		T555	1
values[124]	275	1			T836	2		T553	1		T555	1
values[125]	607	1			T836	2		T553	2		T555	4
values[126]	972	1			T836	15		T553	12		T555	16
values[127]	2778	1			T836	113		T553	112		T555	138
values[128]	5075	1			T836	168		T553	262		T555	286