Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.99	95.52	94.01	95.51		94.89	96.47	99.55

Total tests in report: 2887

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
39.95	39.95	44.39	44.39	42.68	42.68	32.56	32.56			57.36	57.36	62.59	62.59	0.14	0.14	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.2089367628
48.72	8.77	49.56	5.17	55.77	13.08	32.80	0.24			67.53	10.18	85.66	23.08	0.99	0.85	/workspace/coverage/cover_reg_top/9.chip_csr_rw.310849857
55.24	6.52	62.89	13.33	59.60	3.84	40.97	8.17			68.84	1.31	85.66	0.00	13.46	12.48	/workspace/coverage/cover_reg_top/60.xbar_stress_all_with_rand_reset.3159415145
61.71	6.47	76.53	13.64	68.76	9.16	44.50	3.53			81.34	12.51	85.66	0.00	13.46	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_0.1380014618
66.75	5.04	76.53	0.00	68.93	0.17	44.50	0.00			81.34	0.00	85.66	0.00	43.53	30.07	/workspace/coverage/cover_reg_top/96.xbar_access_same_device_slow_rsp.2480090410
70.05	3.31	82.57	6.05	73.24	4.31	48.46	3.96			83.36	2.02	89.16	3.50	43.53	0.00	/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.3324711190
72.94	2.88	82.57	0.00	73.24	0.00	48.46	0.00			83.36	0.00	89.16	0.00	60.83	17.30	/workspace/coverage/cover_reg_top/78.xbar_access_same_device_slow_rsp.1464842320
75.52	2.59	82.58	0.01	73.25	0.01	63.78	15.32			83.37	0.01	89.34	0.17	60.83	0.00	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation.1229128315
77.46	1.94	84.85	2.28	76.00	2.75	68.10	4.32			85.30	1.92	89.69	0.35	60.84	0.01	/workspace/coverage/default/2.rom_e2e_shutdown_exception_c.2046587789
79.26	1.79	84.85	0.00	76.36	0.36	68.10	0.00			85.38	0.08	89.69	0.00	71.15	10.32	/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.335325242
80.83	1.58	85.13	0.27	76.52	0.16	76.39	8.29			85.56	0.18	90.21	0.52	71.20	0.05	/workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.3633270741
82.10	1.27	86.66	1.54	79.25	2.73	76.54	0.15			88.06	2.51	90.91	0.70	71.20	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.701229475
83.17	1.07	86.66	0.00	79.70	0.45	76.54	0.00			88.14	0.08	90.91	0.00	77.08	5.87	/workspace/coverage/cover_reg_top/77.xbar_access_same_device_slow_rsp.799124156
84.15	0.98	86.83	0.17	79.90	0.19	79.38	2.84			88.18	0.03	91.08	0.17	79.52	2.44	/workspace/coverage/default/1.chip_sw_alert_test.3117382751
85.09	0.94	86.83	0.00	79.90	0.00	79.38	0.00			88.18	0.00	91.08	0.00	85.17	5.65	/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.1439325180
85.90	0.81	87.54	0.70	80.05	0.15	79.39	0.01			88.32	0.15	94.93	3.85	85.17	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.3668086241
86.64	0.74	88.97	1.43	81.07	1.02	80.74	1.35			88.98	0.66	94.93	0.00	85.17	0.00	/workspace/coverage/default/1.chip_jtag_csr_rw.3784074040
87.34	0.69	90.22	1.25	82.10	1.03	81.41	0.68			90.17	1.19	94.93	0.00	85.17	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_20.2123857129
87.95	0.61	90.23	0.01	85.12	3.02	81.62	0.20			90.20	0.02	94.93	0.00	85.58	0.41	/workspace/coverage/cover_reg_top/8.chip_tl_errors.2091890115
88.52	0.57	90.23	0.00	85.12	0.00	85.06	3.45			90.20	0.00	94.93	0.00	85.58	0.00	/workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.2487297906
89.06	0.54	90.23	0.00	85.12	0.00	85.06	0.00			90.20	0.00	94.93	0.00	88.83	3.24	/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.1823112897
89.59	0.53	91.12	0.89	86.07	0.96	85.61	0.55			91.01	0.81	94.93	0.00	88.83	0.00	/workspace/coverage/default/0.chip_sw_gpio_smoketest.2775532365
90.09	0.50	92.03	0.91	86.96	0.89	86.09	0.48			91.72	0.71	94.93	0.00	88.83	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.736625303
90.57	0.48	92.56	0.53	88.05	1.09	86.32	0.23			92.74	1.01	94.93	0.00	88.83	0.00	/workspace/coverage/default/0.chip_jtag_csr_rw.1748904635
91.04	0.47	92.56	0.00	88.05	0.00	86.32	0.00			92.74	0.00	94.93	0.00	91.62	2.80	/workspace/coverage/cover_reg_top/92.xbar_access_same_device_slow_rsp.3596146920
91.50	0.46	92.57	0.01	88.11	0.06	86.83	0.51			92.75	0.01	94.93	0.00	93.81	2.19	/workspace/coverage/cover_reg_top/15.xbar_stress_all_with_error.3497384313
91.85	0.35	92.57	0.00	88.19	0.08	86.83	0.00			92.76	0.02	94.93	0.00	95.82	2.01	/workspace/coverage/cover_reg_top/58.xbar_stress_all.128118815
92.19	0.34	93.11	0.54	88.64	0.45	87.41	0.57			93.22	0.46	94.93	0.00	95.82	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_10.1799854801
92.51	0.32	93.26	0.15	88.71	0.07	88.89	1.48			93.28	0.06	94.93	0.00	95.96	0.14	/workspace/coverage/default/59.chip_sw_all_escalation_resets.1616265928
92.80	0.30	93.62	0.36	90.05	1.34	88.95	0.06			93.30	0.02	94.93	0.00	95.97	0.01	/workspace/coverage/cover_reg_top/5.chip_same_csr_outstanding.1421986531
93.05	0.24	93.63	0.01	90.06	0.01	90.39	1.44			93.30	0.00	94.93	0.00	95.97	0.00	/workspace/coverage/default/1.chip_sw_edn_auto_mode.3745041466
93.25	0.21	93.63	0.00	90.09	0.04	90.39	0.00			93.31	0.02	94.93	0.00	97.16	1.19	/workspace/coverage/cover_reg_top/65.xbar_random_large_delays.3542089468
93.45	0.20	93.63	0.00	90.09	0.00	91.58	1.19			93.31	0.00	94.93	0.00	97.16	0.00	/workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.2711637566
93.61	0.16	93.63	0.00	90.23	0.14	91.58	0.00			93.31	0.00	94.93	0.00	97.97	0.81	/workspace/coverage/cover_reg_top/61.xbar_stress_all_with_rand_reset.4157079830
93.75	0.15	93.80	0.17	90.37	0.14	91.68	0.10			93.44	0.12	95.28	0.35	97.97	0.00	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.3745883368
93.89	0.13	94.00	0.20	90.58	0.20	91.98	0.31			93.52	0.09	95.28	0.00	97.97	0.00	/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.1864436594
94.01	0.13	94.23	0.23	90.77	0.19	92.00	0.02			93.84	0.32	95.28	0.00	97.97	0.00	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.3051779542
94.13	0.12	94.28	0.05	91.07	0.30	92.03	0.02			94.18	0.34	95.28	0.00	97.97	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.3134651772
94.24	0.11	94.28	0.00	91.07	0.00	92.66	0.64			94.18	0.00	95.28	0.00	97.97	0.00	/workspace/coverage/default/0.chip_sw_alert_handler_entropy.2982281535
94.34	0.10	94.28	0.00	91.68	0.61	92.66	0.00			94.18	0.00	95.28	0.00	97.97	0.00	/workspace/coverage/cover_reg_top/7.chip_tl_errors.2657491463
94.43	0.09	94.32	0.04	91.81	0.13	92.77	0.10			94.28	0.10	95.45	0.17	97.97	0.00	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.3195488611
94.52	0.08	94.39	0.07	91.92	0.11	92.99	0.22			94.38	0.10	95.45	0.00	97.97	0.00	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.2530991905
94.60	0.08	94.39	0.00	91.92	0.00	93.47	0.48			94.38	0.00	95.45	0.00	97.97	0.00	/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.3654586120
94.66	0.06	94.44	0.04	92.12	0.20	93.52	0.05			94.44	0.06	95.45	0.00	97.97	0.00	/workspace/coverage/cover_reg_top/13.chip_csr_rw.2305914538
94.72	0.06	94.44	0.00	92.20	0.08	93.52	0.00			94.44	0.00	95.45	0.00	98.25	0.28	/workspace/coverage/cover_reg_top/22.xbar_stress_all_with_rand_reset.1750641538
94.77	0.05	94.44	0.00	92.20	0.00	93.85	0.32			94.44	0.00	95.45	0.00	98.25	0.00	/workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.2373115497
94.81	0.04	94.44	0.00	92.20	0.00	94.11	0.26			94.44	0.00	95.45	0.00	98.25	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.115332545
94.86	0.04	94.44	0.00	92.20	0.00	94.37	0.26			94.44	0.00	95.45	0.00	98.25	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.1818921427
94.90	0.04	94.45	0.01	92.21	0.01	94.37	0.00			94.47	0.02	95.63	0.17	98.26	0.01	/workspace/coverage/default/26.chip_sw_all_escalation_resets.2623742886
94.94	0.04	94.47	0.03	92.21	0.01	94.37	0.01			94.47	0.01	95.80	0.17	98.27	0.01	/workspace/coverage/default/39.chip_sw_all_escalation_resets.3553991241
94.97	0.04	94.51	0.04	92.32	0.11	94.37	0.00			94.55	0.07	95.80	0.00	98.27	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_retention.3158195405
95.01	0.04	94.52	0.01	92.33	0.01	94.38	0.01			94.55	0.01	95.98	0.17	98.28	0.01	/workspace/coverage/default/10.chip_sw_all_escalation_resets.1617964211
95.04	0.04	94.52	0.01	92.34	0.01	94.39	0.01			94.56	0.01	96.15	0.17	98.30	0.01	/workspace/coverage/default/15.chip_sw_all_escalation_resets.111611735
95.08	0.04	94.53	0.01	92.36	0.01	94.39	0.00			94.57	0.01	96.33	0.17	98.31	0.01	/workspace/coverage/default/4.chip_sw_all_escalation_resets.2903115852
95.11	0.03	94.53	0.01	92.46	0.10	94.39	0.00			94.67	0.10	96.33	0.00	98.31	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.3482488088
95.15	0.03	94.53	0.00	92.50	0.04	94.39	0.00			94.68	0.02	96.33	0.00	98.45	0.14	/workspace/coverage/cover_reg_top/77.xbar_stress_all_with_rand_reset.1162072440
95.18	0.03	94.60	0.07	92.50	0.00	94.50	0.11			94.69	0.01	96.33	0.00	98.45	0.00	/workspace/coverage/default/2.chip_tap_straps_testunlock0.3896324276
95.21	0.03	94.60	0.00	92.67	0.17	94.50	0.00			94.69	0.00	96.33	0.00	98.46	0.01	/workspace/coverage/cover_reg_top/26.chip_tl_errors.2469605499
95.24	0.03	94.60	0.00	92.67	0.00	94.50	0.01			94.69	0.00	96.50	0.17	98.46	0.00	/workspace/coverage/default/1.chip_sw_data_integrity_escalation.1182767568
95.27	0.03	94.60	0.00	92.76	0.09	94.50	0.00			94.73	0.03	96.50	0.00	98.51	0.05	/workspace/coverage/cover_reg_top/85.xbar_stress_all_with_rand_reset.3124832610
95.30	0.03	94.64	0.04	92.80	0.04	94.57	0.07			94.74	0.02	96.50	0.00	98.51	0.00	/workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.1076755834
95.32	0.03	94.64	0.00	92.97	0.17	94.57	0.00			94.74	0.00	96.50	0.00	98.51	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_0.1445258182
95.35	0.03	94.64	0.00	92.97	0.00	94.74	0.16			94.74	0.00	96.50	0.00	98.51	0.00	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.1721386150
95.38	0.02	94.71	0.07	93.02	0.05	94.74	0.01			94.77	0.02	96.50	0.00	98.51	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.3907821650
95.40	0.02	94.72	0.01	93.05	0.03	94.84	0.10			94.77	0.01	96.50	0.00	98.51	0.00	/workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.3546169303
95.42	0.02	94.75	0.03	93.09	0.04	94.85	0.01			94.80	0.02	96.50	0.00	98.51	0.00	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.640828343
95.43	0.02	94.75	0.00	93.09	0.01	94.85	0.00			94.80	0.00	96.50	0.00	98.60	0.09	/workspace/coverage/cover_reg_top/43.xbar_stress_all_with_rand_reset.635937958
95.45	0.02	94.75	0.00	93.18	0.09	94.85	0.00			94.80	0.00	96.50	0.00	98.60	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_0.2829586214
95.46	0.01	94.75	0.00	93.18	0.00	94.94	0.09			94.80	0.00	96.50	0.00	98.60	0.00	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3349672708
95.48	0.01	94.75	0.00	93.18	0.00	95.02	0.08			94.80	0.00	96.50	0.00	98.60	0.00	/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.553102009
95.49	0.01	94.75	0.00	93.23	0.05	95.02	0.00			94.81	0.02	96.50	0.00	98.61	0.01	/workspace/coverage/cover_reg_top/29.xbar_stress_all_with_rand_reset.3358363718
95.50	0.01	94.75	0.00	93.30	0.07	95.02	0.00			94.81	0.00	96.50	0.00	98.61	0.00	/workspace/coverage/cover_reg_top/25.chip_tl_errors.255853579
95.51	0.01	94.78	0.02	93.30	0.01	95.04	0.02			94.83	0.02	96.50	0.00	98.61	0.00	/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.4061726066
95.52	0.01	94.79	0.02	93.33	0.03	95.05	0.01			94.85	0.02	96.50	0.00	98.61	0.00	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.1238575739
95.53	0.01	94.82	0.02	93.35	0.02	95.08	0.03			94.85	0.00	96.50	0.00	98.61	0.00	/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.3213066446
95.55	0.01	94.85	0.03	93.37	0.02	95.08	0.00			94.86	0.01	96.50	0.00	98.61	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.722260754
95.56	0.01	94.85	0.00	93.43	0.06	95.08	0.00			94.86	0.00	96.50	0.00	98.61	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_20.4033586042
95.56	0.01	94.85	0.00	93.45	0.01	95.11	0.03			94.86	0.01	96.50	0.00	98.61	0.00	/workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.52110350
95.57	0.01	94.85	0.00	93.46	0.02	95.11	0.00			94.86	0.00	96.50	0.00	98.65	0.04	/workspace/coverage/cover_reg_top/36.xbar_stress_all_with_rand_reset.3200465429
95.58	0.01	94.85	0.01	93.47	0.01	95.15	0.04			94.86	0.00	96.50	0.00	98.65	0.00	/workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.700301280
95.59	0.01	94.88	0.02	93.48	0.01	95.15	0.01			94.88	0.02	96.50	0.00	98.65	0.00	/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.1596359291
95.60	0.01	94.88	0.00	93.52	0.04	95.15	0.00			94.88	0.00	96.50	0.00	98.65	0.00	/workspace/coverage/cover_reg_top/16.chip_tl_errors.848585734
95.60	0.01	94.88	0.00	93.56	0.04	95.15	0.00			94.88	0.00	96.50	0.00	98.65	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_10.4055430973
95.61	0.01	94.88	0.00	93.56	0.00	95.19	0.04			94.88	0.00	96.50	0.00	98.65	0.00	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.2644083328
95.62	0.01	94.88	0.00	93.60	0.04	95.19	0.00			94.88	0.00	96.50	0.00	98.65	0.00	/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.666388843
95.62	0.01	94.88	0.00	93.62	0.01	95.22	0.02			94.88	0.00	96.50	0.00	98.65	0.00	/workspace/coverage/default/2.chip_sw_uart_tx_rx.1901020533
95.63	0.01	94.88	0.00	93.62	0.00	95.25	0.04			94.88	0.00	96.50	0.00	98.65	0.00	/workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.336242977
95.64	0.01	94.88	0.00	93.65	0.04	95.25	0.00			94.88	0.00	96.50	0.00	98.65	0.00	/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.2240779288
95.64	0.01	94.88	0.00	93.65	0.00	95.25	0.00			94.88	0.00	96.50	0.00	98.68	0.04	/workspace/coverage/cover_reg_top/3.xbar_stress_all_with_reset_error.4143198328
95.65	0.01	94.88	0.00	93.67	0.02	95.27	0.01			94.88	0.00	96.50	0.00	98.68	0.00	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2473775552
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95.86	0.01	94.90	0.00	93.88	0.00	95.43	0.00			94.88	0.00	96.50	0.00	99.55	0.01	/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.2879110342
95.86	0.01	94.90	0.00	93.89	0.01	95.43	0.00			94.88	0.00	96.50	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/97.xbar_stress_all.1771369344
95.86	0.01	94.90	0.00	93.90	0.01	95.43	0.00			94.88	0.00	96.50	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_gpio.725347714
95.86	0.01	94.90	0.00	93.91	0.01	95.43	0.00			94.88	0.00	96.50	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.149883435
95.87	0.01	94.91	0.01	93.91	0.00	95.43	0.00			94.88	0.00	96.50	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_plic_sw_irq.2372472316
95.87	0.01	94.91	0.00	93.92	0.01	95.44	0.01			94.88	0.00	96.50	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_entropy_src_csrng.561274763
95.87	0.01	94.91	0.00	93.92	0.00	95.45	0.01			94.88	0.00	96.50	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.2834068828
95.87	0.01	94.91	0.00	93.92	0.00	95.45	0.01			94.88	0.00	96.50	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.54614142
95.87	0.01	94.91	0.00	93.92	0.01	95.46	0.01			94.88	0.00	96.50	0.00	99.55	0.00	/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.1231446015
95.87	0.01	94.91	0.00	93.92	0.00	95.46	0.00			94.89	0.01	96.50	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.2975384539
95.87	0.01	94.91	0.00	93.93	0.01	95.46	0.00			94.89	0.00	96.50	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/12.xbar_random.1358070686
95.87	0.01	94.91	0.00	93.93	0.01	95.46	0.00			94.89	0.00	96.50	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/5.chip_tl_errors.479979847
95.88	0.01	94.91	0.00	93.94	0.01	95.46	0.00			94.89	0.00	96.50	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/82.xbar_stress_all_with_error.1835025681
95.88	0.01	94.91	0.00	93.95	0.01	95.46	0.00			94.89	0.00	96.50	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.372804412
95.88	0.01	94.91	0.00	93.95	0.01	95.46	0.00			94.89	0.00	96.50	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.487904146
95.88	0.01	94.91	0.00	93.96	0.01	95.46	0.00			94.89	0.00	96.50	0.00	99.55	0.00	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops.2274806175
95.88	0.01	94.91	0.00	93.96	0.00	95.47	0.01			94.89	0.00	96.50	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.782055308
95.88	0.01	94.91	0.00	93.96	0.00	95.47	0.01			94.89	0.00	96.50	0.00	99.55	0.00	/workspace/coverage/default/1.chip_sw_kmac_entropy.544714949
95.88	0.01	94.92	0.01	93.96	0.00	95.47	0.00			94.89	0.00	96.50	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.599658802
95.88	0.01	94.93	0.01	93.96	0.00	95.47	0.00			94.89	0.00	96.50	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.2065868922
95.89	0.01	94.93	0.01	93.96	0.00	95.47	0.00			94.89	0.00	96.50	0.00	99.55	0.00	/workspace/coverage/default/1.chip_sw_pattgen_ios.2485621927
95.89	0.01	94.93	0.00	93.97	0.01	95.47	0.01			94.89	0.00	96.50	0.00	99.55	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.4254662204
95.89	0.01	94.93	0.00	93.97	0.00	95.48	0.01			94.89	0.00	96.50	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.747458174
95.89	0.01	94.93	0.00	93.97	0.00	95.48	0.01			94.89	0.00	96.50	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2000376845
95.89	0.01	94.93	0.00	93.97	0.00	95.49	0.01			94.89	0.00	96.50	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.4032572530
95.89	0.01	94.93	0.00	93.97	0.00	95.49	0.01			94.89	0.00	96.50	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.2600180441
95.89	0.01	94.93	0.00	93.97	0.00	95.50	0.01			94.89	0.00	96.50	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.1778048258
95.89	0.01	94.93	0.00	93.97	0.01	95.50	0.00			94.89	0.00	96.50	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/1.chip_csr_rw.3238411861
95.89	0.01	94.93	0.00	93.97	0.01	95.50	0.00			94.89	0.00	96.50	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/17.chip_tl_errors.3442130006
95.89	0.01	94.93	0.00	93.98	0.01	95.50	0.00			94.89	0.00	96.50	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/18.xbar_stress_all_with_error.2619092881
95.89	0.01	94.93	0.00	93.98	0.01	95.50	0.00			94.89	0.00	96.50	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/29.xbar_stress_all_with_error.314122661
95.89	0.01	94.93	0.00	93.98	0.01	95.50	0.00			94.89	0.00	96.50	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/53.xbar_stress_all_with_reset_error.1206928155
95.89	0.01	94.93	0.00	93.99	0.01	95.50	0.00			94.89	0.00	96.50	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/61.xbar_stress_all_with_error.1773255706
95.89	0.01	94.93	0.00	93.99	0.01	95.50	0.00			94.89	0.00	96.50	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/69.xbar_stress_all_with_reset_error.37174021
95.89	0.01	94.93	0.00	93.99	0.01	95.50	0.00			94.89	0.00	96.50	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/76.xbar_stress_all_with_error.4030576952
95.90	0.01	94.93	0.00	94.00	0.01	95.50	0.00			94.89	0.00	96.50	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/85.xbar_stress_all_with_error.250964248
95.90	0.01	94.93	0.00	94.00	0.01	95.50	0.00			94.89	0.00	96.50	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/93.xbar_stress_all_with_error.1833328229
95.90	0.01	94.93	0.00	94.00	0.01	95.50	0.00			94.89	0.00	96.50	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/96.xbar_stress_all_with_error.3800191054
95.90	0.01	94.93	0.00	94.01	0.01	95.50	0.00			94.89	0.00	96.50	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.3117474909
95.90	0.01	94.93	0.00	94.01	0.00	95.50	0.01			94.89	0.00	96.50	0.00	99.55	0.00	/workspace/coverage/default/0.chip_tap_straps_rma.2824247633
95.90	0.01	94.94	0.01	94.01	0.00	95.50	0.00			94.89	0.00	96.50	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.2039032628
95.90	0.01	94.94	0.01	94.01	0.00	95.50	0.00			94.89	0.00	96.50	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.4256186597
95.90	0.01	94.94	0.00	94.01	0.00	95.50	0.01			94.89	0.00	96.50	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.4218750271
95.90	0.01	94.94	0.00	94.01	0.00	95.51	0.01			94.89	0.00	96.50	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_edn_boot_mode.181260829
95.90	0.01	94.94	0.00	94.01	0.00	95.51	0.01			94.89	0.00	96.50	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.3995849522
95.90	0.01	94.94	0.00	94.01	0.00	95.51	0.01			94.89	0.00	96.50	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.3233510294
95.90	0.01	94.94	0.00	94.01	0.00	95.51	0.01			94.89	0.00	96.50	0.00	99.55	0.00	/workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.2218283367

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.1647323975
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.1286900133
/workspace/coverage/cover_reg_top/0.chip_csr_rw.1183787753
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.3993530006
/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.1466453781
/workspace/coverage/cover_reg_top/0.chip_tl_errors.792860937
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.1008955449
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.3653729514
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.1974751671
/workspace/coverage/cover_reg_top/0.xbar_error_random.1945330753
/workspace/coverage/cover_reg_top/0.xbar_random.1443490148
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.331683058
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.1226649076
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.2910838431
/workspace/coverage/cover_reg_top/0.xbar_same_source.4147368201
/workspace/coverage/cover_reg_top/0.xbar_smoke.3278631520
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.219859981
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.383297822
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.1165171890
/workspace/coverage/cover_reg_top/0.xbar_stress_all.2429861470
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.2642117831
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.3604141467
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.2621040331
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.685443605
/workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.3519516255
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.1177634216
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.1565407467
/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.3865099532
/workspace/coverage/cover_reg_top/1.chip_tl_errors.2901099053
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.1650418163
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.3600735451
/workspace/coverage/cover_reg_top/1.xbar_error_random.3701023919
/workspace/coverage/cover_reg_top/1.xbar_random.939419078
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.801358752
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.3009803610
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.575092101
/workspace/coverage/cover_reg_top/1.xbar_same_source.3461891944
/workspace/coverage/cover_reg_top/1.xbar_smoke.3034101496
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.1728146231
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.431712974
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.3816820449
/workspace/coverage/cover_reg_top/1.xbar_stress_all.465667635
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.863277750
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.2918817501
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.1339915300
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.2645000344
/workspace/coverage/cover_reg_top/10.chip_csr_rw.2051221424
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.1526376996
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.1005976888
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.2453036221
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.2377702601
/workspace/coverage/cover_reg_top/10.xbar_error_random.1086760042
/workspace/coverage/cover_reg_top/10.xbar_random.4289356847
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.1426394570
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.3352361571
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.3567763639
/workspace/coverage/cover_reg_top/10.xbar_same_source.525583328
/workspace/coverage/cover_reg_top/10.xbar_smoke.1936713203
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.3959184072
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.30285905
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.1651042190
/workspace/coverage/cover_reg_top/10.xbar_stress_all.445192025
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.3674114605
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.1271028621
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.1239171300
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.1019012972
/workspace/coverage/cover_reg_top/11.chip_csr_rw.887902768
/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.1338349121
/workspace/coverage/cover_reg_top/11.chip_tl_errors.371200370
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.922555129
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.1035844061
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.1194393424
/workspace/coverage/cover_reg_top/11.xbar_error_random.2838600497
/workspace/coverage/cover_reg_top/11.xbar_random.43338160
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.2718833472
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.45308890
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.3088382779
/workspace/coverage/cover_reg_top/11.xbar_same_source.306672782
/workspace/coverage/cover_reg_top/11.xbar_smoke.3269444770
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.495952335
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.2481436931
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.790675572
/workspace/coverage/cover_reg_top/11.xbar_stress_all.1830374374
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.2763776659
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.3928214951
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.3042210692
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.518005816
/workspace/coverage/cover_reg_top/12.chip_csr_rw.1290926007
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.2827186221
/workspace/coverage/cover_reg_top/12.chip_tl_errors.3300697754
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.548499589
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.1403826896
/workspace/coverage/cover_reg_top/12.xbar_error_random.1939026800
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.763453951
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.916712394
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.1719080506
/workspace/coverage/cover_reg_top/12.xbar_same_source.2338202223
/workspace/coverage/cover_reg_top/12.xbar_smoke.1804495066
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.3068644970
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.2266413729
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.3033495846
/workspace/coverage/cover_reg_top/12.xbar_stress_all.3714130787
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.3195415670
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.16604016
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.60109596
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.4173033162
/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.250497290
/workspace/coverage/cover_reg_top/13.chip_tl_errors.2720698449
/workspace/coverage/cover_reg_top/13.xbar_access_same_device.1417065121
/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.3499733054
/workspace/coverage/cover_reg_top/13.xbar_error_random.3361038970
/workspace/coverage/cover_reg_top/13.xbar_random.1317279231
/workspace/coverage/cover_reg_top/13.xbar_random_large_delays.1090660404
/workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.3794315515
/workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.2825771680
/workspace/coverage/cover_reg_top/13.xbar_same_source.2852685247
/workspace/coverage/cover_reg_top/13.xbar_smoke.4096010437
/workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.1487798632
/workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.3336822757
/workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.1524254012
/workspace/coverage/cover_reg_top/13.xbar_stress_all.727199275
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.588380616
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.898127779
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.1391424464
/workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.712471418
/workspace/coverage/cover_reg_top/14.chip_csr_rw.2602448020
/workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.3230095882
/workspace/coverage/cover_reg_top/14.chip_tl_errors.1259526949
/workspace/coverage/cover_reg_top/14.xbar_access_same_device.4063838976
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/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.1749089935
/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.2447419855
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/workspace/coverage/default/37.chip_sw_all_escalation_resets.3606941910
/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.966024946
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/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.2032397549
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.2025907589
/workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.2038627841
/workspace/coverage/default/4.chip_sw_data_integrity_escalation.3910291965
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.3726172186
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.2876022696
/workspace/coverage/default/4.chip_sw_uart_tx_rx.3416961445
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.3347222903
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/workspace/coverage/default/4.chip_tap_straps_rma.3986370043
/workspace/coverage/default/4.chip_tap_straps_testunlock0.1672678361
/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.3871955744
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/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.3409826946
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/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.2342276476
/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.3696308267
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.3191604308
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.3055983449
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.1108488671
/workspace/coverage/default/50.chip_sw_all_escalation_resets.2501352823
/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.3094605632
/workspace/coverage/default/52.chip_sw_all_escalation_resets.1156553754
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.3247955919
/workspace/coverage/default/53.chip_sw_all_escalation_resets.3671610372
/workspace/coverage/default/54.chip_sw_all_escalation_resets.478989835
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.3136246546
/workspace/coverage/default/55.chip_sw_all_escalation_resets.1166082215
/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.906824394
/workspace/coverage/default/56.chip_sw_all_escalation_resets.2973370373
/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.796162010
/workspace/coverage/default/57.chip_sw_all_escalation_resets.3988143626
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.563614665
/workspace/coverage/default/58.chip_sw_all_escalation_resets.1545313272
/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.3234803154
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.2448511363
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.1893795808
/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.3978069814
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.2208568872
/workspace/coverage/default/61.chip_sw_all_escalation_resets.3493066493
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.1750136026
/workspace/coverage/default/62.chip_sw_all_escalation_resets.3557363283
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.2051447827
/workspace/coverage/default/63.chip_sw_all_escalation_resets.2254877554
/workspace/coverage/default/64.chip_sw_all_escalation_resets.1153247643
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.3168837080
/workspace/coverage/default/65.chip_sw_all_escalation_resets.4085438275
/workspace/coverage/default/66.chip_sw_all_escalation_resets.1796207025
/workspace/coverage/default/68.chip_sw_all_escalation_resets.1251908137
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.450647747
/workspace/coverage/default/69.chip_sw_all_escalation_resets.1252009549
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.3566644299
/workspace/coverage/default/7.chip_sw_all_escalation_resets.242944225
/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.2450682449
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.3410131783
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.706683670
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.2134570775
/workspace/coverage/default/70.chip_sw_all_escalation_resets.3794842563
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.2135087540
/workspace/coverage/default/71.chip_sw_all_escalation_resets.2746597529
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.3181669926
/workspace/coverage/default/72.chip_sw_all_escalation_resets.1626840150
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.3483788153
/workspace/coverage/default/73.chip_sw_all_escalation_resets.1886439679
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.2495027371
/workspace/coverage/default/74.chip_sw_all_escalation_resets.3724021128
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.2335494201
/workspace/coverage/default/75.chip_sw_all_escalation_resets.4226728617
/workspace/coverage/default/76.chip_sw_all_escalation_resets.484120037
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.1200320183
/workspace/coverage/default/77.chip_sw_all_escalation_resets.3128367108
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.751677869
/workspace/coverage/default/78.chip_sw_all_escalation_resets.2856409283
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.3721989269
/workspace/coverage/default/79.chip_sw_all_escalation_resets.1257983273
/workspace/coverage/default/8.chip_sw_all_escalation_resets.3279686528
/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.530762968
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.2882502683
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.2934908732
/workspace/coverage/default/80.chip_sw_all_escalation_resets.3754160204
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.420306478
/workspace/coverage/default/81.chip_sw_all_escalation_resets.1827368666
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.147827366
/workspace/coverage/default/82.chip_sw_all_escalation_resets.3743982497
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.3476553136
/workspace/coverage/default/83.chip_sw_all_escalation_resets.1658551342
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.1718048243
/workspace/coverage/default/84.chip_sw_all_escalation_resets.2555483184
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.34444850
/workspace/coverage/default/85.chip_sw_all_escalation_resets.1489394132
/workspace/coverage/default/87.chip_sw_all_escalation_resets.1559679521
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.2862260836
/workspace/coverage/default/88.chip_sw_all_escalation_resets.586746659
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.1624881625
/workspace/coverage/default/89.chip_sw_all_escalation_resets.2184114097
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.1499315256
/workspace/coverage/default/9.chip_sw_all_escalation_resets.334933546
/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.2592602607
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.1797316283
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.176119700
/workspace/coverage/default/90.chip_sw_all_escalation_resets.131369115
/workspace/coverage/default/91.chip_sw_all_escalation_resets.2265502606
/workspace/coverage/default/92.chip_sw_all_escalation_resets.486555341
/workspace/coverage/default/93.chip_sw_all_escalation_resets.1245735141
/workspace/coverage/default/95.chip_sw_all_escalation_resets.1088735158
/workspace/coverage/default/96.chip_sw_all_escalation_resets.654456581
/workspace/coverage/default/97.chip_sw_all_escalation_resets.1760778879
/workspace/coverage/default/98.chip_sw_all_escalation_resets.1606288878
/workspace/coverage/default/99.chip_sw_all_escalation_resets.596545242
/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.3491200130
/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.1672446290
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.3113098661
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.9591631
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.1391435216
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.2322167733
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.2995272527
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.1255866798

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Total test records in report: 2887

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T4	/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.3566644299			Jun 07 10:07:19 PM PDT 24	Jun 07 10:14:26 PM PDT 24	3874498676 ps
T5	/workspace/coverage/default/0.chip_sw_flash_crash_alert.3481267136			Jun 07 09:49:30 PM PDT 24	Jun 07 10:00:50 PM PDT 24	5076157600 ps
T6	/workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.3633270741			Jun 07 09:42:57 PM PDT 24	Jun 07 11:01:41 PM PDT 24	44708027001 ps
T70	/workspace/coverage/default/4.chip_tap_straps_dev.74446018			Jun 07 10:04:52 PM PDT 24	Jun 07 10:33:37 PM PDT 24	17916887908 ps
T17	/workspace/coverage/default/11.chip_sw_uart_rand_baudrate.3453944050			Jun 07 10:07:43 PM PDT 24	Jun 07 10:17:03 PM PDT 24	3501083712 ps
T42	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation.1229128315			Jun 07 09:37:49 PM PDT 24	Jun 07 10:05:33 PM PDT 24	7087353758 ps
T61	/workspace/coverage/default/42.chip_sw_all_escalation_resets.3737614325			Jun 07 10:11:00 PM PDT 24	Jun 07 10:20:32 PM PDT 24	5151357564 ps
T82	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.2530991905			Jun 07 10:07:24 PM PDT 24	Jun 07 10:18:47 PM PDT 24	4485450152 ps
T1	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.2089367628			Jun 07 09:39:45 PM PDT 24	Jun 07 10:11:01 PM PDT 24	21896978300 ps
T83	/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.3172495547			Jun 07 09:50:57 PM PDT 24	Jun 07 09:55:35 PM PDT 24	2340620526 ps
T101	/workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.686146467			Jun 07 09:41:55 PM PDT 24	Jun 07 09:45:52 PM PDT 24	3096318464 ps
T102	/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.3376699982			Jun 07 09:58:38 PM PDT 24	Jun 07 10:02:36 PM PDT 24	3457662484 ps
T103	/workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.1296100175			Jun 07 09:42:01 PM PDT 24	Jun 07 09:51:39 PM PDT 24	4356167528 ps
T62	/workspace/coverage/default/59.chip_sw_all_escalation_resets.1616265928			Jun 07 10:13:14 PM PDT 24	Jun 07 10:23:09 PM PDT 24	5422207240 ps
T104	/workspace/coverage/default/2.chip_sw_uart_tx_rx.1901020533			Jun 07 09:53:28 PM PDT 24	Jun 07 10:06:06 PM PDT 24	4826963570 ps
T28	/workspace/coverage/default/0.chip_sw_usbdev_setuprx.3009042836			Jun 07 09:35:38 PM PDT 24	Jun 07 09:47:09 PM PDT 24	4409413740 ps
T105	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.1291421610			Jun 07 09:36:28 PM PDT 24	Jun 07 09:43:25 PM PDT 24	4361616424 ps
T55	/workspace/coverage/default/2.chip_tap_straps_testunlock0.3896324276			Jun 07 10:00:17 PM PDT 24	Jun 07 10:14:06 PM PDT 24	6614095356 ps
T53	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.1059245083			Jun 07 09:46:19 PM PDT 24	Jun 07 10:47:29 PM PDT 24	14516052250 ps
T170	/workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.1076755834			Jun 07 09:43:26 PM PDT 24	Jun 07 09:54:02 PM PDT 24	4850676314 ps
T18	/workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.1818921427			Jun 07 09:35:22 PM PDT 24	Jun 07 09:37:21 PM PDT 24	2828452247 ps
T347	/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.551947168			Jun 07 10:08:28 PM PDT 24	Jun 07 10:13:49 PM PDT 24	3545911852 ps
T115	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3349672708			Jun 07 10:00:14 PM PDT 24	Jun 07 10:11:26 PM PDT 24	4275444200 ps
T182	/workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.1172208559			Jun 07 09:49:51 PM PDT 24	Jun 07 09:59:31 PM PDT 24	5444074956 ps
T119	/workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1538174351			Jun 07 09:46:27 PM PDT 24	Jun 08 01:25:02 AM PDT 24	255610569224 ps
T157	/workspace/coverage/default/14.chip_sw_all_escalation_resets.2946445181			Jun 07 10:07:11 PM PDT 24	Jun 07 10:16:55 PM PDT 24	4181032224 ps
T116	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.604082089			Jun 07 09:38:53 PM PDT 24	Jun 07 09:51:51 PM PDT 24	4693592304 ps
T147	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.956947152			Jun 07 10:05:50 PM PDT 24	Jun 07 10:16:51 PM PDT 24	4382108208 ps
T439	/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.3978069814			Jun 07 10:12:03 PM PDT 24	Jun 07 10:17:36 PM PDT 24	3232384770 ps
T224	/workspace/coverage/default/20.chip_sw_all_escalation_resets.2175349205			Jun 07 10:08:25 PM PDT 24	Jun 07 10:17:34 PM PDT 24	5844272382 ps
T19	/workspace/coverage/default/2.rom_e2e_shutdown_exception_c.2046587789			Jun 07 10:07:46 PM PDT 24	Jun 07 11:10:56 PM PDT 24	14275309298 ps
T117	/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2070666311			Jun 07 09:53:14 PM PDT 24	Jun 07 10:20:52 PM PDT 24	13114740199 ps
T801	/workspace/coverage/default/2.chip_sw_aes_entropy.611859844			Jun 07 10:00:45 PM PDT 24	Jun 07 10:05:11 PM PDT 24	2916334560 ps
T269	/workspace/coverage/default/0.chip_plic_all_irqs_0.1380014618			Jun 07 09:36:57 PM PDT 24	Jun 07 09:53:19 PM PDT 24	6018671234 ps
T54	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.2892522987			Jun 07 09:44:08 PM PDT 24	Jun 07 10:47:11 PM PDT 24	14079127250 ps
T442	/workspace/coverage/default/2.chip_sw_kmac_entropy.13082463			Jun 07 09:53:57 PM PDT 24	Jun 07 09:59:37 PM PDT 24	3451942600 ps
T868	/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.1499315256			Jun 07 10:11:33 PM PDT 24	Jun 07 10:19:28 PM PDT 24	4264433238 ps
T129	/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.4061726066			Jun 07 10:04:59 PM PDT 24	Jun 07 10:17:51 PM PDT 24	6100118240 ps
T225	/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.3620327410			Jun 07 10:08:56 PM PDT 24	Jun 07 10:55:15 PM PDT 24	13964185868 ps
T118	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2694834925			Jun 07 09:38:37 PM PDT 24	Jun 07 09:48:56 PM PDT 24	4465397984 ps
T111	/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.997478405			Jun 07 09:59:14 PM PDT 24	Jun 07 10:04:29 PM PDT 24	2699104742 ps
T60	/workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.2777992146			Jun 07 09:55:18 PM PDT 24	Jun 07 10:00:03 PM PDT 24	3667100282 ps
T148	/workspace/coverage/default/1.chip_sw_power_idle_load.791044576			Jun 07 09:52:59 PM PDT 24	Jun 07 10:01:24 PM PDT 24	3974462032 ps
T108	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3030377231			Jun 07 09:50:52 PM PDT 24	Jun 07 10:11:53 PM PDT 24	8097353412 ps
T377	/workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.2024815700			Jun 07 09:41:59 PM PDT 24	Jun 07 09:46:02 PM PDT 24	2459640672 ps
T344	/workspace/coverage/default/65.chip_sw_all_escalation_resets.4085438275			Jun 07 10:15:10 PM PDT 24	Jun 07 10:24:32 PM PDT 24	5137740408 ps
T363	/workspace/coverage/default/58.chip_sw_all_escalation_resets.1545313272			Jun 07 10:11:39 PM PDT 24	Jun 07 10:21:02 PM PDT 24	5811447192 ps
T404	/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.753738986			Jun 07 09:57:36 PM PDT 24	Jun 07 10:55:02 PM PDT 24	14733171336 ps
T120	/workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.859276518			Jun 07 10:03:43 PM PDT 24	Jun 07 10:09:16 PM PDT 24	4905516734 ps
T166	/workspace/coverage/default/0.chip_sival_flash_info_access.4035115124			Jun 07 09:36:36 PM PDT 24	Jun 07 09:41:51 PM PDT 24	3556210768 ps
T228	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.2284920908			Jun 07 09:55:24 PM PDT 24	Jun 07 10:22:41 PM PDT 24	8903103868 ps
T270	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.581335505			Jun 07 09:35:58 PM PDT 24	Jun 07 10:37:50 PM PDT 24	32571080804 ps
T66	/workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.190384067			Jun 07 09:51:05 PM PDT 24	Jun 07 09:58:19 PM PDT 24	4569047676 ps
T365	/workspace/coverage/default/87.chip_sw_all_escalation_resets.1559679521			Jun 07 10:14:24 PM PDT 24	Jun 07 10:22:09 PM PDT 24	5426728120 ps
T266	/workspace/coverage/default/0.chip_sw_rv_timer_smoketest.2135219080			Jun 07 09:43:28 PM PDT 24	Jun 07 09:47:55 PM PDT 24	3047664624 ps
T802	/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.3156877907			Jun 07 09:51:24 PM PDT 24	Jun 07 09:56:09 PM PDT 24	2826733563 ps
T26	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.2223707212			Jun 07 09:55:32 PM PDT 24	Jun 07 10:05:52 PM PDT 24	3844001560 ps
T191	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.318133378			Jun 07 09:38:50 PM PDT 24	Jun 07 09:47:38 PM PDT 24	3658199520 ps
T124	/workspace/coverage/default/2.chip_sw_edn_sw_mode.2973759555			Jun 07 09:57:24 PM PDT 24	Jun 07 10:31:33 PM PDT 24	8627094408 ps
T155	/workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3510460925			Jun 07 09:58:12 PM PDT 24	Jun 08 12:54:42 AM PDT 24	254167807682 ps
T341	/workspace/coverage/default/13.chip_sw_all_escalation_resets.3832757121			Jun 07 10:08:58 PM PDT 24	Jun 07 10:21:39 PM PDT 24	5049922904 ps
T978	/workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.861820861			Jun 07 10:01:01 PM PDT 24	Jun 07 10:06:00 PM PDT 24	3223778744 ps
T546	/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.2510177793			Jun 07 09:40:23 PM PDT 24	Jun 07 09:51:47 PM PDT 24	7697592274 ps
T979	/workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.2089849997			Jun 07 09:48:34 PM PDT 24	Jun 07 09:55:57 PM PDT 24	2991248872 ps
T980	/workspace/coverage/default/1.chip_sw_clkmgr_jitter.2308290395			Jun 07 09:51:06 PM PDT 24	Jun 07 09:55:45 PM PDT 24	2784688302 ps
T981	/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2896723711			Jun 07 10:04:15 PM PDT 24	Jun 07 10:26:55 PM PDT 24	9116292356 ps
T804	/workspace/coverage/default/1.chip_sw_hmac_oneshot.2958105060			Jun 07 09:46:25 PM PDT 24	Jun 07 09:52:30 PM PDT 24	3200621140 ps
T208	/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.2380419220			Jun 07 09:54:38 PM PDT 24	Jun 07 10:08:13 PM PDT 24	5144872760 ps
T451	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2127602057			Jun 07 09:43:10 PM PDT 24	Jun 07 10:01:23 PM PDT 24	11897037751 ps
T227	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.1276024700			Jun 07 09:43:36 PM PDT 24	Jun 07 10:02:42 PM PDT 24	7818435652 ps
T452	/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.1074089198			Jun 07 09:55:19 PM PDT 24	Jun 07 10:02:39 PM PDT 24	7054125468 ps
T453	/workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.3948524814			Jun 07 09:37:07 PM PDT 24	Jun 07 09:49:51 PM PDT 24	7229179120 ps
T777	/workspace/coverage/default/30.chip_sw_all_escalation_resets.2801346219			Jun 07 10:15:07 PM PDT 24	Jun 07 10:26:06 PM PDT 24	5226599252 ps
T254	/workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.3453656077			Jun 07 09:54:49 PM PDT 24	Jun 07 10:08:15 PM PDT 24	4836365270 ps
T67	/workspace/coverage/default/1.chip_jtag_csr_rw.3784074040			Jun 07 09:41:55 PM PDT 24	Jun 07 09:59:15 PM PDT 24	10589847029 ps
T114	/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.2882502683			Jun 07 10:06:42 PM PDT 24	Jun 07 10:22:26 PM PDT 24	11455393548 ps
T278	/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.757859412			Jun 07 10:12:53 PM PDT 24	Jun 07 10:19:04 PM PDT 24	3572564760 ps
T109	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.4287874196			Jun 07 09:57:30 PM PDT 24	Jun 07 10:56:36 PM PDT 24	18633046401 ps
T279	/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.4282490978			Jun 07 10:14:06 PM PDT 24	Jun 07 10:20:09 PM PDT 24	3373778240 ps
T2	/workspace/coverage/default/2.chip_sw_sleep_pin_retention.621176114			Jun 07 09:57:15 PM PDT 24	Jun 07 10:03:11 PM PDT 24	4070484912 ps
T280	/workspace/coverage/default/0.chip_sw_all_escalation_resets.223108482			Jun 07 09:37:56 PM PDT 24	Jun 07 09:48:20 PM PDT 24	5071329766 ps
T164	/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.153573775			Jun 07 09:54:31 PM PDT 24	Jun 07 09:56:44 PM PDT 24	2234402198 ps
T281	/workspace/coverage/default/95.chip_sw_all_escalation_resets.1088735158			Jun 07 10:18:00 PM PDT 24	Jun 07 10:26:47 PM PDT 24	4511280120 ps
T223	/workspace/coverage/default/1.chip_tap_straps_prod.2761124138			Jun 07 09:49:45 PM PDT 24	Jun 07 09:52:53 PM PDT 24	2885249980 ps
T412	/workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.1511453655			Jun 07 09:38:18 PM PDT 24	Jun 07 09:46:38 PM PDT 24	6269906054 ps
T121	/workspace/coverage/default/1.chip_sw_edn_kat.2467281022			Jun 07 09:47:45 PM PDT 24	Jun 07 09:57:10 PM PDT 24	3538528612 ps
T413	/workspace/coverage/default/1.chip_sw_rstmgr_smoketest.2200201448			Jun 07 09:52:49 PM PDT 24	Jun 07 09:57:12 PM PDT 24	3136923384 ps
T414	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac.34668818			Jun 07 09:38:27 PM PDT 24	Jun 07 09:43:23 PM PDT 24	3206942612 ps
T415	/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.2412841628			Jun 07 10:08:24 PM PDT 24	Jun 07 10:15:38 PM PDT 24	3769027656 ps
T240	/workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.2328615906			Jun 07 09:58:42 PM PDT 24	Jun 07 10:10:53 PM PDT 24	9124917070 ps
T185	/workspace/coverage/default/0.chip_sw_lc_ctrl_transition.2213371534			Jun 07 09:36:35 PM PDT 24	Jun 07 09:49:20 PM PDT 24	11255601967 ps
T173	/workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.4106706422			Jun 07 09:38:01 PM PDT 24	Jun 07 09:40:47 PM PDT 24	2737654377 ps
T982	/workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.3804952035			Jun 07 10:01:18 PM PDT 24	Jun 07 10:04:08 PM PDT 24	2693188559 ps
T158	/workspace/coverage/default/27.chip_sw_all_escalation_resets.2276300766			Jun 07 10:14:01 PM PDT 24	Jun 07 10:23:46 PM PDT 24	5703202154 ps
T29	/workspace/coverage/default/0.chip_sw_usbdev_pullup.3113722107			Jun 07 09:37:14 PM PDT 24	Jun 07 09:40:43 PM PDT 24	2741232400 ps
T357	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2473775552			Jun 07 10:02:41 PM PDT 24	Jun 07 10:15:34 PM PDT 24	5635304102 ps
T983	/workspace/coverage/default/0.chip_sw_rstmgr_sw_req.4174935243			Jun 07 09:40:15 PM PDT 24	Jun 07 09:50:22 PM PDT 24	3851327426 ps
T364	/workspace/coverage/default/40.chip_sw_all_escalation_resets.479318276			Jun 07 10:10:31 PM PDT 24	Jun 07 10:20:35 PM PDT 24	5329135544 ps
T870	/workspace/coverage/default/90.chip_sw_all_escalation_resets.131369115			Jun 07 10:15:04 PM PDT 24	Jun 07 10:23:56 PM PDT 24	5075505736 ps
T779	/workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.928525253			Jun 07 10:00:45 PM PDT 24	Jun 07 10:09:20 PM PDT 24	3698510128 ps
T984	/workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.1130730994			Jun 07 09:55:00 PM PDT 24	Jun 07 09:59:56 PM PDT 24	3240478503 ps
T390	/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.2540509875			Jun 07 10:13:31 PM PDT 24	Jun 07 10:20:43 PM PDT 24	3842623464 ps
T985	/workspace/coverage/default/1.chip_sw_example_flash.2211567865			Jun 07 09:42:33 PM PDT 24	Jun 07 09:45:55 PM PDT 24	3275199240 ps
T45	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1075980653			Jun 07 09:57:04 PM PDT 24	Jun 07 10:05:19 PM PDT 24	5588425904 ps
T391	/workspace/coverage/default/82.chip_sw_all_escalation_resets.3743982497			Jun 07 10:15:15 PM PDT 24	Jun 07 10:27:22 PM PDT 24	6181367824 ps
T110	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1956803224			Jun 07 10:01:16 PM PDT 24	Jun 07 10:55:03 PM PDT 24	24263557395 ps
T159	/workspace/coverage/default/55.chip_sw_all_escalation_resets.1166082215			Jun 07 10:12:32 PM PDT 24	Jun 07 10:22:37 PM PDT 24	5308516896 ps
T986	/workspace/coverage/default/2.chip_sw_aon_timer_smoketest.1266748645			Jun 07 10:04:59 PM PDT 24	Jun 07 10:09:08 PM PDT 24	2993525628 ps
T987	/workspace/coverage/default/2.chip_sw_uart_rand_baudrate.3588381516			Jun 07 09:55:48 PM PDT 24	Jun 07 10:52:40 PM PDT 24	12956206560 ps
T778	/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.796162010			Jun 07 10:12:32 PM PDT 24	Jun 07 10:20:18 PM PDT 24	3829864708 ps
T878	/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.301344352			Jun 07 10:09:42 PM PDT 24	Jun 07 10:17:06 PM PDT 24	3917407554 ps
T171	/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.115332545			Jun 07 09:35:34 PM PDT 24	Jun 07 09:42:32 PM PDT 24	4326863503 ps
T352	/workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.700301280			Jun 07 09:56:01 PM PDT 24	Jun 07 10:23:19 PM PDT 24	12549348394 ps
T257	/workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.913499629			Jun 07 09:48:23 PM PDT 24	Jun 07 09:58:20 PM PDT 24	5285899400 ps
T220	/workspace/coverage/default/13.chip_sw_uart_rand_baudrate.866081847			Jun 07 10:10:33 PM PDT 24	Jun 07 10:30:51 PM PDT 24	8470735000 ps
T68	/workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.846596733			Jun 07 09:50:40 PM PDT 24	Jun 07 09:58:36 PM PDT 24	5700622136 ps
T3	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.3588351360			Jun 07 10:02:11 PM PDT 24	Jun 07 10:36:00 PM PDT 24	24967049952 ps
T988	/workspace/coverage/default/1.chip_sw_example_concurrency.347739456			Jun 07 09:41:01 PM PDT 24	Jun 07 09:45:39 PM PDT 24	2634129800 ps
T405	/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.77481268			Jun 07 09:45:45 PM PDT 24	Jun 07 10:48:24 PM PDT 24	15197460370 ps
T206	/workspace/coverage/default/45.chip_sw_all_escalation_resets.4281776545			Jun 07 10:11:26 PM PDT 24	Jun 07 10:22:45 PM PDT 24	5441863812 ps
T356	/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1809347326			Jun 07 09:56:32 PM PDT 24	Jun 07 10:20:47 PM PDT 24	11648538399 ps
T366	/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.235550553			Jun 07 09:39:37 PM PDT 24	Jun 07 09:44:20 PM PDT 24	3226252927 ps
T360	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.658805968			Jun 07 09:36:03 PM PDT 24	Jun 07 09:48:06 PM PDT 24	4589577406 ps
T989	/workspace/coverage/default/2.chip_sw_clkmgr_jitter.3142005196			Jun 07 10:00:14 PM PDT 24	Jun 07 10:05:03 PM PDT 24	3463602198 ps
T787	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.350666135			Jun 07 09:43:00 PM PDT 24	Jun 07 09:48:00 PM PDT 24	3332237604 ps
T990	/workspace/coverage/default/0.chip_sw_aes_smoketest.2329696898			Jun 07 09:43:04 PM PDT 24	Jun 07 09:48:51 PM PDT 24	2735936050 ps
T829	/workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.2283272293			Jun 07 09:36:29 PM PDT 24	Jun 07 09:50:36 PM PDT 24	5492707224 ps
T760	/workspace/coverage/default/50.chip_sw_all_escalation_resets.2501352823			Jun 07 10:10:39 PM PDT 24	Jun 07 10:21:37 PM PDT 24	5152850084 ps
T401	/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.14010717			Jun 07 10:13:42 PM PDT 24	Jun 07 10:20:52 PM PDT 24	4383360014 ps
T991	/workspace/coverage/default/2.chip_sw_uart_smoketest.1149946551			Jun 07 10:04:31 PM PDT 24	Jun 07 10:08:50 PM PDT 24	2921892992 ps
T406	/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.1377955709			Jun 07 09:57:24 PM PDT 24	Jun 07 10:56:20 PM PDT 24	14152106040 ps
T51	/workspace/coverage/default/1.rom_e2e_shutdown_exception_c.2337099935			Jun 07 09:55:43 PM PDT 24	Jun 07 10:51:00 PM PDT 24	14515098925 ps
T27	/workspace/coverage/default/14.chip_sw_uart_rand_baudrate.2021885991			Jun 07 10:08:20 PM PDT 24	Jun 07 10:16:54 PM PDT 24	4284577616 ps
T992	/workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.498506498			Jun 07 09:50:26 PM PDT 24	Jun 07 09:56:55 PM PDT 24	4769992224 ps
T258	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.487904146			Jun 07 09:37:56 PM PDT 24	Jun 07 10:12:39 PM PDT 24	11383467640 ps
T160	/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.4008812492			Jun 07 09:56:34 PM PDT 24	Jun 07 10:30:17 PM PDT 24	12876741532 ps
T252	/workspace/coverage/default/2.chip_sw_data_integrity_escalation.179814615			Jun 07 09:53:09 PM PDT 24	Jun 07 10:05:48 PM PDT 24	5955695624 ps
T287	/workspace/coverage/default/1.chip_plic_all_irqs_0.1445258182			Jun 07 09:48:56 PM PDT 24	Jun 07 10:09:43 PM PDT 24	5970443172 ps
T288	/workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.851242117			Jun 07 09:43:13 PM PDT 24	Jun 07 09:50:16 PM PDT 24	4307288996 ps
T289	/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.2447419855			Jun 07 10:13:25 PM PDT 24	Jun 07 10:19:34 PM PDT 24	3710075330 ps
T290	/workspace/coverage/default/1.chip_sw_kmac_entropy.544714949			Jun 07 09:41:11 PM PDT 24	Jun 07 09:46:03 PM PDT 24	2815663280 ps
T291	/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.3723911031			Jun 07 10:08:17 PM PDT 24	Jun 07 10:16:12 PM PDT 24	4058550312 ps
T292	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.4254662204			Jun 07 09:46:30 PM PDT 24	Jun 07 11:18:21 PM PDT 24	22878036200 ps
T293	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.771401940			Jun 07 09:45:56 PM PDT 24	Jun 07 10:48:37 PM PDT 24	14444239610 ps
T294	/workspace/coverage/default/4.chip_sw_uart_tx_rx.3416961445			Jun 07 10:04:23 PM PDT 24	Jun 07 10:16:55 PM PDT 24	4188197258 ps
T209	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.599658802			Jun 07 09:37:14 PM PDT 24	Jun 07 09:52:02 PM PDT 24	4760927496 ps
T993	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3895710078			Jun 07 09:49:07 PM PDT 24	Jun 07 09:59:44 PM PDT 24	4808414312 ps
T833	/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1435390036			Jun 07 09:40:48 PM PDT 24	Jun 07 10:00:28 PM PDT 24	7631503139 ps
T169	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.3699852117			Jun 07 09:35:53 PM PDT 24	Jun 07 10:01:59 PM PDT 24	9206174760 ps
T547	/workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.648250131			Jun 07 09:40:07 PM PDT 24	Jun 07 09:44:44 PM PDT 24	3276689600 ps
T161	/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.3104355070			Jun 07 09:44:23 PM PDT 24	Jun 07 09:48:04 PM PDT 24	2632215895 ps
T994	/workspace/coverage/default/2.chip_sw_example_manufacturer.970709029			Jun 07 09:52:24 PM PDT 24	Jun 07 09:56:40 PM PDT 24	2487886916 ps
T995	/workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.1203501367			Jun 07 09:36:16 PM PDT 24	Jun 07 11:09:03 PM PDT 24	26620397390 ps
T831	/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.687062483			Jun 07 10:07:29 PM PDT 24	Jun 07 10:13:11 PM PDT 24	4149146816 ps
T996	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3955281303			Jun 07 09:55:58 PM PDT 24	Jun 07 10:38:21 PM PDT 24	29349891798 ps
T255	/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.1192967166			Jun 07 09:37:39 PM PDT 24	Jun 07 09:48:38 PM PDT 24	6902437400 ps
T79	/workspace/coverage/default/1.chip_sw_alert_handler_entropy.4257169199			Jun 07 09:47:05 PM PDT 24	Jun 07 09:53:52 PM PDT 24	3618971059 ps
T112	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.3195488611			Jun 07 09:59:31 PM PDT 24	Jun 07 10:11:48 PM PDT 24	4346898443 ps
T302	/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.3483788153			Jun 07 10:13:45 PM PDT 24	Jun 07 10:19:05 PM PDT 24	3374784090 ps
T303	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.80061216			Jun 07 10:05:26 PM PDT 24	Jun 07 10:14:57 PM PDT 24	4412221640 ps
T212	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.2039032628			Jun 07 09:35:00 PM PDT 24	Jun 07 09:43:45 PM PDT 24	4867543212 ps
T106	/workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.643439014			Jun 07 09:45:07 PM PDT 24	Jun 07 09:55:57 PM PDT 24	18537584794 ps
T122	/workspace/coverage/default/1.chip_sw_edn_auto_mode.3745041466			Jun 07 09:48:43 PM PDT 24	Jun 07 10:07:19 PM PDT 24	4057594518 ps
T304	/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.554583903			Jun 07 10:06:50 PM PDT 24	Jun 07 10:15:52 PM PDT 24	3784070448 ps
T133	/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.1596359291			Jun 07 09:47:12 PM PDT 24	Jun 07 10:05:50 PM PDT 24	7831891024 ps
T213	/workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.2984159055			Jun 07 09:54:00 PM PDT 24	Jun 07 10:03:32 PM PDT 24	4796003680 ps
T305	/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.1334579140			Jun 07 10:07:51 PM PDT 24	Jun 07 10:14:38 PM PDT 24	3949692620 ps
T437	/workspace/coverage/default/53.chip_sw_all_escalation_resets.3671610372			Jun 07 10:11:37 PM PDT 24	Jun 07 10:20:37 PM PDT 24	5236236120 ps
T210	/workspace/coverage/default/17.chip_sw_uart_rand_baudrate.2123215717			Jun 07 10:08:19 PM PDT 24	Jun 07 10:34:53 PM PDT 24	8975341144 ps
T832	/workspace/coverage/default/1.chip_sw_flash_crash_alert.2925383637			Jun 07 09:50:14 PM PDT 24	Jun 07 10:00:36 PM PDT 24	5453035040 ps
T267	/workspace/coverage/default/1.chip_sw_rv_timer_irq.3880722500			Jun 07 09:43:19 PM PDT 24	Jun 07 09:47:04 PM PDT 24	2875309270 ps
T149	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.2493315909			Jun 07 09:40:28 PM PDT 24	Jun 07 10:47:32 PM PDT 24	19326421019 ps
T997	/workspace/coverage/default/2.chip_sw_kmac_idle.1578769466			Jun 07 09:58:25 PM PDT 24	Jun 07 10:04:01 PM PDT 24	3389225400 ps
T156	/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.310857105			Jun 07 09:43:46 PM PDT 24	Jun 07 10:14:50 PM PDT 24	13365995464 ps
T394	/workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.2218283367			Jun 07 10:01:57 PM PDT 24	Jun 07 10:04:36 PM PDT 24	2444159360 ps
T211	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.2258214269			Jun 07 09:40:18 PM PDT 24	Jun 07 09:49:12 PM PDT 24	4490453662 ps
T56	/workspace/coverage/default/1.chip_sw_alert_test.3117382751			Jun 07 09:46:30 PM PDT 24	Jun 07 09:51:43 PM PDT 24	2871252428 ps
T998	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1612629489			Jun 07 09:38:03 PM PDT 24	Jun 07 10:03:20 PM PDT 24	11467661508 ps
T999	/workspace/coverage/default/1.chip_sival_flash_info_access.1987544099			Jun 07 09:42:15 PM PDT 24	Jun 07 09:48:33 PM PDT 24	3771961432 ps
T1000	/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2865068777			Jun 07 10:06:31 PM PDT 24	Jun 07 10:28:35 PM PDT 24	8922222216 ps
T1001	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3715153724			Jun 07 09:49:23 PM PDT 24	Jun 07 10:00:01 PM PDT 24	4179742220 ps
T1002	/workspace/coverage/default/1.chip_sw_aes_smoketest.2712081100			Jun 07 09:53:32 PM PDT 24	Jun 07 09:59:10 PM PDT 24	3492263598 ps
T276	/workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.2558123898			Jun 07 09:44:00 PM PDT 24	Jun 07 10:02:54 PM PDT 24	5209393468 ps
T184	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.2565973139			Jun 07 09:57:32 PM PDT 24	Jun 07 10:03:45 PM PDT 24	3274830556 ps
T834	/workspace/coverage/default/49.chip_sw_all_escalation_resets.3552327814			Jun 07 10:10:38 PM PDT 24	Jun 07 10:20:10 PM PDT 24	5601469676 ps
T33	/workspace/coverage/default/0.chip_sw_usbdev_dpi.1810439922			Jun 07 09:36:34 PM PDT 24	Jun 07 10:25:41 PM PDT 24	11937199856 ps
T1003	/workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.1480002578			Jun 07 09:54:23 PM PDT 24	Jun 07 09:59:20 PM PDT 24	3154150480 ps
T48	/workspace/coverage/default/0.chip_sw_spi_device_tpm.2282200482			Jun 07 09:36:21 PM PDT 24	Jun 07 09:41:21 PM PDT 24	3495140708 ps
T1004	/workspace/coverage/default/0.chip_tap_straps_dev.3186134394			Jun 07 09:37:12 PM PDT 24	Jun 07 09:40:27 PM PDT 24	3065018172 ps
T843	/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.3476553136			Jun 07 10:15:59 PM PDT 24	Jun 07 10:21:04 PM PDT 24	3334176336 ps
T844	/workspace/coverage/default/11.chip_sw_all_escalation_resets.2350535378			Jun 07 10:07:32 PM PDT 24	Jun 07 10:19:15 PM PDT 24	4798108148 ps
T207	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.1250420902			Jun 07 09:37:35 PM PDT 24	Jun 07 10:03:54 PM PDT 24	7584312230 ps
T818	/workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.182446193			Jun 07 09:46:02 PM PDT 24	Jun 07 10:16:44 PM PDT 24	8036161260 ps
T1005	/workspace/coverage/default/2.chip_sw_otbn_randomness.1435770434			Jun 07 09:56:06 PM PDT 24	Jun 07 10:15:25 PM PDT 24	6535862328 ps
T126	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.3051779542			Jun 07 09:39:02 PM PDT 24	Jun 07 09:58:03 PM PDT 24	8519844714 ps
T1006	/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.1370598385			Jun 07 09:37:25 PM PDT 24	Jun 07 10:16:49 PM PDT 24	12563899720 ps
T1007	/workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.2600180441			Jun 07 09:36:54 PM PDT 24	Jun 07 09:42:48 PM PDT 24	3744827176 ps
T35	/workspace/coverage/default/0.chip_sw_gpio_smoketest.2775532365			Jun 07 09:39:41 PM PDT 24	Jun 07 09:44:52 PM PDT 24	2887457373 ps
T780	/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.1200320183			Jun 07 10:14:20 PM PDT 24	Jun 07 10:20:29 PM PDT 24	4309480650 ps
T821	/workspace/coverage/default/67.chip_sw_all_escalation_resets.842275181			Jun 07 10:13:27 PM PDT 24	Jun 07 10:22:00 PM PDT 24	5261551610 ps
T1008	/workspace/coverage/default/2.rom_keymgr_functest.936803256			Jun 07 10:02:30 PM PDT 24	Jun 07 10:13:38 PM PDT 24	4569204560 ps
T1009	/workspace/coverage/default/2.chip_sw_csrng_smoketest.3583540848			Jun 07 10:05:25 PM PDT 24	Jun 07 10:09:49 PM PDT 24	2492467176 ps
T1010	/workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.268047923			Jun 07 09:37:28 PM PDT 24	Jun 07 09:42:12 PM PDT 24	3050944650 ps
T274	/workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.2038627841			Jun 07 10:05:25 PM PDT 24	Jun 07 11:18:54 PM PDT 24	17453868604 ps
T1011	/workspace/coverage/default/1.chip_sw_edn_sw_mode.3772762885			Jun 07 09:47:38 PM PDT 24	Jun 07 10:16:31 PM PDT 24	7730390424 ps
T268	/workspace/coverage/default/2.chip_sw_rv_timer_irq.2513228789			Jun 07 09:55:39 PM PDT 24	Jun 07 09:59:45 PM PDT 24	3691741434 ps
T1012	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.2479962801			Jun 07 09:35:53 PM PDT 24	Jun 07 09:43:05 PM PDT 24	6172059250 ps
T226	/workspace/coverage/default/2.chip_sw_alert_handler_escalation.1424743727			Jun 07 10:01:25 PM PDT 24	Jun 07 10:11:25 PM PDT 24	5845057960 ps
T10	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.722260754			Jun 07 09:36:15 PM PDT 24	Jun 07 09:45:31 PM PDT 24	7369685080 ps
T113	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.1721386150			Jun 07 09:40:28 PM PDT 24	Jun 07 10:02:03 PM PDT 24	6800159018 ps
T361	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops.2274806175			Jun 07 09:43:50 PM PDT 24	Jun 07 09:55:04 PM PDT 24	4617860520 ps
T165	/workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.2711637566			Jun 07 09:54:18 PM PDT 24	Jun 07 11:21:27 PM PDT 24	49926013241 ps
T200	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.3745883368			Jun 07 09:45:05 PM PDT 24	Jun 07 09:55:03 PM PDT 24	5204830177 ps
T424	/workspace/coverage/default/1.chip_sw_example_manufacturer.1572358097			Jun 07 09:42:03 PM PDT 24	Jun 07 09:45:46 PM PDT 24	3019930216 ps
T425	/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.2581282795			Jun 07 10:09:23 PM PDT 24	Jun 07 10:14:52 PM PDT 24	3538282900 ps
T217	/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.3637361825			Jun 07 09:40:44 PM PDT 24	Jun 07 09:51:46 PM PDT 24	4738829222 ps
T426	/workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.3695527506			Jun 07 10:04:22 PM PDT 24	Jun 07 10:08:51 PM PDT 24	2948118664 ps
T427	/workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.2628964244			Jun 07 09:46:20 PM PDT 24	Jun 07 10:01:12 PM PDT 24	4463479140 ps
T7	/workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.3359844642			Jun 07 10:01:07 PM PDT 24	Jun 07 10:11:53 PM PDT 24	5055863016 ps
T176	/workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.2910799964			Jun 07 09:51:49 PM PDT 24	Jun 07 09:56:46 PM PDT 24	2486943240 ps
T52	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.82290541			Jun 07 09:44:36 PM PDT 24	Jun 07 10:36:35 PM PDT 24	13987127915 ps
T318	/workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.2685546073			Jun 07 09:44:59 PM PDT 24	Jun 07 09:57:30 PM PDT 24	5164458332 ps
T319	/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.1262158315			Jun 07 09:55:07 PM PDT 24	Jun 07 10:40:22 PM PDT 24	13654819574 ps
T229	/workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.2487297906			Jun 07 09:46:49 PM PDT 24	Jun 07 10:13:18 PM PDT 24	7069326362 ps
T23	/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.287561846			Jun 07 09:56:31 PM PDT 24	Jun 07 10:06:18 PM PDT 24	4541398677 ps
T320	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.3641338122			Jun 07 09:48:15 PM PDT 24	Jun 07 10:18:29 PM PDT 24	8198347114 ps
T321	/workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.4093218776			Jun 07 10:00:39 PM PDT 24	Jun 07 10:07:59 PM PDT 24	3594561584 ps
T322	/workspace/coverage/default/80.chip_sw_all_escalation_resets.3754160204			Jun 07 10:16:18 PM PDT 24	Jun 07 10:24:27 PM PDT 24	5468857670 ps
T323	/workspace/coverage/default/2.chip_sw_example_rom.2636086241			Jun 07 09:52:24 PM PDT 24	Jun 07 09:54:23 PM PDT 24	1893353576 ps
T1013	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1375070651			Jun 07 09:39:21 PM PDT 24	Jun 07 09:44:15 PM PDT 24	3254951234 ps
T444	/workspace/coverage/default/2.chip_sw_edn_entropy_reqs.2943225870			Jun 07 09:59:59 PM PDT 24	Jun 07 10:23:28 PM PDT 24	8320508996 ps
T256	/workspace/coverage/default/39.chip_sw_all_escalation_resets.3553991241			Jun 07 10:10:43 PM PDT 24	Jun 07 10:18:44 PM PDT 24	5466828684 ps
T1014	/workspace/coverage/default/0.chip_sw_kmac_smoketest.2097238790			Jun 07 09:43:19 PM PDT 24	Jun 07 09:48:34 PM PDT 24	2684277056 ps
T177	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.3668086241			Jun 07 09:38:58 PM PDT 24	Jun 07 09:46:22 PM PDT 24	3616609688 ps
T830	/workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.1695960964			Jun 07 09:40:50 PM PDT 24	Jun 07 09:47:59 PM PDT 24	3544586688 ps
T230	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.22896547			Jun 07 10:00:49 PM PDT 24	Jun 07 10:29:35 PM PDT 24	10820309594 ps
T1015	/workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.1168011198			Jun 07 09:37:18 PM PDT 24	Jun 07 09:46:29 PM PDT 24	3752660258 ps
T1016	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.2890430657			Jun 07 09:56:38 PM PDT 24	Jun 07 10:07:26 PM PDT 24	8558626296 ps
T127	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.3921165936			Jun 07 10:01:38 PM PDT 24	Jun 07 10:11:29 PM PDT 24	6708942122 ps
T1017	/workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.2003636701			Jun 07 09:40:16 PM PDT 24	Jun 07 09:52:27 PM PDT 24	5331884420 ps
T828	/workspace/coverage/default/17.chip_sw_all_escalation_resets.520863940			Jun 07 10:07:32 PM PDT 24	Jun 07 10:16:33 PM PDT 24	6309723880 ps
T395	/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.2031369695			Jun 07 09:40:27 PM PDT 24	Jun 07 09:45:23 PM PDT 24	2473974718 ps
T235	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.3783904210			Jun 07 09:44:16 PM PDT 24	Jun 07 10:04:11 PM PDT 24	6260473186 ps
T1018	/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.3055983449			Jun 07 10:06:29 PM PDT 24	Jun 07 10:17:13 PM PDT 24	5088593161 ps
T885	/workspace/coverage/default/81.chip_sw_all_escalation_resets.1827368666			Jun 07 10:15:35 PM PDT 24	Jun 07 10:23:26 PM PDT 24	4883203184 ps
T57	/workspace/coverage/default/0.chip_sw_alert_test.46975938			Jun 07 09:38:44 PM PDT 24	Jun 07 09:43:18 PM PDT 24	2866101020 ps
T368	/workspace/coverage/default/24.chip_sw_all_escalation_resets.3865074737			Jun 07 10:08:15 PM PDT 24	Jun 07 10:17:17 PM PDT 24	5039857924 ps
T367	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.640828343			Jun 07 09:42:18 PM PDT 24	Jun 07 09:53:39 PM PDT 24	3907915814 ps
T24	/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.1130394335			Jun 07 09:35:15 PM PDT 24	Jun 07 09:39:09 PM PDT 24	3300229700 ps
T25	/workspace/coverage/default/1.chip_sw_spi_device_pass_through.3975887372			Jun 07 09:41:02 PM PDT 24	Jun 07 09:53:58 PM PDT 24	7610150545 ps