Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.gpio_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	128330	1			T73	128		T74	1		T78	24
values[2]	7029	1			T73	1		T262	2		T557	4
values[3]	2302	1			T557	1		T836	1		T555	2
values[4]	1365	1			T836	1		T555	1		T634	5
values[5]	1018	1			T836	1		T555	1		T634	2
values[6]	833	1			T836	1		T555	1		T496	12
values[7]	630	1			T836	1		T555	1		T496	12
values[8]	521	1			T836	1		T555	1		T496	2
values[9]	495	1			T836	1		T555	1		T496	7
values[10]	429	1			T836	1		T555	1		T496	5
values[11]	451	1			T836	1		T555	1		T496	10
values[12]	424	1			T836	1		T555	1		T496	9
values[13]	442	1			T836	1		T555	1		T496	4
values[14]	405	1			T836	1		T555	1		T496	4
values[15]	360	1			T836	1		T555	1		T496	5
values[16]	356	1			T836	1		T555	1		T496	15
values[17]	344	1			T836	1		T555	1		T496	6
values[18]	328	1			T836	1		T555	1		T496	6
values[19]	336	1			T836	1		T555	1		T496	2
values[20]	328	1			T836	1		T555	1		T496	8
values[21]	335	1			T836	1		T555	1		T496	16
values[22]	329	1			T836	2		T555	1		T496	6
values[23]	310	1			T836	1		T555	1		T496	4
values[24]	377	1			T836	1		T555	1		T496	5
values[25]	319	1			T836	1		T555	1		T496	4
values[26]	314	1			T836	1		T555	2		T496	8
values[27]	330	1			T836	1		T555	1		T496	7
values[28]	337	1			T836	1		T555	1		T496	12
values[29]	316	1			T836	1		T555	1		T496	6
values[30]	363	1			T836	1		T555	1		T496	5
values[31]	321	1			T836	1		T555	1		T496	5
values[32]	316	1			T836	1		T555	1		T496	3
values[33]	323	1			T836	1		T555	1		T496	4
values[34]	315	1			T836	1		T555	1		T496	10
values[35]	353	1			T836	1		T555	1		T496	14
values[36]	322	1			T836	1		T555	1		T496	28
values[37]	318	1			T836	1		T555	1		T496	13
values[38]	333	1			T836	1		T555	1		T496	6
values[39]	337	1			T836	1		T555	1		T496	6
values[40]	347	1			T836	1		T555	1		T496	4
values[41]	333	1			T836	1		T555	1		T496	2
values[42]	359	1			T836	1		T555	1		T496	6
values[43]	347	1			T836	1		T555	1		T496	17
values[44]	277	1			T836	1		T555	1		T496	5
values[45]	287	1			T836	1		T555	1		T496	4
values[46]	276	1			T836	1		T555	1		T496	4
values[47]	366	1			T836	2		T555	1		T496	13
values[48]	299	1			T836	1		T555	1		T496	3
values[49]	266	1			T836	1		T555	1		T496	5
values[50]	287	1			T836	1		T555	1		T496	5
values[51]	262	1			T836	1		T555	1		T496	6
values[52]	264	1			T836	1		T555	1		T496	4
values[53]	278	1			T836	1		T555	1		T496	6
values[54]	274	1			T836	1		T555	1		T496	18
values[55]	265	1			T836	1		T555	1		T496	13
values[56]	232	1			T836	1		T555	1		T496	11
values[57]	252	1			T836	2		T555	1		T496	7
values[58]	240	1			T836	1		T555	1		T496	7
values[59]	250	1			T836	1		T555	1		T496	8
values[60]	194	1			T836	1		T555	1		T496	3
values[61]	200	1			T836	1		T555	1		T496	6
values[62]	211	1			T836	1		T555	1		T496	5
values[63]	182	1			T836	1		T555	1		T496	10
values[64]	181	1			T836	1		T555	1		T496	3
values[65]	137	1			T836	1		T555	1		T496	4
values[66]	128	1			T836	1		T555	1		T496	5
values[67]	140	1			T836	1		T555	1		T496	3
values[68]	153	1			T836	1		T555	1		T496	10
values[69]	147	1			T836	1		T555	1		T496	9
values[70]	128	1			T836	1		T555	1		T496	9
values[71]	93	1			T836	1		T555	1		T496	2
values[72]	116	1			T836	1		T555	1		T770	5
values[73]	119	1			T836	1		T555	1		T770	6
values[74]	86	1			T836	1		T555	1		T770	4
values[75]	77	1			T836	1		T555	1		T433	1
values[76]	74	1			T836	1		T555	1		T433	1
values[77]	84	1			T836	1		T555	1		T433	1
values[78]	105	1			T836	1		T555	1		T433	1
values[79]	82	1			T836	1		T555	1		T433	1
values[80]	76	1			T836	1		T555	1		T433	1
values[81]	74	1			T836	1		T555	1		T433	1
values[82]	67	1			T836	1		T555	1		T433	1
values[83]	54	1			T836	1		T555	1		T433	1
values[84]	58	1			T836	1		T555	1		T433	1
values[85]	63	1			T836	1		T555	1		T433	1
values[86]	73	1			T836	1		T555	1		T433	1
values[87]	60	1			T836	1		T555	1		T433	1
values[88]	54	1			T836	1		T555	1		T433	1
values[89]	74	1			T836	1		T555	1		T433	1
values[90]	81	1			T836	1		T555	1		T433	1
values[91]	70	1			T836	1		T555	1		T433	1
values[92]	52	1			T836	1		T555	1		T433	1
values[93]	56	1			T836	1		T555	1		T433	1
values[94]	69	1			T836	1		T555	1		T433	2
values[95]	87	1			T836	1		T555	1		T433	3
values[96]	68	1			T836	1		T555	1		T433	1
values[97]	63	1			T836	1		T555	1		T433	2
values[98]	70	1			T836	1		T555	1		T433	3
values[99]	62	1			T836	1		T555	1		T433	2
values[100]	66	1			T836	1		T555	1		T433	2
values[101]	58	1			T836	1		T555	1		T433	2
values[102]	63	1			T836	1		T555	1		T433	1
values[103]	56	1			T836	1		T555	1		T433	3
values[104]	70	1			T836	1		T555	3		T433	1
values[105]	61	1			T836	1		T555	7		T433	3
values[106]	56	1			T836	1		T555	10		T433	3
values[107]	63	1			T836	1		T555	2		T433	3
values[108]	63	1			T836	1		T555	1		T433	5
values[109]	47	1			T836	1		T555	1		T433	2
values[110]	59	1			T836	1		T555	3		T433	6
values[111]	53	1			T836	1		T555	3		T433	4
values[112]	87	1			T836	1		T555	6		T433	4
values[113]	58	1			T836	1		T555	3		T433	4
values[114]	43	1			T836	4		T555	1		T433	1
values[115]	63	1			T836	2		T555	2		T433	2
values[116]	49	1			T836	1		T555	1		T433	2
values[117]	40	1			T836	5		T555	2		T433	1
values[118]	45	1			T836	1		T555	5		T433	1
values[119]	45	1			T836	1		T555	1		T433	5
values[120]	42	1			T836	1		T555	1		T433	3
values[121]	45	1			T836	3		T555	2		T433	5
values[122]	34	1			T836	1		T555	5		T433	1
values[123]	52	1			T836	3		T555	3		T433	5
values[124]	44	1			T836	1		T555	2		T433	1
values[125]	77	1			T836	2		T555	1		T433	1
values[126]	116	1			T836	4		T555	5		T433	2
values[127]	719	1			T836	29		T555	35		T433	38
values[128]	5182	1			T836	271		T555	276		T433	277