Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.i2c2_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	130796	1			T73	141		T74	1		T78	11
values[2]	8454	1			T73	8		T262	4		T549	1
values[3]	3005	1			T836	2		T555	1		T432	5
values[4]	1872	1			T836	1		T555	1		T432	5
values[5]	1197	1			T836	1		T555	1		T432	6
values[6]	845	1			T836	1		T555	1		T432	4
values[7]	629	1			T836	1		T555	1		T432	3
values[8]	499	1			T836	1		T555	1		T432	5
values[9]	389	1			T836	1		T555	1		T432	11
values[10]	298	1			T836	1		T555	1		T432	4
values[11]	297	1			T836	1		T555	1		T432	9
values[12]	273	1			T836	1		T555	1		T432	4
values[13]	292	1			T836	1		T555	1		T432	4
values[14]	288	1			T836	1		T555	1		T432	5
values[15]	323	1			T836	1		T555	1		T432	6
values[16]	319	1			T836	1		T555	1		T432	9
values[17]	291	1			T836	1		T555	1		T432	3
values[18]	294	1			T836	1		T555	1		T432	2
values[19]	330	1			T836	1		T555	1		T432	1
values[20]	249	1			T836	1		T555	1		T432	5
values[21]	244	1			T836	1		T555	1		T432	2
values[22]	235	1			T836	1		T555	1		T432	5
values[23]	239	1			T836	1		T555	1		T432	4
values[24]	327	1			T836	1		T555	1		T432	6
values[25]	264	1			T836	1		T555	1		T432	3
values[26]	254	1			T836	1		T555	1		T432	2
values[27]	248	1			T836	1		T555	1		T432	7
values[28]	236	1			T836	1		T555	1		T432	4
values[29]	274	1			T836	1		T555	1		T432	2
values[30]	298	1			T836	1		T555	1		T432	2
values[31]	243	1			T836	1		T555	1		T432	1
values[32]	255	1			T836	1		T555	1		T432	1
values[33]	227	1			T836	1		T555	1		T432	3
values[34]	254	1			T836	1		T555	1		T432	3
values[35]	239	1			T836	1		T555	1		T432	5
values[36]	219	1			T836	1		T555	1		T432	2
values[37]	236	1			T836	1		T555	1		T432	1
values[38]	248	1			T836	1		T555	1		T432	2
values[39]	253	1			T836	1		T555	1		T432	2
values[40]	182	1			T836	1		T555	1		T432	2
values[41]	198	1			T836	1		T555	1		T432	5
values[42]	235	1			T836	1		T555	1		T432	6
values[43]	247	1			T836	1		T555	1		T432	6
values[44]	216	1			T836	2		T555	1		T432	5
values[45]	229	1			T836	1		T555	1		T432	1
values[46]	230	1			T836	1		T555	1		T432	1
values[47]	233	1			T836	1		T555	1		T432	1
values[48]	234	1			T836	1		T555	1		T432	6
values[49]	215	1			T836	1		T555	1		T432	7
values[50]	219	1			T836	1		T555	1		T432	5
values[51]	200	1			T836	1		T555	1		T432	2
values[52]	194	1			T836	1		T555	1		T432	2
values[53]	187	1			T836	1		T555	1		T432	1
values[54]	176	1			T836	1		T555	1		T432	4
values[55]	206	1			T836	1		T555	1		T432	1
values[56]	225	1			T836	1		T555	1		T432	2
values[57]	261	1			T836	1		T555	1		T432	2
values[58]	209	1			T836	1		T555	1		T432	2
values[59]	189	1			T836	1		T555	1		T432	2
values[60]	204	1			T836	1		T555	1		T432	2
values[61]	226	1			T836	1		T555	1		T432	3
values[62]	185	1			T836	1		T555	1		T432	2
values[63]	156	1			T836	1		T555	1		T432	1
values[64]	162	1			T836	1		T555	1		T432	2
values[65]	147	1			T836	1		T555	1		T432	3
values[66]	158	1			T836	1		T555	1		T432	5
values[67]	146	1			T836	1		T555	1		T432	1
values[68]	107	1			T836	1		T555	1		T432	2
values[69]	119	1			T836	1		T555	1		T458	1
values[70]	132	1			T836	1		T555	1		T458	1
values[71]	100	1			T836	1		T555	1		T458	1
values[72]	88	1			T836	1		T555	1		T458	1
values[73]	118	1			T836	1		T555	1		T458	1
values[74]	115	1			T836	1		T555	1		T458	1
values[75]	111	1			T836	1		T555	1		T458	1
values[76]	103	1			T836	1		T555	1		T458	1
values[77]	106	1			T836	1		T555	1		T458	1
values[78]	94	1			T836	1		T555	1		T458	1
values[79]	79	1			T836	1		T555	1		T458	1
values[80]	102	1			T836	1		T555	1		T458	1
values[81]	125	1			T836	1		T555	1		T458	1
values[82]	96	1			T836	1		T555	1		T458	1
values[83]	84	1			T836	1		T555	1		T458	1
values[84]	97	1			T836	1		T555	1		T458	1
values[85]	89	1			T836	1		T555	1		T458	1
values[86]	101	1			T836	1		T555	1		T458	1
values[87]	99	1			T836	1		T555	1		T458	1
values[88]	103	1			T836	1		T555	1		T458	1
values[89]	123	1			T836	1		T555	1		T458	1
values[90]	116	1			T836	1		T555	2		T458	1
values[91]	89	1			T836	1		T555	2		T458	1
values[92]	94	1			T836	1		T555	3		T458	1
values[93]	80	1			T836	1		T555	5		T458	1
values[94]	132	1			T836	1		T555	11		T458	1
values[95]	101	1			T836	1		T555	3		T458	1
values[96]	111	1			T836	1		T555	6		T458	1
values[97]	106	1			T836	1		T555	1		T458	1
values[98]	127	1			T836	1		T555	2		T458	1
values[99]	114	1			T836	1		T555	1		T458	1
values[100]	88	1			T836	1		T555	1		T458	1
values[101]	97	1			T836	1		T555	3		T458	1
values[102]	95	1			T836	1		T555	1		T458	1
values[103]	104	1			T836	1		T555	1		T458	1
values[104]	85	1			T836	1		T555	9		T458	1
values[105]	98	1			T836	3		T555	1		T458	1
values[106]	103	1			T836	3		T555	1		T458	1
values[107]	107	1			T836	2		T555	1		T458	1
values[108]	101	1			T836	2		T555	1		T458	1
values[109]	87	1			T836	2		T555	3		T458	1
values[110]	94	1			T836	2		T555	2		T458	1
values[111]	81	1			T836	1		T555	1		T458	1
values[112]	78	1			T836	4		T555	1		T458	1
values[113]	64	1			T836	1		T555	2		T458	1
values[114]	83	1			T836	1		T555	2		T458	2
values[115]	81	1			T836	1		T555	2		T458	1
values[116]	98	1			T836	2		T555	5		T458	3
values[117]	89	1			T836	6		T555	3		T458	1
values[118]	101	1			T836	4		T555	1		T458	1
values[119]	103	1			T836	3		T555	3		T458	5
values[120]	90	1			T836	3		T555	3		T458	3
values[121]	81	1			T836	3		T555	1		T458	1
values[122]	65	1			T836	1		T555	1		T458	2
values[123]	74	1			T836	1		T555	1		T458	4
values[124]	70	1			T836	1		T555	1		T458	1
values[125]	102	1			T836	3		T555	1		T458	1
values[126]	230	1			T836	1		T555	2		T458	4
values[127]	1213	1			T836	39		T555	29		T458	31
values[128]	7998	1			T836	293		T555	287		T458	250