Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.lc_ctrl_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	133766	1			T73	132		T74	3		T78	13
values[2]	9349	1			T73	1		T262	1		T557	3
values[3]	3477	1			T553	1		T555	1		T446	9
values[4]	2035	1			T553	1		T555	1		T446	4
values[5]	1311	1			T553	1		T555	1		T446	1
values[6]	906	1			T553	1		T555	1		T782	1
values[7]	740	1			T553	1		T555	1		T782	1
values[8]	562	1			T553	1		T555	1		T782	3
values[9]	511	1			T553	1		T555	1		T782	5
values[10]	400	1			T553	1		T555	1		T782	2
values[11]	415	1			T553	1		T555	1		T782	3
values[12]	388	1			T553	1		T555	1		T782	4
values[13]	323	1			T553	1		T555	1		T782	9
values[14]	370	1			T553	1		T555	1		T782	5
values[15]	368	1			T553	1		T555	1		T782	5
values[16]	284	1			T553	1		T555	1		T782	3
values[17]	297	1			T553	1		T555	1		T782	1
values[18]	319	1			T553	1		T555	1		T782	6
values[19]	286	1			T553	1		T555	1		T782	3
values[20]	314	1			T553	1		T555	1		T782	3
values[21]	257	1			T553	1		T555	1		T782	1
values[22]	274	1			T553	1		T555	1		T782	1
values[23]	273	1			T553	1		T555	1		T782	1
values[24]	234	1			T553	1		T555	1		T782	3
values[25]	244	1			T553	1		T555	1		T782	2
values[26]	271	1			T553	1		T555	1		T782	1
values[27]	312	1			T553	1		T555	1		T782	5
values[28]	299	1			T553	1		T555	1		T782	11
values[29]	329	1			T553	1		T555	1		T782	4
values[30]	275	1			T553	1		T555	1		T782	1
values[31]	249	1			T553	1		T555	1		T782	2
values[32]	253	1			T553	1		T555	1		T782	2
values[33]	261	1			T553	1		T555	1		T782	3
values[34]	240	1			T553	1		T555	1		T782	5
values[35]	247	1			T553	1		T555	1		T782	2
values[36]	268	1			T553	1		T555	1		T782	1
values[37]	235	1			T553	1		T555	1		T782	2
values[38]	259	1			T553	1		T555	1		T782	2
values[39]	234	1			T553	1		T555	1		T782	2
values[40]	271	1			T553	1		T555	1		T782	1
values[41]	245	1			T553	1		T555	1		T782	1
values[42]	300	1			T553	1		T555	1		T782	2
values[43]	277	1			T553	1		T555	1		T782	11
values[44]	276	1			T553	1		T555	1		T782	2
values[45]	228	1			T553	1		T555	1		T782	1
values[46]	252	1			T553	1		T555	1		T782	2
values[47]	212	1			T553	1		T555	1		T782	1
values[48]	269	1			T553	2		T555	1		T782	3
values[49]	273	1			T553	1		T555	1		T782	1
values[50]	287	1			T553	1		T555	1		T782	2
values[51]	241	1			T553	1		T555	1		T782	5
values[52]	193	1			T553	1		T555	1		T782	2
values[53]	213	1			T553	1		T555	1		T782	2
values[54]	217	1			T553	1		T555	1		T782	1
values[55]	213	1			T553	1		T555	1		T782	2
values[56]	243	1			T553	1		T555	1		T782	7
values[57]	185	1			T553	1		T555	1		T782	5
values[58]	207	1			T553	1		T555	1		T782	6
values[59]	213	1			T553	1		T555	1		T782	1
values[60]	191	1			T553	1		T555	1		T782	3
values[61]	178	1			T553	1		T555	1		T782	3
values[62]	181	1			T553	1		T555	1		T782	4
values[63]	170	1			T553	1		T555	1		T782	1
values[64]	151	1			T553	1		T555	1		T782	4
values[65]	169	1			T553	1		T555	1		T782	9
values[66]	135	1			T553	1		T555	1		T782	3
values[67]	125	1			T553	1		T555	1		T782	3
values[68]	161	1			T553	1		T555	1		T782	2
values[69]	156	1			T553	1		T555	1		T782	1
values[70]	136	1			T553	1		T555	1		T782	2
values[71]	111	1			T553	1		T555	1		T782	1
values[72]	116	1			T553	1		T555	1		T782	3
values[73]	92	1			T553	1		T555	1		T782	1
values[74]	69	1			T553	1		T555	1		T782	3
values[75]	77	1			T553	1		T555	1		T782	1
values[76]	71	1			T553	1		T555	1		T782	2
values[77]	96	1			T553	1		T555	1		T782	1
values[78]	68	1			T553	1		T555	1		T782	11
values[79]	62	1			T553	1		T555	1		T782	9
values[80]	81	1			T553	1		T555	1		T782	15
values[81]	58	1			T553	1		T555	1		T782	8
values[82]	70	1			T553	1		T555	1		T782	4
values[83]	77	1			T553	1		T555	1		T782	6
values[84]	74	1			T553	1		T555	1		T782	7
values[85]	70	1			T553	1		T555	1		T782	5
values[86]	52	1			T553	1		T555	1		T782	1
values[87]	69	1			T553	1		T555	1		T782	1
values[88]	66	1			T553	1		T555	1		T782	3
values[89]	65	1			T553	1		T555	1		T782	2
values[90]	80	1			T553	1		T555	1		T782	3
values[91]	76	1			T553	1		T555	1		T782	6
values[92]	59	1			T553	1		T555	1		T782	3
values[93]	48	1			T553	1		T555	1		T782	2
values[94]	69	1			T553	1		T555	4		T782	1
values[95]	84	1			T553	1		T555	1		T782	2
values[96]	84	1			T553	1		T555	4		T782	2
values[97]	63	1			T553	1		T555	1		T782	3
values[98]	51	1			T553	1		T555	1		T782	1
values[99]	57	1			T553	1		T555	1		T782	1
values[100]	64	1			T553	1		T555	5		T782	2
values[101]	64	1			T553	1		T555	10		T782	5
values[102]	61	1			T553	1		T555	4		T782	1
values[103]	59	1			T553	1		T555	1		T782	4
values[104]	72	1			T553	1		T555	8		T782	3
values[105]	48	1			T553	1		T555	1		T782	2
values[106]	66	1			T553	2		T555	3		T782	2
values[107]	61	1			T553	1		T555	2		T782	4
values[108]	59	1			T553	1		T555	4		T782	3
values[109]	77	1			T553	1		T555	2		T782	6
values[110]	100	1			T553	1		T555	2		T782	6
values[111]	73	1			T553	1		T555	2		T782	1
values[112]	71	1			T553	1		T555	2		T782	4
values[113]	68	1			T553	1		T555	1		T782	1
values[114]	56	1			T553	1		T555	2		T782	1
values[115]	48	1			T553	1		T555	1		T782	1
values[116]	42	1			T553	1		T555	1		T782	2
values[117]	54	1			T553	1		T555	4		T782	5
values[118]	57	1			T553	1		T555	1		T782	11
values[119]	47	1			T553	1		T555	1		T782	3
values[120]	54	1			T553	1		T555	1		T782	8
values[121]	53	1			T553	1		T555	1		T782	1
values[122]	41	1			T553	1		T555	1		T782	1
values[123]	50	1			T553	1		T555	2		T782	1
values[124]	62	1			T553	1		T555	3		T782	5
values[125]	54	1			T553	1		T555	4		T782	5
values[126]	100	1			T553	1		T555	3		T782	27
values[127]	770	1			T553	34		T555	24		T782	61
values[128]	6159	1			T553	277		T555	310		T782	30