Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.otbn_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	157313	1			T73	146		T74	4		T78	18
values[2]	4209	1			T73	2		T262	5		T557	5
values[3]	2210	1			T836	1		T561	1		T553	1
values[4]	1738	1			T836	1		T553	1		T555	2
values[5]	1499	1			T836	1		T553	1		T555	2
values[6]	1233	1			T836	1		T553	1		T555	2
values[7]	1044	1			T836	1		T553	1		T555	2
values[8]	867	1			T836	1		T553	1		T555	2
values[9]	804	1			T836	1		T553	1		T555	2
values[10]	681	1			T836	1		T553	1		T555	2
values[11]	596	1			T836	1		T553	1		T555	2
values[12]	516	1			T836	1		T553	1		T555	2
values[13]	389	1			T836	1		T553	1		T555	2
values[14]	349	1			T836	1		T553	1		T555	2
values[15]	274	1			T836	1		T553	1		T555	2
values[16]	291	1			T836	1		T553	1		T555	2
values[17]	317	1			T836	1		T553	1		T555	2
values[18]	316	1			T836	1		T553	1		T555	2
values[19]	290	1			T836	1		T553	1		T555	2
values[20]	279	1			T836	1		T553	1		T555	2
values[21]	295	1			T836	1		T553	1		T555	2
values[22]	427	1			T836	1		T553	1		T555	2
values[23]	407	1			T836	1		T553	1		T555	2
values[24]	369	1			T836	1		T553	1		T555	2
values[25]	318	1			T836	1		T553	1		T555	2
values[26]	253	1			T836	1		T553	1		T555	2
values[27]	234	1			T836	1		T553	1		T555	2
values[28]	210	1			T836	1		T553	1		T555	2
values[29]	269	1			T836	1		T553	1		T555	2
values[30]	266	1			T836	1		T553	1		T555	2
values[31]	254	1			T836	1		T553	1		T555	2
values[32]	205	1			T836	1		T553	1		T555	2
values[33]	212	1			T836	1		T553	1		T555	2
values[34]	230	1			T836	1		T553	1		T555	2
values[35]	241	1			T836	1		T553	1		T555	3
values[36]	256	1			T836	1		T553	1		T555	2
values[37]	218	1			T836	1		T553	1		T555	2
values[38]	179	1			T836	1		T553	1		T555	2
values[39]	171	1			T836	1		T553	1		T555	2
values[40]	137	1			T836	1		T553	1		T555	2
values[41]	104	1			T836	1		T553	1		T555	2
values[42]	83	1			T836	1		T553	1		T555	2
values[43]	90	1			T836	1		T553	1		T555	2
values[44]	86	1			T836	1		T553	1		T555	2
values[45]	92	1			T836	1		T553	1		T555	2
values[46]	93	1			T836	1		T553	1		T555	2
values[47]	106	1			T836	1		T553	1		T555	2
values[48]	88	1			T836	1		T553	1		T555	2
values[49]	80	1			T836	1		T553	1		T555	2
values[50]	91	1			T836	1		T553	1		T555	2
values[51]	109	1			T836	1		T553	1		T555	2
values[52]	90	1			T836	1		T553	1		T555	2
values[53]	97	1			T836	1		T553	1		T555	2
values[54]	111	1			T836	1		T553	1		T555	2
values[55]	104	1			T836	1		T553	1		T555	2
values[56]	88	1			T836	1		T553	1		T555	2
values[57]	86	1			T836	1		T553	1		T555	2
values[58]	94	1			T836	1		T553	1		T555	2
values[59]	88	1			T836	1		T553	2		T555	2
values[60]	87	1			T836	1		T553	1		T555	2
values[61]	80	1			T836	1		T553	1		T555	2
values[62]	89	1			T836	1		T553	1		T555	2
values[63]	72	1			T836	1		T553	1		T555	2
values[64]	63	1			T836	1		T553	1		T555	2
values[65]	61	1			T836	1		T553	1		T555	2
values[66]	52	1			T836	2		T553	1		T555	2
values[67]	54	1			T836	1		T553	1		T555	2
values[68]	48	1			T836	1		T553	1		T555	2
values[69]	59	1			T836	1		T553	1		T555	2
values[70]	49	1			T836	1		T553	1		T555	2
values[71]	72	1			T836	1		T553	1		T555	2
values[72]	70	1			T836	1		T553	5		T555	2
values[73]	81	1			T836	1		T553	9		T555	2
values[74]	64	1			T836	1		T553	3		T555	2
values[75]	57	1			T836	1		T553	3		T555	2
values[76]	59	1			T836	1		T553	2		T555	2
values[77]	62	1			T836	1		T553	2		T555	2
values[78]	83	1			T836	1		T553	5		T555	2
values[79]	85	1			T836	1		T553	3		T555	2
values[80]	71	1			T836	1		T553	9		T555	2
values[81]	59	1			T836	1		T553	2		T555	2
values[82]	70	1			T836	1		T553	4		T555	2
values[83]	74	1			T836	1		T553	6		T555	2
values[84]	60	1			T836	1		T553	2		T555	2
values[85]	83	1			T836	1		T553	1		T555	2
values[86]	90	1			T836	1		T553	2		T555	2
values[87]	71	1			T836	1		T553	6		T555	2
values[88]	74	1			T836	1		T553	2		T555	2
values[89]	85	1			T836	1		T553	3		T555	2
values[90]	75	1			T836	1		T553	3		T555	2
values[91]	87	1			T836	1		T553	2		T555	2
values[92]	79	1			T836	1		T553	2		T555	2
values[93]	79	1			T836	1		T553	6		T555	2
values[94]	88	1			T836	1		T553	1		T555	2
values[95]	87	1			T836	1		T553	1		T555	2
values[96]	92	1			T836	1		T553	2		T555	2
values[97]	100	1			T836	2		T553	1		T555	2
values[98]	87	1			T836	4		T553	2		T555	2
values[99]	92	1			T836	1		T553	3		T555	2
values[100]	66	1			T836	3		T553	2		T555	2
values[101]	70	1			T836	1		T553	1		T555	4
values[102]	87	1			T836	2		T553	3		T555	3
values[103]	79	1			T836	3		T553	1		T555	10
values[104]	97	1			T836	1		T553	1		T555	6
values[105]	89	1			T836	1		T553	1		T555	2
values[106]	94	1			T836	3		T553	1		T555	4
values[107]	102	1			T836	1		T553	2		T555	6
values[108]	110	1			T836	4		T553	1		T555	2
values[109]	106	1			T836	2		T553	1		T555	3
values[110]	94	1			T836	1		T553	1		T555	6
values[111]	102	1			T836	3		T553	1		T555	8
values[112]	83	1			T836	3		T553	1		T555	4
values[113]	86	1			T836	8		T553	1		T555	3
values[114]	95	1			T836	3		T553	2		T555	3
values[115]	73	1			T836	3		T553	1		T555	4
values[116]	108	1			T836	1		T553	2		T555	4
values[117]	98	1			T836	1		T553	1		T555	3
values[118]	98	1			T836	3		T553	1		T555	2
values[119]	104	1			T836	2		T553	1		T555	4
values[120]	119	1			T836	2		T553	4		T555	5
values[121]	108	1			T836	3		T553	5		T555	4
values[122]	123	1			T836	6		T553	5		T555	5
values[123]	121	1			T836	4		T553	4		T555	3
values[124]	211	1			T836	1		T553	3		T555	4
values[125]	456	1			T836	2		T553	1		T555	4
values[126]	907	1			T836	19		T553	11		T555	27
values[127]	2011	1			T836	103		T553	95		T555	207
values[128]	3128	1			T836	182		T553	172		T555	461