Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.aon_timer_aon_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	132579	1			T73	505		T74	4		T78	12
values[2]	8762	1			T73	78		T557	4		T550	1
values[3]	3329	1			T73	10		T555	1		T446	37
values[4]	1907	1			T73	5		T555	1		T446	3
values[5]	1283	1			T73	3		T555	1		T432	2
values[6]	836	1			T73	3		T555	1		T432	1
values[7]	587	1			T73	3		T555	1		T432	3
values[8]	456	1			T73	1		T555	1		T432	2
values[9]	407	1			T73	4		T555	1		T432	1
values[10]	332	1			T73	2		T555	1		T432	3
values[11]	308	1			T73	5		T555	1		T432	3
values[12]	337	1			T73	1		T555	1		T432	3
values[13]	319	1			T73	4		T555	1		T432	3
values[14]	294	1			T73	3		T555	1		T432	3
values[15]	292	1			T73	1		T555	1		T432	8
values[16]	300	1			T73	3		T555	1		T432	2
values[17]	270	1			T73	3		T555	1		T432	2
values[18]	282	1			T73	5		T555	1		T432	4
values[19]	296	1			T73	6		T555	1		T432	9
values[20]	301	1			T73	1		T555	1		T432	6
values[21]	272	1			T555	1		T432	15		T496	15
values[22]	332	1			T555	1		T432	2		T496	25
values[23]	252	1			T555	1		T432	3		T496	21
values[24]	258	1			T555	1		T432	5		T496	10
values[25]	257	1			T555	1		T432	4		T496	8
values[26]	236	1			T555	1		T432	1		T496	13
values[27]	258	1			T555	1		T432	4		T496	18
values[28]	282	1			T555	1		T432	3		T496	23
values[29]	207	1			T555	1		T432	2		T496	15
values[30]	250	1			T555	1		T432	2		T496	7
values[31]	234	1			T555	1		T432	4		T496	16
values[32]	265	1			T555	1		T432	3		T496	12
values[33]	262	1			T555	1		T432	5		T496	10
values[34]	223	1			T555	1		T432	2		T496	20
values[35]	247	1			T555	1		T432	1		T496	20
values[36]	276	1			T555	1		T432	3		T496	10
values[37]	236	1			T555	1		T432	3		T496	10
values[38]	222	1			T555	1		T432	1		T496	9
values[39]	269	1			T555	1		T432	1		T496	28
values[40]	281	1			T555	1		T432	2		T496	14
values[41]	252	1			T555	1		T432	1		T496	21
values[42]	229	1			T555	1		T432	2		T496	11
values[43]	283	1			T555	1		T432	1		T496	22
values[44]	249	1			T555	1		T432	3		T496	21
values[45]	225	1			T555	1		T432	4		T496	6
values[46]	212	1			T555	1		T432	2		T496	10
values[47]	245	1			T555	1		T432	2		T496	11
values[48]	233	1			T555	1		T432	1		T496	15
values[49]	202	1			T555	1		T432	2		T496	19
values[50]	201	1			T555	1		T432	1		T496	19
values[51]	216	1			T555	1		T432	6		T496	24
values[52]	242	1			T555	1		T432	3		T496	14
values[53]	220	1			T555	1		T432	2		T496	10
values[54]	223	1			T555	1		T432	3		T496	14
values[55]	232	1			T555	1		T432	2		T496	23
values[56]	207	1			T555	1		T432	1		T496	10
values[57]	203	1			T555	1		T432	6		T496	7
values[58]	237	1			T555	1		T432	10		T496	19
values[59]	237	1			T555	1		T432	8		T496	21
values[60]	223	1			T555	1		T432	2		T496	16
values[61]	223	1			T555	1		T432	3		T496	14
values[62]	156	1			T555	1		T432	2		T496	13
values[63]	139	1			T555	1		T432	2		T496	15
values[64]	125	1			T555	1		T432	4		T496	9
values[65]	144	1			T555	1		T432	3		T496	21
values[66]	151	1			T555	1		T432	5		T496	25
values[67]	144	1			T555	1		T432	10		T496	16
values[68]	78	1			T555	1		T432	1		T496	4
values[69]	76	1			T555	1		T432	2		T433	1
values[70]	81	1			T555	1		T432	2		T433	1
values[71]	100	1			T555	1		T432	2		T433	1
values[72]	90	1			T555	1		T432	4		T433	1
values[73]	73	1			T555	1		T432	2		T433	1
values[74]	68	1			T555	1		T432	2		T433	1
values[75]	55	1			T555	1		T432	4		T433	1
values[76]	53	1			T555	1		T432	2		T433	1
values[77]	72	1			T555	1		T432	14		T433	1
values[78]	56	1			T555	1		T432	7		T433	1
values[79]	60	1			T555	1		T432	10		T433	1
values[80]	68	1			T555	2		T432	2		T433	1
values[81]	69	1			T555	1		T432	3		T433	1
values[82]	67	1			T555	1		T432	1		T433	1
values[83]	63	1			T555	1		T432	7		T433	1
values[84]	56	1			T555	1		T432	6		T433	1
values[85]	66	1			T555	1		T432	2		T433	1
values[86]	79	1			T555	6		T432	4		T433	1
values[87]	65	1			T555	1		T432	6		T433	1
values[88]	57	1			T555	4		T432	1		T433	1
values[89]	78	1			T555	11		T432	6		T433	2
values[90]	60	1			T555	3		T432	6		T433	1
values[91]	68	1			T555	2		T432	6		T433	1
values[92]	76	1			T555	1		T432	8		T433	1
values[93]	99	1			T555	5		T432	7		T433	1
values[94]	103	1			T555	6		T432	3		T433	4
values[95]	83	1			T555	2		T432	4		T433	17
values[96]	84	1			T555	7		T432	11		T433	3
values[97]	75	1			T555	1		T432	9		T433	5
values[98]	81	1			T555	3		T432	5		T433	2
values[99]	79	1			T555	1		T432	3		T433	4
values[100]	82	1			T555	1		T432	2		T433	2
values[101]	86	1			T555	1		T432	4		T433	2
values[102]	90	1			T555	1		T432	1		T433	1
values[103]	81	1			T555	1		T432	4		T433	1
values[104]	74	1			T555	1		T432	4		T433	1
values[105]	65	1			T555	1		T432	4		T433	2
values[106]	80	1			T555	1		T432	2		T433	2
values[107]	80	1			T555	1		T432	1		T433	2
values[108]	81	1			T555	5		T432	4		T433	2
values[109]	72	1			T555	3		T432	4		T433	1
values[110]	61	1			T555	3		T432	3		T433	2
values[111]	73	1			T555	4		T432	4		T433	4
values[112]	74	1			T555	1		T432	8		T433	4
values[113]	96	1			T555	2		T433	2		T914	2
values[114]	70	1			T555	2		T433	1		T914	2
values[115]	75	1			T555	1		T433	2		T914	1
values[116]	83	1			T555	7		T433	2		T914	1
values[117]	88	1			T555	1		T433	4		T914	2
values[118]	83	1			T555	3		T433	1		T914	2
values[119]	65	1			T555	1		T433	1		T914	2
values[120]	62	1			T555	2		T433	1		T914	1
values[121]	66	1			T555	1		T433	1		T914	2
values[122]	68	1			T555	4		T433	2		T914	1
values[123]	75	1			T555	2		T433	1		T914	1
values[124]	93	1			T555	4		T433	3		T914	1
values[125]	70	1			T555	4		T433	2		T914	1
values[126]	119	1			T555	1		T433	2		T914	3
values[127]	843	1			T555	26		T433	29		T914	29
values[128]	7733	1			T555	305		T433	336		T914	276