Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.rom_ctrl__regs_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	145646	1			T73	392		T74	5		T78	14
values[2]	4394	1			T73	127		T74	1		T262	1
values[3]	2080	1			T73	49		T74	1		T557	1
values[4]	1533	1			T73	25		T836	1		T553	1
values[5]	1152	1			T73	18		T836	1		T553	1
values[6]	1035	1			T73	7		T836	1		T553	1
values[7]	900	1			T836	1		T553	1		T555	2
values[8]	766	1			T836	1		T553	1		T555	2
values[9]	560	1			T836	1		T553	1		T555	2
values[10]	467	1			T836	1		T553	1		T555	2
values[11]	438	1			T836	1		T553	1		T555	2
values[12]	436	1			T836	1		T553	1		T555	2
values[13]	448	1			T836	1		T553	1		T555	2
values[14]	435	1			T836	1		T553	1		T555	2
values[15]	345	1			T836	1		T553	1		T555	2
values[16]	373	1			T836	1		T553	1		T555	2
values[17]	316	1			T836	1		T553	1		T555	2
values[18]	302	1			T836	1		T553	1		T555	2
values[19]	221	1			T836	1		T553	1		T555	2
values[20]	250	1			T836	1		T553	1		T555	2
values[21]	314	1			T836	1		T553	1		T555	2
values[22]	284	1			T836	1		T553	1		T555	2
values[23]	217	1			T836	1		T553	1		T555	2
values[24]	150	1			T836	1		T553	1		T555	2
values[25]	119	1			T836	1		T553	1		T555	2
values[26]	125	1			T836	1		T553	1		T555	2
values[27]	101	1			T836	1		T553	1		T555	2
values[28]	102	1			T836	1		T553	1		T555	2
values[29]	122	1			T836	1		T553	1		T555	2
values[30]	122	1			T836	1		T553	1		T555	2
values[31]	108	1			T836	1		T553	1		T555	2
values[32]	82	1			T836	1		T553	1		T555	2
values[33]	85	1			T836	1		T553	1		T555	2
values[34]	83	1			T836	1		T553	1		T555	2
values[35]	109	1			T836	1		T553	1		T555	2
values[36]	138	1			T836	1		T553	1		T555	2
values[37]	113	1			T836	1		T553	1		T555	2
values[38]	97	1			T836	1		T553	1		T555	2
values[39]	92	1			T836	1		T553	1		T555	2
values[40]	96	1			T836	1		T553	1		T555	2
values[41]	106	1			T836	1		T553	2		T555	2
values[42]	84	1			T836	1		T553	1		T555	2
values[43]	80	1			T836	1		T553	1		T555	2
values[44]	58	1			T836	1		T553	1		T555	2
values[45]	73	1			T836	1		T553	1		T555	2
values[46]	88	1			T836	2		T553	1		T555	2
values[47]	75	1			T836	1		T553	1		T555	2
values[48]	71	1			T836	1		T553	1		T555	2
values[49]	53	1			T836	1		T553	1		T555	2
values[50]	40	1			T836	1		T553	1		T555	2
values[51]	40	1			T836	1		T553	1		T555	2
values[52]	56	1			T836	1		T553	1		T555	2
values[53]	56	1			T836	1		T553	1		T555	2
values[54]	54	1			T836	1		T553	1		T555	2
values[55]	44	1			T836	1		T553	1		T555	2
values[56]	46	1			T836	1		T553	1		T555	2
values[57]	61	1			T836	1		T553	1		T555	2
values[58]	62	1			T836	1		T553	1		T555	2
values[59]	64	1			T836	1		T553	1		T555	2
values[60]	49	1			T836	1		T553	1		T555	2
values[61]	51	1			T836	1		T553	1		T555	2
values[62]	50	1			T836	1		T553	1		T555	2
values[63]	77	1			T836	1		T553	1		T555	2
values[64]	50	1			T836	1		T553	1		T555	3
values[65]	43	1			T836	1		T553	1		T555	2
values[66]	50	1			T836	1		T553	1		T555	3
values[67]	41	1			T836	1		T553	1		T555	2
values[68]	31	1			T836	1		T553	1		T555	2
values[69]	35	1			T836	1		T553	1		T555	2
values[70]	37	1			T836	1		T553	1		T555	2
values[71]	34	1			T836	1		T553	1		T555	2
values[72]	37	1			T836	1		T553	1		T555	2
values[73]	35	1			T836	1		T553	1		T555	2
values[74]	41	1			T836	1		T553	1		T555	2
values[75]	39	1			T836	1		T553	1		T555	2
values[76]	35	1			T836	1		T553	1		T555	2
values[77]	39	1			T836	1		T553	1		T555	2
values[78]	34	1			T836	1		T553	1		T555	2
values[79]	32	1			T836	1		T553	1		T555	2
values[80]	49	1			T836	1		T553	1		T555	2
values[81]	48	1			T836	1		T553	1		T555	2
values[82]	47	1			T836	1		T553	1		T555	2
values[83]	49	1			T836	1		T553	1		T555	2
values[84]	43	1			T836	1		T553	1		T555	2
values[85]	45	1			T836	1		T553	1		T555	2
values[86]	47	1			T836	1		T553	1		T555	2
values[87]	55	1			T836	1		T553	1		T555	2
values[88]	65	1			T836	1		T553	1		T555	2
values[89]	61	1			T836	1		T553	1		T555	2
values[90]	49	1			T836	1		T553	1		T555	3
values[91]	56	1			T836	1		T553	1		T555	7
values[92]	48	1			T836	1		T553	1		T555	2
values[93]	69	1			T836	1		T553	1		T555	5
values[94]	51	1			T836	1		T553	1		T555	3
values[95]	51	1			T836	1		T553	1		T555	7
values[96]	61	1			T836	1		T553	1		T555	4
values[97]	49	1			T836	1		T553	1		T555	2
values[98]	67	1			T836	1		T553	1		T555	3
values[99]	57	1			T836	1		T553	1		T555	5
values[100]	60	1			T836	1		T553	1		T555	3
values[101]	66	1			T836	1		T553	1		T555	4
values[102]	48	1			T836	1		T553	1		T555	3
values[103]	55	1			T836	1		T553	1		T555	2
values[104]	61	1			T836	1		T553	1		T555	3
values[105]	58	1			T836	1		T553	1		T555	6
values[106]	77	1			T836	1		T553	1		T555	4
values[107]	75	1			T836	1		T553	1		T555	4
values[108]	70	1			T836	1		T553	1		T555	6
values[109]	73	1			T836	4		T553	1		T555	4
values[110]	70	1			T836	4		T553	1		T555	4
values[111]	73	1			T836	3		T553	1		T555	7
values[112]	65	1			T836	1		T553	1		T555	5
values[113]	69	1			T836	5		T553	1		T555	3
values[114]	68	1			T836	2		T553	1		T555	2
values[115]	70	1			T836	1		T553	1		T555	3
values[116]	71	1			T836	1		T553	2		T555	2
values[117]	72	1			T836	1		T553	6		T555	2
values[118]	73	1			T836	1		T553	3		T555	3
values[119]	79	1			T836	3		T553	2		T555	7
values[120]	70	1			T836	1		T553	5		T555	5
values[121]	58	1			T836	1		T553	2		T555	4
values[122]	65	1			T836	2		T553	1		T555	3
values[123]	105	1			T836	1		T553	1		T555	6
values[124]	164	1			T836	2		T553	3		T555	3
values[125]	333	1			T836	1		T553	1		T555	3
values[126]	693	1			T836	20		T553	14		T555	20
values[127]	2545	1			T836	124		T553	116		T555	199
values[128]	4431	1			T836	207		T553	253		T555	416