Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.rstmgr_aon_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	136302	1			T73	114		T74	6		T78	13
values[2]	9821	1			T73	1		T262	1		T549	1
values[3]	3688	1			T428	1		T555	1		T446	3
values[4]	2296	1			T555	1		T496	14		T770	3
values[5]	1501	1			T555	1		T496	7		T930	1
values[6]	1045	1			T555	1		T496	13		T930	1
values[7]	768	1			T555	1		T496	21		T930	1
values[8]	539	1			T555	1		T496	20		T930	1
values[9]	439	1			T555	1		T496	9		T930	1
values[10]	416	1			T555	1		T496	18		T930	1
values[11]	365	1			T555	1		T496	5		T930	1
values[12]	354	1			T555	1		T496	14		T930	1
values[13]	342	1			T555	1		T496	11		T930	1
values[14]	321	1			T555	1		T496	16		T930	1
values[15]	313	1			T555	1		T496	13		T930	1
values[16]	408	1			T555	1		T496	22		T930	1
values[17]	331	1			T555	1		T496	13		T930	1
values[18]	321	1			T555	1		T496	20		T930	1
values[19]	340	1			T555	1		T496	22		T930	1
values[20]	268	1			T555	1		T496	8		T930	1
values[21]	287	1			T555	1		T496	9		T930	1
values[22]	286	1			T555	1		T496	15		T930	1
values[23]	321	1			T555	1		T496	25		T930	1
values[24]	361	1			T555	1		T496	15		T930	1
values[25]	296	1			T555	1		T496	10		T930	1
values[26]	354	1			T555	1		T496	15		T930	1
values[27]	283	1			T555	1		T496	15		T930	1
values[28]	340	1			T555	1		T496	7		T930	1
values[29]	277	1			T555	1		T496	13		T930	1
values[30]	353	1			T555	1		T496	25		T930	1
values[31]	294	1			T555	1		T496	12		T930	1
values[32]	338	1			T555	1		T496	6		T930	1
values[33]	359	1			T555	1		T496	22		T930	1
values[34]	293	1			T555	1		T496	13		T930	1
values[35]	281	1			T555	1		T496	14		T930	1
values[36]	263	1			T555	1		T496	10		T930	1
values[37]	321	1			T555	1		T496	14		T930	1
values[38]	318	1			T555	1		T496	45		T930	1
values[39]	297	1			T555	1		T496	15		T930	1
values[40]	313	1			T555	1		T496	14		T930	1
values[41]	260	1			T555	1		T496	27		T930	1
values[42]	353	1			T555	1		T496	7		T930	1
values[43]	287	1			T555	1		T496	7		T930	1
values[44]	290	1			T555	1		T496	5		T930	1
values[45]	245	1			T555	1		T496	15		T930	1
values[46]	293	1			T555	1		T496	28		T930	1
values[47]	245	1			T555	1		T496	11		T930	1
values[48]	255	1			T555	1		T496	16		T930	1
values[49]	248	1			T555	1		T496	18		T930	1
values[50]	251	1			T555	1		T496	29		T930	1
values[51]	284	1			T555	1		T496	10		T930	1
values[52]	227	1			T555	1		T496	13		T930	1
values[53]	245	1			T555	1		T496	10		T930	1
values[54]	249	1			T555	1		T496	11		T930	1
values[55]	186	1			T555	1		T496	13		T930	1
values[56]	196	1			T555	1		T496	13		T930	1
values[57]	206	1			T555	1		T496	13		T930	1
values[58]	193	1			T555	1		T496	13		T930	1
values[59]	203	1			T555	1		T496	19		T930	1
values[60]	206	1			T555	1		T496	9		T930	1
values[61]	220	1			T555	1		T496	15		T930	1
values[62]	203	1			T555	1		T496	12		T930	1
values[63]	205	1			T555	1		T496	5		T930	1
values[64]	183	1			T555	1		T496	12		T930	1
values[65]	218	1			T555	1		T496	22		T930	1
values[66]	214	1			T555	1		T496	4		T930	1
values[67]	124	1			T555	1		T496	5		T930	1
values[68]	110	1			T555	1		T496	5		T930	1
values[69]	147	1			T555	1		T496	7		T930	1
values[70]	127	1			T555	1		T496	2		T930	1
values[71]	141	1			T555	1		T496	6		T930	1
values[72]	134	1			T555	1		T496	5		T930	1
values[73]	94	1			T555	1		T930	1		T458	1
values[74]	85	1			T555	1		T930	1		T458	1
values[75]	89	1			T555	1		T930	1		T458	1
values[76]	129	1			T555	1		T930	1		T458	1
values[77]	119	1			T555	1		T930	1		T458	1
values[78]	92	1			T555	1		T930	1		T458	1
values[79]	92	1			T555	1		T930	1		T458	1
values[80]	120	1			T555	1		T930	1		T458	1
values[81]	111	1			T555	1		T930	1		T458	1
values[82]	107	1			T555	1		T930	1		T458	2
values[83]	92	1			T555	1		T930	1		T458	1
values[84]	87	1			T555	1		T930	1		T458	1
values[85]	97	1			T555	1		T930	1		T458	1
values[86]	114	1			T555	1		T930	1		T458	1
values[87]	123	1			T555	1		T930	1		T458	1
values[88]	95	1			T555	1		T930	1		T458	1
values[89]	77	1			T555	1		T930	1		T458	1
values[90]	63	1			T555	1		T930	1		T458	1
values[91]	83	1			T555	1		T930	1		T458	1
values[92]	93	1			T555	1		T930	1		T458	1
values[93]	81	1			T555	1		T930	1		T458	1
values[94]	81	1			T555	1		T930	1		T458	1
values[95]	86	1			T555	1		T930	1		T458	1
values[96]	92	1			T555	1		T930	1		T458	1
values[97]	74	1			T555	1		T930	1		T458	1
values[98]	90	1			T555	2		T930	1		T458	1
values[99]	86	1			T555	12		T930	1		T458	1
values[100]	78	1			T555	2		T930	1		T458	1
values[101]	97	1			T555	1		T930	1		T458	1
values[102]	75	1			T555	2		T930	1		T458	1
values[103]	69	1			T555	2		T930	1		T458	1
values[104]	90	1			T555	1		T930	1		T458	1
values[105]	99	1			T555	5		T930	1		T458	1
values[106]	92	1			T555	10		T930	1		T458	1
values[107]	79	1			T555	6		T930	1		T458	1
values[108]	65	1			T555	1		T930	1		T458	1
values[109]	73	1			T555	1		T930	1		T458	1
values[110]	83	1			T555	2		T930	1		T458	1
values[111]	66	1			T555	1		T930	1		T458	1
values[112]	79	1			T555	1		T930	4		T458	1
values[113]	69	1			T555	1		T930	1		T458	1
values[114]	75	1			T555	3		T930	3		T458	1
values[115]	91	1			T555	4		T930	7		T458	1
values[116]	72	1			T555	4		T930	3		T458	1
values[117]	64	1			T555	3		T930	2		T458	1
values[118]	78	1			T555	2		T930	1		T458	1
values[119]	72	1			T555	2		T930	1		T458	1
values[120]	63	1			T555	1		T930	1		T458	1
values[121]	70	1			T555	2		T930	1		T458	1
values[122]	57	1			T555	2		T930	1		T458	1
values[123]	47	1			T555	1		T930	1		T458	2
values[124]	60	1			T555	2		T930	2		T458	1
values[125]	75	1			T555	1		T930	5		T458	1
values[126]	105	1			T555	3		T930	2		T458	3
values[127]	810	1			T555	34		T930	35		T458	34
values[128]	6879	1			T555	335		T930	293		T458	370