Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.spi_device_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	134374	1			T73	200		T78	24		T125	59
values[2]	9730	1			T73	33		T548	1		T549	1
values[3]	3476	1			T73	5		T548	1		T561	1
values[4]	2040	1			T73	4		T548	1		T551	10
values[5]	1257	1			T548	1		T551	5		T770	11
values[6]	864	1			T548	1		T551	9		T770	4
values[7]	696	1			T548	1		T551	11		T816	2
values[8]	554	1			T548	1		T551	9		T910	1
values[9]	503	1			T548	1		T551	6		T910	1
values[10]	497	1			T548	1		T551	9		T910	1
values[11]	415	1			T548	1		T551	5		T910	1
values[12]	383	1			T548	2		T551	2		T910	1
values[13]	392	1			T548	1		T551	7		T910	1
values[14]	377	1			T548	1		T551	12		T910	1
values[15]	324	1			T548	1		T551	7		T910	1
values[16]	371	1			T548	1		T551	7		T910	1
values[17]	353	1			T548	1		T551	11		T910	1
values[18]	354	1			T548	1		T551	7		T910	1
values[19]	299	1			T548	1		T551	8		T910	1
values[20]	343	1			T548	1		T551	8		T910	1
values[21]	337	1			T548	1		T551	8		T910	1
values[22]	346	1			T548	1		T551	7		T910	1
values[23]	308	1			T548	1		T551	10		T910	1
values[24]	292	1			T548	1		T551	13		T910	1
values[25]	326	1			T548	1		T551	5		T910	1
values[26]	320	1			T548	1		T551	14		T910	1
values[27]	301	1			T548	1		T551	8		T910	1
values[28]	285	1			T548	1		T551	5		T910	1
values[29]	321	1			T548	1		T551	7		T910	1
values[30]	303	1			T548	1		T551	7		T910	1
values[31]	287	1			T548	1		T551	4		T910	1
values[32]	330	1			T548	1		T551	3		T910	1
values[33]	313	1			T548	1		T551	11		T910	1
values[34]	326	1			T548	1		T551	14		T910	1
values[35]	337	1			T548	1		T551	16		T910	1
values[36]	265	1			T548	1		T551	3		T910	1
values[37]	314	1			T548	1		T551	13		T910	1
values[38]	295	1			T548	1		T551	5		T910	1
values[39]	280	1			T548	1		T551	10		T910	1
values[40]	266	1			T548	1		T551	14		T910	1
values[41]	250	1			T548	1		T551	4		T910	1
values[42]	269	1			T548	1		T551	5		T910	1
values[43]	245	1			T548	1		T551	5		T910	1
values[44]	237	1			T548	1		T551	3		T910	1
values[45]	259	1			T548	1		T551	4		T910	1
values[46]	243	1			T548	1		T551	12		T910	1
values[47]	251	1			T548	1		T551	4		T910	1
values[48]	254	1			T548	1		T551	5		T910	1
values[49]	244	1			T548	1		T551	9		T910	1
values[50]	264	1			T548	1		T551	8		T910	1
values[51]	241	1			T548	1		T551	12		T910	1
values[52]	207	1			T548	1		T551	3		T910	1
values[53]	274	1			T548	1		T551	11		T910	1
values[54]	246	1			T548	1		T551	7		T910	1
values[55]	271	1			T548	1		T551	4		T910	1
values[56]	191	1			T548	1		T551	3		T910	1
values[57]	178	1			T548	1		T551	6		T910	1
values[58]	176	1			T548	1		T551	5		T910	1
values[59]	236	1			T548	1		T551	4		T910	1
values[60]	231	1			T548	1		T551	4		T910	1
values[61]	182	1			T548	1		T551	3		T910	1
values[62]	174	1			T548	1		T551	6		T910	1
values[63]	171	1			T548	1		T551	3		T910	1
values[64]	216	1			T548	1		T551	37		T910	1
values[65]	161	1			T548	1		T551	2		T910	1
values[66]	145	1			T548	1		T910	1		T517	6
values[67]	132	1			T548	1		T910	1		T517	5
values[68]	131	1			T548	1		T910	1		T517	3
values[69]	148	1			T548	1		T910	1		T915	1
values[70]	131	1			T548	2		T910	1		T915	1
values[71]	133	1			T548	1		T910	1		T915	1
values[72]	160	1			T548	1		T910	1		T915	1
values[73]	157	1			T548	1		T910	1		T915	1
values[74]	132	1			T548	1		T910	1		T915	1
values[75]	123	1			T548	1		T910	1		T915	1
values[76]	131	1			T548	1		T910	1		T915	1
values[77]	129	1			T548	1		T910	1		T915	1
values[78]	117	1			T548	1		T910	1		T915	1
values[79]	111	1			T548	1		T910	1		T915	1
values[80]	112	1			T548	1		T910	1		T915	1
values[81]	124	1			T548	1		T910	1		T915	2
values[82]	110	1			T548	1		T910	1		T915	4
values[83]	125	1			T548	1		T910	1		T915	5
values[84]	119	1			T548	1		T910	1		T915	4
values[85]	95	1			T548	1		T910	1		T915	5
values[86]	115	1			T548	1		T910	1		T915	1
values[87]	117	1			T548	1		T910	1		T915	2
values[88]	105	1			T548	1		T910	1		T915	2
values[89]	121	1			T548	1		T910	1		T915	1
values[90]	121	1			T548	1		T910	1		T915	1
values[91]	127	1			T548	1		T910	1		T915	2
values[92]	144	1			T548	1		T910	1		T915	9
values[93]	117	1			T548	1		T910	1		T915	3
values[94]	105	1			T548	1		T910	1		T915	1
values[95]	121	1			T548	1		T910	1		T915	4
values[96]	116	1			T548	1		T910	1		T915	6
values[97]	111	1			T548	1		T910	1		T915	3
values[98]	84	1			T548	1		T910	1		T915	2
values[99]	107	1			T548	1		T910	1		T915	9
values[100]	108	1			T548	1		T910	1		T915	3
values[101]	97	1			T548	1		T910	1		T915	1
values[102]	108	1			T548	1		T910	1		T915	5
values[103]	113	1			T548	1		T910	1		T915	1
values[104]	105	1			T548	1		T910	1		T915	1
values[105]	125	1			T548	1		T910	1		T915	4
values[106]	119	1			T548	1		T910	3		T915	2
values[107]	94	1			T548	1		T910	1		T915	1
values[108]	77	1			T548	1		T910	2		T915	1
values[109]	100	1			T548	1		T910	3		T915	1
values[110]	95	1			T548	1		T910	3		T915	1
values[111]	67	1			T548	1		T910	2		T915	2
values[112]	81	1			T548	1		T910	2		T915	3
values[113]	82	1			T548	1		T910	2		T915	2
values[114]	81	1			T548	1		T910	3		T915	1
values[115]	76	1			T548	1		T910	1		T915	6
values[116]	97	1			T548	1		T910	3		T915	3
values[117]	75	1			T548	1		T910	1		T915	1
values[118]	93	1			T548	1		T910	2		T915	2
values[119]	79	1			T548	1		T910	2		T915	2
values[120]	75	1			T548	1		T910	2		T915	3
values[121]	88	1			T548	1		T910	2		T915	2
values[122]	59	1			T548	1		T910	3		T915	2
values[123]	67	1			T548	1		T910	3		T915	3
values[124]	99	1			T548	3		T910	5		T915	3
values[125]	83	1			T548	2		T910	1		T915	2
values[126]	191	1			T548	7		T910	1		T915	4
values[127]	1049	1			T548	38		T910	29		T915	28
values[128]	7860	1			T548	317		T910	311		T915	261