Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_ret_aon__ram_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	134662	1			T73	130		T74	2		T78	17
values[2]	10459	1			T73	4		T125	69		T262	2
values[3]	4447	1			T125	13		T553	1		T562	1
values[4]	2766	1			T125	5		T553	1		T562	1
values[5]	1889	1			T125	2		T553	1		T562	1
values[6]	1257	1			T553	1		T562	1		T496	6
values[7]	886	1			T553	1		T562	1		T496	6
values[8]	609	1			T553	1		T562	1		T496	8
values[9]	511	1			T553	1		T562	2		T496	9
values[10]	443	1			T553	1		T562	1		T496	12
values[11]	315	1			T553	1		T562	1		T496	5
values[12]	288	1			T553	1		T562	1		T496	10
values[13]	347	1			T553	1		T562	1		T496	11
values[14]	255	1			T553	1		T562	1		T496	5
values[15]	280	1			T553	1		T562	1		T496	6
values[16]	314	1			T553	1		T562	1		T496	10
values[17]	276	1			T553	1		T562	1		T496	10
values[18]	278	1			T553	1		T562	1		T496	3
values[19]	251	1			T553	1		T562	1		T496	4
values[20]	287	1			T553	1		T562	1		T496	3
values[21]	289	1			T553	1		T562	1		T496	5
values[22]	284	1			T553	1		T562	1		T496	23
values[23]	206	1			T553	1		T562	1		T496	9
values[24]	237	1			T553	1		T562	1		T496	3
values[25]	203	1			T553	1		T562	1		T496	3
values[26]	239	1			T553	1		T562	1		T496	13
values[27]	255	1			T553	1		T562	1		T496	6
values[28]	290	1			T553	1		T562	1		T496	3
values[29]	240	1			T553	1		T562	1		T496	6
values[30]	254	1			T553	1		T562	1		T496	5
values[31]	223	1			T553	1		T562	1		T496	6
values[32]	227	1			T553	1		T562	1		T496	13
values[33]	238	1			T553	1		T562	1		T496	14
values[34]	235	1			T553	1		T562	1		T496	4
values[35]	264	1			T553	1		T562	1		T496	3
values[36]	232	1			T553	1		T562	1		T496	8
values[37]	228	1			T553	1		T562	1		T496	7
values[38]	234	1			T553	1		T562	1		T496	9
values[39]	252	1			T553	1		T562	1		T496	3
values[40]	247	1			T553	1		T562	1		T496	5
values[41]	224	1			T553	1		T562	1		T496	6
values[42]	278	1			T553	1		T562	1		T496	7
values[43]	234	1			T553	1		T562	1		T496	3
values[44]	226	1			T553	1		T562	1		T496	23
values[45]	244	1			T553	1		T562	1		T496	21
values[46]	209	1			T553	1		T562	1		T496	8
values[47]	195	1			T553	1		T562	1		T496	7
values[48]	247	1			T553	1		T562	1		T496	6
values[49]	220	1			T553	1		T562	1		T496	9
values[50]	230	1			T553	1		T562	1		T496	26
values[51]	162	1			T553	1		T562	1		T496	7
values[52]	255	1			T553	1		T562	1		T496	12
values[53]	231	1			T553	1		T562	2		T496	2
values[54]	243	1			T553	1		T562	1		T496	7
values[55]	207	1			T553	1		T562	1		T496	7
values[56]	170	1			T553	1		T562	1		T496	5
values[57]	153	1			T553	1		T562	1		T496	4
values[58]	190	1			T553	1		T562	1		T496	5
values[59]	196	1			T553	1		T562	1		T496	14
values[60]	196	1			T553	1		T562	1		T496	6
values[61]	145	1			T553	1		T562	1		T496	8
values[62]	146	1			T553	1		T562	1		T496	10
values[63]	144	1			T553	1		T562	2		T496	11
values[64]	135	1			T553	1		T562	1		T496	2
values[65]	143	1			T553	1		T562	1		T517	7
values[66]	120	1			T553	1		T562	1		T517	8
values[67]	152	1			T553	1		T562	1		T501	1
values[68]	117	1			T553	1		T562	1		T501	6
values[69]	150	1			T553	1		T562	1		T501	3
values[70]	95	1			T553	1		T562	1		T501	5
values[71]	95	1			T553	1		T562	1		T501	5
values[72]	97	1			T553	1		T562	1		T501	2
values[73]	87	1			T553	1		T562	1		T501	2
values[74]	85	1			T553	1		T562	1		T501	1
values[75]	71	1			T553	1		T562	1		T501	13
values[76]	67	1			T553	1		T562	1		T501	18
values[77]	60	1			T553	1		T562	1		T501	4
values[78]	59	1			T553	1		T562	1		T501	5
values[79]	53	1			T553	1		T562	1		T501	8
values[80]	50	1			T553	1		T562	1		T501	7
values[81]	43	1			T553	1		T562	1		T501	7
values[82]	48	1			T553	1		T562	1		T501	5
values[83]	68	1			T553	1		T562	1		T501	19
values[84]	63	1			T553	1		T562	2		T501	8
values[85]	61	1			T553	1		T562	1		T501	7
values[86]	61	1			T553	1		T562	1		T501	5
values[87]	58	1			T553	1		T562	1		T501	6
values[88]	76	1			T553	1		T562	1		T501	13
values[89]	76	1			T553	1		T562	1		T501	4
values[90]	71	1			T553	1		T562	1		T501	3
values[91]	55	1			T553	1		T562	1		T501	2
values[92]	67	1			T553	1		T562	1		T501	15
values[93]	53	1			T553	1		T562	1		T501	10
values[94]	68	1			T553	1		T562	1		T501	3
values[95]	74	1			T553	1		T562	1		T501	3
values[96]	84	1			T553	1		T562	1		T501	1
values[97]	64	1			T553	1		T562	1		T501	7
values[98]	69	1			T553	1		T562	1		T501	6
values[99]	73	1			T553	3		T562	1		T501	11
values[100]	73	1			T553	3		T562	1		T501	14
values[101]	67	1			T553	2		T562	1		T501	7
values[102]	66	1			T553	2		T562	1		T501	2
values[103]	65	1			T553	3		T562	1		T501	4
values[104]	78	1			T553	1		T562	1		T501	4
values[105]	83	1			T553	2		T562	1		T501	3
values[106]	81	1			T553	5		T562	1		T501	4
values[107]	65	1			T553	5		T562	1		T501	1
values[108]	52	1			T553	2		T562	1		T501	3
values[109]	61	1			T553	3		T562	1		T501	7
values[110]	75	1			T553	1		T562	1		T501	4
values[111]	79	1			T553	1		T562	1		T501	3
values[112]	66	1			T553	3		T562	1		T501	9
values[113]	64	1			T553	1		T562	1		T501	4
values[114]	52	1			T553	1		T562	1		T501	2
values[115]	75	1			T553	2		T562	1		T501	2
values[116]	64	1			T553	3		T562	1		T501	9
values[117]	65	1			T553	2		T562	1		T501	5
values[118]	63	1			T553	2		T562	1		T501	3
values[119]	68	1			T553	1		T562	1		T501	2
values[120]	72	1			T553	1		T562	1		T501	3
values[121]	73	1			T553	1		T562	1		T501	1
values[122]	62	1			T553	1		T562	6		T501	4
values[123]	55	1			T553	1		T562	1		T501	2
values[124]	66	1			T553	1		T562	3		T501	6
values[125]	79	1			T553	1		T562	2		T501	5
values[126]	112	1			T553	2		T562	4		T501	1
values[127]	717	1			T553	24		T562	17		T922	15
values[128]	5752	1			T553	281		T562	327		T922	7